gth.h 2.1 KB

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  1. /*
  2. * Intel(R) Trace Hub Global Trace Hub (GTH) data structures
  3. *
  4. * Copyright (C) 2014-2015 Intel Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. */
  15. #ifndef __INTEL_TH_GTH_H__
  16. #define __INTEL_TH_GTH_H__
  17. /* Map output port parameter bits to symbolic names */
  18. #define TH_OUTPUT_PARM(name) \
  19. TH_OUTPUT_ ## name
  20. enum intel_th_output_parm {
  21. /* output port type */
  22. TH_OUTPUT_PARM(port),
  23. /* generate NULL packet */
  24. TH_OUTPUT_PARM(null),
  25. /* packet drop */
  26. TH_OUTPUT_PARM(drop),
  27. /* port in reset state */
  28. TH_OUTPUT_PARM(reset),
  29. /* flush out data */
  30. TH_OUTPUT_PARM(flush),
  31. /* mainenance packet frequency */
  32. TH_OUTPUT_PARM(smcfreq),
  33. };
  34. /*
  35. * Register offsets
  36. */
  37. enum {
  38. REG_GTH_GTHOPT0 = 0x00, /* Output ports 0..3 config */
  39. REG_GTH_GTHOPT1 = 0x04, /* Output ports 4..7 config */
  40. REG_GTH_SWDEST0 = 0x08, /* Switching destination masters 0..7 */
  41. REG_GTH_GSWTDEST = 0x88, /* Global sw trace destination */
  42. REG_GTH_SMCR0 = 0x9c, /* STP mainenance for ports 0/1 */
  43. REG_GTH_SMCR1 = 0xa0, /* STP mainenance for ports 2/3 */
  44. REG_GTH_SMCR2 = 0xa4, /* STP mainenance for ports 4/5 */
  45. REG_GTH_SMCR3 = 0xa8, /* STP mainenance for ports 6/7 */
  46. REG_GTH_SCR = 0xc8, /* Source control (storeEn override) */
  47. REG_GTH_STAT = 0xd4, /* GTH status */
  48. REG_GTH_SCR2 = 0xd8, /* Source control (force storeEn off) */
  49. REG_GTH_DESTOVR = 0xdc, /* Destination override */
  50. REG_GTH_SCRPD0 = 0xe0, /* ScratchPad[0] */
  51. REG_GTH_SCRPD1 = 0xe4, /* ScratchPad[1] */
  52. REG_GTH_SCRPD2 = 0xe8, /* ScratchPad[2] */
  53. REG_GTH_SCRPD3 = 0xec, /* ScratchPad[3] */
  54. };
  55. /* Externall debugger is using Intel TH */
  56. #define SCRPD_DEBUGGER_IN_USE BIT(24)
  57. /* waiting for Pipeline Empty bit(s) to assert for GTH */
  58. #define GTH_PLE_WAITLOOP_DEPTH 10000
  59. #endif /* __INTEL_TH_GTH_H__ */