i2c-designware-pcidrv.c 8.0 KB

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  1. /*
  2. * Synopsys DesignWare I2C adapter driver (master only).
  3. *
  4. * Based on the TI DAVINCI I2C adapter driver.
  5. *
  6. * Copyright (C) 2006 Texas Instruments.
  7. * Copyright (C) 2007 MontaVista Software Inc.
  8. * Copyright (C) 2009 Provigent Ltd.
  9. * Copyright (C) 2011, 2015 Intel Corporation.
  10. *
  11. * ----------------------------------------------------------------------------
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License as published by
  15. * the Free Software Foundation; either version 2 of the License, or
  16. * (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. * ----------------------------------------------------------------------------
  23. *
  24. */
  25. #include <linux/kernel.h>
  26. #include <linux/module.h>
  27. #include <linux/delay.h>
  28. #include <linux/i2c.h>
  29. #include <linux/errno.h>
  30. #include <linux/sched.h>
  31. #include <linux/err.h>
  32. #include <linux/interrupt.h>
  33. #include <linux/io.h>
  34. #include <linux/slab.h>
  35. #include <linux/pci.h>
  36. #include <linux/pm_runtime.h>
  37. #include <linux/acpi.h>
  38. #include "i2c-designware-core.h"
  39. #define DRIVER_NAME "i2c-designware-pci"
  40. enum dw_pci_ctl_id_t {
  41. medfield_0,
  42. medfield_1,
  43. medfield_2,
  44. medfield_3,
  45. medfield_4,
  46. medfield_5,
  47. baytrail,
  48. haswell,
  49. };
  50. struct dw_scl_sda_cfg {
  51. u32 ss_hcnt;
  52. u32 fs_hcnt;
  53. u32 ss_lcnt;
  54. u32 fs_lcnt;
  55. u32 sda_hold;
  56. };
  57. struct dw_pci_controller {
  58. u32 bus_num;
  59. u32 bus_cfg;
  60. u32 tx_fifo_depth;
  61. u32 rx_fifo_depth;
  62. u32 clk_khz;
  63. u32 functionality;
  64. struct dw_scl_sda_cfg *scl_sda_cfg;
  65. };
  66. #define INTEL_MID_STD_CFG (DW_IC_CON_MASTER | \
  67. DW_IC_CON_SLAVE_DISABLE | \
  68. DW_IC_CON_RESTART_EN)
  69. #define DW_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \
  70. I2C_FUNC_SMBUS_BYTE | \
  71. I2C_FUNC_SMBUS_BYTE_DATA | \
  72. I2C_FUNC_SMBUS_WORD_DATA | \
  73. I2C_FUNC_SMBUS_I2C_BLOCK)
  74. /* BayTrail HCNT/LCNT/SDA hold time */
  75. static struct dw_scl_sda_cfg byt_config = {
  76. .ss_hcnt = 0x200,
  77. .fs_hcnt = 0x55,
  78. .ss_lcnt = 0x200,
  79. .fs_lcnt = 0x99,
  80. .sda_hold = 0x6,
  81. };
  82. /* Haswell HCNT/LCNT/SDA hold time */
  83. static struct dw_scl_sda_cfg hsw_config = {
  84. .ss_hcnt = 0x01b0,
  85. .fs_hcnt = 0x48,
  86. .ss_lcnt = 0x01fb,
  87. .fs_lcnt = 0xa0,
  88. .sda_hold = 0x9,
  89. };
  90. static struct dw_pci_controller dw_pci_controllers[] = {
  91. [medfield_0] = {
  92. .bus_num = 0,
  93. .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
  94. .tx_fifo_depth = 32,
  95. .rx_fifo_depth = 32,
  96. .clk_khz = 25000,
  97. },
  98. [medfield_1] = {
  99. .bus_num = 1,
  100. .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
  101. .tx_fifo_depth = 32,
  102. .rx_fifo_depth = 32,
  103. .clk_khz = 25000,
  104. },
  105. [medfield_2] = {
  106. .bus_num = 2,
  107. .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
  108. .tx_fifo_depth = 32,
  109. .rx_fifo_depth = 32,
  110. .clk_khz = 25000,
  111. },
  112. [medfield_3] = {
  113. .bus_num = 3,
  114. .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_STD,
  115. .tx_fifo_depth = 32,
  116. .rx_fifo_depth = 32,
  117. .clk_khz = 25000,
  118. },
  119. [medfield_4] = {
  120. .bus_num = 4,
  121. .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
  122. .tx_fifo_depth = 32,
  123. .rx_fifo_depth = 32,
  124. .clk_khz = 25000,
  125. },
  126. [medfield_5] = {
  127. .bus_num = 5,
  128. .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
  129. .tx_fifo_depth = 32,
  130. .rx_fifo_depth = 32,
  131. .clk_khz = 25000,
  132. },
  133. [baytrail] = {
  134. .bus_num = -1,
  135. .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
  136. .tx_fifo_depth = 32,
  137. .rx_fifo_depth = 32,
  138. .functionality = I2C_FUNC_10BIT_ADDR,
  139. .scl_sda_cfg = &byt_config,
  140. },
  141. [haswell] = {
  142. .bus_num = -1,
  143. .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
  144. .tx_fifo_depth = 32,
  145. .rx_fifo_depth = 32,
  146. .functionality = I2C_FUNC_10BIT_ADDR,
  147. .scl_sda_cfg = &hsw_config,
  148. },
  149. };
  150. #ifdef CONFIG_PM
  151. static int i2c_dw_pci_suspend(struct device *dev)
  152. {
  153. struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
  154. i2c_dw_disable(pci_get_drvdata(pdev));
  155. return 0;
  156. }
  157. static int i2c_dw_pci_resume(struct device *dev)
  158. {
  159. struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
  160. return i2c_dw_init(pci_get_drvdata(pdev));
  161. }
  162. #endif
  163. static UNIVERSAL_DEV_PM_OPS(i2c_dw_pm_ops, i2c_dw_pci_suspend,
  164. i2c_dw_pci_resume, NULL);
  165. static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev)
  166. {
  167. return dev->controller->clk_khz;
  168. }
  169. static int i2c_dw_pci_probe(struct pci_dev *pdev,
  170. const struct pci_device_id *id)
  171. {
  172. struct dw_i2c_dev *dev;
  173. struct i2c_adapter *adap;
  174. int r;
  175. struct dw_pci_controller *controller;
  176. struct dw_scl_sda_cfg *cfg;
  177. if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers)) {
  178. dev_err(&pdev->dev, "%s: invalid driver data %ld\n", __func__,
  179. id->driver_data);
  180. return -EINVAL;
  181. }
  182. controller = &dw_pci_controllers[id->driver_data];
  183. r = pcim_enable_device(pdev);
  184. if (r) {
  185. dev_err(&pdev->dev, "Failed to enable I2C PCI device (%d)\n",
  186. r);
  187. return r;
  188. }
  189. r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
  190. if (r) {
  191. dev_err(&pdev->dev, "I/O memory remapping failed\n");
  192. return r;
  193. }
  194. dev = devm_kzalloc(&pdev->dev, sizeof(struct dw_i2c_dev), GFP_KERNEL);
  195. if (!dev)
  196. return -ENOMEM;
  197. dev->clk = NULL;
  198. dev->controller = controller;
  199. dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
  200. dev->base = pcim_iomap_table(pdev)[0];
  201. dev->dev = &pdev->dev;
  202. dev->irq = pdev->irq;
  203. dev->functionality = controller->functionality |
  204. DW_DEFAULT_FUNCTIONALITY;
  205. dev->master_cfg = controller->bus_cfg;
  206. if (controller->scl_sda_cfg) {
  207. cfg = controller->scl_sda_cfg;
  208. dev->ss_hcnt = cfg->ss_hcnt;
  209. dev->fs_hcnt = cfg->fs_hcnt;
  210. dev->ss_lcnt = cfg->ss_lcnt;
  211. dev->fs_lcnt = cfg->fs_lcnt;
  212. dev->sda_hold_time = cfg->sda_hold;
  213. }
  214. pci_set_drvdata(pdev, dev);
  215. dev->tx_fifo_depth = controller->tx_fifo_depth;
  216. dev->rx_fifo_depth = controller->rx_fifo_depth;
  217. adap = &dev->adapter;
  218. adap->owner = THIS_MODULE;
  219. adap->class = 0;
  220. ACPI_COMPANION_SET(&adap->dev, ACPI_COMPANION(&pdev->dev));
  221. adap->nr = controller->bus_num;
  222. r = i2c_dw_probe(dev);
  223. if (r)
  224. return r;
  225. pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
  226. pm_runtime_use_autosuspend(&pdev->dev);
  227. pm_runtime_put_autosuspend(&pdev->dev);
  228. pm_runtime_allow(&pdev->dev);
  229. return 0;
  230. }
  231. static void i2c_dw_pci_remove(struct pci_dev *pdev)
  232. {
  233. struct dw_i2c_dev *dev = pci_get_drvdata(pdev);
  234. i2c_dw_disable(dev);
  235. pm_runtime_forbid(&pdev->dev);
  236. pm_runtime_get_noresume(&pdev->dev);
  237. i2c_del_adapter(&dev->adapter);
  238. }
  239. /* work with hotplug and coldplug */
  240. MODULE_ALIAS("i2c_designware-pci");
  241. static const struct pci_device_id i2_designware_pci_ids[] = {
  242. /* Medfield */
  243. { PCI_VDEVICE(INTEL, 0x0817), medfield_3 },
  244. { PCI_VDEVICE(INTEL, 0x0818), medfield_4 },
  245. { PCI_VDEVICE(INTEL, 0x0819), medfield_5 },
  246. { PCI_VDEVICE(INTEL, 0x082C), medfield_0 },
  247. { PCI_VDEVICE(INTEL, 0x082D), medfield_1 },
  248. { PCI_VDEVICE(INTEL, 0x082E), medfield_2 },
  249. /* Baytrail */
  250. { PCI_VDEVICE(INTEL, 0x0F41), baytrail },
  251. { PCI_VDEVICE(INTEL, 0x0F42), baytrail },
  252. { PCI_VDEVICE(INTEL, 0x0F43), baytrail },
  253. { PCI_VDEVICE(INTEL, 0x0F44), baytrail },
  254. { PCI_VDEVICE(INTEL, 0x0F45), baytrail },
  255. { PCI_VDEVICE(INTEL, 0x0F46), baytrail },
  256. { PCI_VDEVICE(INTEL, 0x0F47), baytrail },
  257. /* Haswell */
  258. { PCI_VDEVICE(INTEL, 0x9c61), haswell },
  259. { PCI_VDEVICE(INTEL, 0x9c62), haswell },
  260. /* Braswell / Cherrytrail */
  261. { PCI_VDEVICE(INTEL, 0x22C1), baytrail },
  262. { PCI_VDEVICE(INTEL, 0x22C2), baytrail },
  263. { PCI_VDEVICE(INTEL, 0x22C3), baytrail },
  264. { PCI_VDEVICE(INTEL, 0x22C4), baytrail },
  265. { PCI_VDEVICE(INTEL, 0x22C5), baytrail },
  266. { PCI_VDEVICE(INTEL, 0x22C6), baytrail },
  267. { PCI_VDEVICE(INTEL, 0x22C7), baytrail },
  268. { 0,}
  269. };
  270. MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);
  271. static struct pci_driver dw_i2c_driver = {
  272. .name = DRIVER_NAME,
  273. .id_table = i2_designware_pci_ids,
  274. .probe = i2c_dw_pci_probe,
  275. .remove = i2c_dw_pci_remove,
  276. .driver = {
  277. .pm = &i2c_dw_pm_ops,
  278. },
  279. };
  280. module_pci_driver(dw_i2c_driver);
  281. MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
  282. MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter");
  283. MODULE_LICENSE("GPL");