i2c-pasemi.c 10 KB

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  1. /*
  2. * Copyright (C) 2006-2007 PA Semi, Inc
  3. *
  4. * SMBus host driver for PA Semi PWRficient
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/module.h>
  16. #include <linux/pci.h>
  17. #include <linux/kernel.h>
  18. #include <linux/stddef.h>
  19. #include <linux/sched.h>
  20. #include <linux/i2c.h>
  21. #include <linux/delay.h>
  22. #include <linux/slab.h>
  23. #include <linux/io.h>
  24. static struct pci_driver pasemi_smb_driver;
  25. struct pasemi_smbus {
  26. struct pci_dev *dev;
  27. struct i2c_adapter adapter;
  28. unsigned long base;
  29. int size;
  30. };
  31. /* Register offsets */
  32. #define REG_MTXFIFO 0x00
  33. #define REG_MRXFIFO 0x04
  34. #define REG_SMSTA 0x14
  35. #define REG_CTL 0x1c
  36. /* Register defs */
  37. #define MTXFIFO_READ 0x00000400
  38. #define MTXFIFO_STOP 0x00000200
  39. #define MTXFIFO_START 0x00000100
  40. #define MTXFIFO_DATA_M 0x000000ff
  41. #define MRXFIFO_EMPTY 0x00000100
  42. #define MRXFIFO_DATA_M 0x000000ff
  43. #define SMSTA_XEN 0x08000000
  44. #define SMSTA_MTN 0x00200000
  45. #define CTL_MRR 0x00000400
  46. #define CTL_MTR 0x00000200
  47. #define CTL_CLK_M 0x000000ff
  48. #define CLK_100K_DIV 84
  49. #define CLK_400K_DIV 21
  50. static inline void reg_write(struct pasemi_smbus *smbus, int reg, int val)
  51. {
  52. dev_dbg(&smbus->dev->dev, "smbus write reg %lx val %08x\n",
  53. smbus->base + reg, val);
  54. outl(val, smbus->base + reg);
  55. }
  56. static inline int reg_read(struct pasemi_smbus *smbus, int reg)
  57. {
  58. int ret;
  59. ret = inl(smbus->base + reg);
  60. dev_dbg(&smbus->dev->dev, "smbus read reg %lx val %08x\n",
  61. smbus->base + reg, ret);
  62. return ret;
  63. }
  64. #define TXFIFO_WR(smbus, reg) reg_write((smbus), REG_MTXFIFO, (reg))
  65. #define RXFIFO_RD(smbus) reg_read((smbus), REG_MRXFIFO)
  66. static void pasemi_smb_clear(struct pasemi_smbus *smbus)
  67. {
  68. unsigned int status;
  69. status = reg_read(smbus, REG_SMSTA);
  70. reg_write(smbus, REG_SMSTA, status);
  71. }
  72. static int pasemi_smb_waitready(struct pasemi_smbus *smbus)
  73. {
  74. int timeout = 10;
  75. unsigned int status;
  76. status = reg_read(smbus, REG_SMSTA);
  77. while (!(status & SMSTA_XEN) && timeout--) {
  78. msleep(1);
  79. status = reg_read(smbus, REG_SMSTA);
  80. }
  81. /* Got NACK? */
  82. if (status & SMSTA_MTN)
  83. return -ENXIO;
  84. if (timeout < 0) {
  85. dev_warn(&smbus->dev->dev, "Timeout, status 0x%08x\n", status);
  86. reg_write(smbus, REG_SMSTA, status);
  87. return -ETIME;
  88. }
  89. /* Clear XEN */
  90. reg_write(smbus, REG_SMSTA, SMSTA_XEN);
  91. return 0;
  92. }
  93. static int pasemi_i2c_xfer_msg(struct i2c_adapter *adapter,
  94. struct i2c_msg *msg, int stop)
  95. {
  96. struct pasemi_smbus *smbus = adapter->algo_data;
  97. int read, i, err;
  98. u32 rd;
  99. read = msg->flags & I2C_M_RD ? 1 : 0;
  100. TXFIFO_WR(smbus, MTXFIFO_START | (msg->addr << 1) | read);
  101. if (read) {
  102. TXFIFO_WR(smbus, msg->len | MTXFIFO_READ |
  103. (stop ? MTXFIFO_STOP : 0));
  104. err = pasemi_smb_waitready(smbus);
  105. if (err)
  106. goto reset_out;
  107. for (i = 0; i < msg->len; i++) {
  108. rd = RXFIFO_RD(smbus);
  109. if (rd & MRXFIFO_EMPTY) {
  110. err = -ENODATA;
  111. goto reset_out;
  112. }
  113. msg->buf[i] = rd & MRXFIFO_DATA_M;
  114. }
  115. } else {
  116. for (i = 0; i < msg->len - 1; i++)
  117. TXFIFO_WR(smbus, msg->buf[i]);
  118. TXFIFO_WR(smbus, msg->buf[msg->len-1] |
  119. (stop ? MTXFIFO_STOP : 0));
  120. }
  121. return 0;
  122. reset_out:
  123. reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR |
  124. (CLK_100K_DIV & CTL_CLK_M)));
  125. return err;
  126. }
  127. static int pasemi_i2c_xfer(struct i2c_adapter *adapter,
  128. struct i2c_msg *msgs, int num)
  129. {
  130. struct pasemi_smbus *smbus = adapter->algo_data;
  131. int ret, i;
  132. pasemi_smb_clear(smbus);
  133. ret = 0;
  134. for (i = 0; i < num && !ret; i++)
  135. ret = pasemi_i2c_xfer_msg(adapter, &msgs[i], (i == (num - 1)));
  136. return ret ? ret : num;
  137. }
  138. static int pasemi_smb_xfer(struct i2c_adapter *adapter,
  139. u16 addr, unsigned short flags, char read_write, u8 command,
  140. int size, union i2c_smbus_data *data)
  141. {
  142. struct pasemi_smbus *smbus = adapter->algo_data;
  143. unsigned int rd;
  144. int read_flag, err;
  145. int len = 0, i;
  146. /* All our ops take 8-bit shifted addresses */
  147. addr <<= 1;
  148. read_flag = read_write == I2C_SMBUS_READ;
  149. pasemi_smb_clear(smbus);
  150. switch (size) {
  151. case I2C_SMBUS_QUICK:
  152. TXFIFO_WR(smbus, addr | read_flag | MTXFIFO_START |
  153. MTXFIFO_STOP);
  154. break;
  155. case I2C_SMBUS_BYTE:
  156. TXFIFO_WR(smbus, addr | read_flag | MTXFIFO_START);
  157. if (read_write)
  158. TXFIFO_WR(smbus, 1 | MTXFIFO_STOP | MTXFIFO_READ);
  159. else
  160. TXFIFO_WR(smbus, MTXFIFO_STOP | command);
  161. break;
  162. case I2C_SMBUS_BYTE_DATA:
  163. TXFIFO_WR(smbus, addr | MTXFIFO_START);
  164. TXFIFO_WR(smbus, command);
  165. if (read_write) {
  166. TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
  167. TXFIFO_WR(smbus, 1 | MTXFIFO_READ | MTXFIFO_STOP);
  168. } else {
  169. TXFIFO_WR(smbus, MTXFIFO_STOP | data->byte);
  170. }
  171. break;
  172. case I2C_SMBUS_WORD_DATA:
  173. TXFIFO_WR(smbus, addr | MTXFIFO_START);
  174. TXFIFO_WR(smbus, command);
  175. if (read_write) {
  176. TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
  177. TXFIFO_WR(smbus, 2 | MTXFIFO_READ | MTXFIFO_STOP);
  178. } else {
  179. TXFIFO_WR(smbus, data->word & MTXFIFO_DATA_M);
  180. TXFIFO_WR(smbus, MTXFIFO_STOP | (data->word >> 8));
  181. }
  182. break;
  183. case I2C_SMBUS_BLOCK_DATA:
  184. TXFIFO_WR(smbus, addr | MTXFIFO_START);
  185. TXFIFO_WR(smbus, command);
  186. if (read_write) {
  187. TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
  188. TXFIFO_WR(smbus, 1 | MTXFIFO_READ);
  189. rd = RXFIFO_RD(smbus);
  190. len = min_t(u8, (rd & MRXFIFO_DATA_M),
  191. I2C_SMBUS_BLOCK_MAX);
  192. TXFIFO_WR(smbus, len | MTXFIFO_READ |
  193. MTXFIFO_STOP);
  194. } else {
  195. len = min_t(u8, data->block[0], I2C_SMBUS_BLOCK_MAX);
  196. TXFIFO_WR(smbus, len);
  197. for (i = 1; i < len; i++)
  198. TXFIFO_WR(smbus, data->block[i]);
  199. TXFIFO_WR(smbus, data->block[len] | MTXFIFO_STOP);
  200. }
  201. break;
  202. case I2C_SMBUS_PROC_CALL:
  203. read_write = I2C_SMBUS_READ;
  204. TXFIFO_WR(smbus, addr | MTXFIFO_START);
  205. TXFIFO_WR(smbus, command);
  206. TXFIFO_WR(smbus, data->word & MTXFIFO_DATA_M);
  207. TXFIFO_WR(smbus, (data->word >> 8) & MTXFIFO_DATA_M);
  208. TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
  209. TXFIFO_WR(smbus, 2 | MTXFIFO_STOP | MTXFIFO_READ);
  210. break;
  211. case I2C_SMBUS_BLOCK_PROC_CALL:
  212. len = min_t(u8, data->block[0], I2C_SMBUS_BLOCK_MAX - 1);
  213. read_write = I2C_SMBUS_READ;
  214. TXFIFO_WR(smbus, addr | MTXFIFO_START);
  215. TXFIFO_WR(smbus, command);
  216. TXFIFO_WR(smbus, len);
  217. for (i = 1; i <= len; i++)
  218. TXFIFO_WR(smbus, data->block[i]);
  219. TXFIFO_WR(smbus, addr | I2C_SMBUS_READ);
  220. TXFIFO_WR(smbus, MTXFIFO_READ | 1);
  221. rd = RXFIFO_RD(smbus);
  222. len = min_t(u8, (rd & MRXFIFO_DATA_M),
  223. I2C_SMBUS_BLOCK_MAX - len);
  224. TXFIFO_WR(smbus, len | MTXFIFO_READ | MTXFIFO_STOP);
  225. break;
  226. default:
  227. dev_warn(&adapter->dev, "Unsupported transaction %d\n", size);
  228. return -EINVAL;
  229. }
  230. err = pasemi_smb_waitready(smbus);
  231. if (err)
  232. goto reset_out;
  233. if (read_write == I2C_SMBUS_WRITE)
  234. return 0;
  235. switch (size) {
  236. case I2C_SMBUS_BYTE:
  237. case I2C_SMBUS_BYTE_DATA:
  238. rd = RXFIFO_RD(smbus);
  239. if (rd & MRXFIFO_EMPTY) {
  240. err = -ENODATA;
  241. goto reset_out;
  242. }
  243. data->byte = rd & MRXFIFO_DATA_M;
  244. break;
  245. case I2C_SMBUS_WORD_DATA:
  246. case I2C_SMBUS_PROC_CALL:
  247. rd = RXFIFO_RD(smbus);
  248. if (rd & MRXFIFO_EMPTY) {
  249. err = -ENODATA;
  250. goto reset_out;
  251. }
  252. data->word = rd & MRXFIFO_DATA_M;
  253. rd = RXFIFO_RD(smbus);
  254. if (rd & MRXFIFO_EMPTY) {
  255. err = -ENODATA;
  256. goto reset_out;
  257. }
  258. data->word |= (rd & MRXFIFO_DATA_M) << 8;
  259. break;
  260. case I2C_SMBUS_BLOCK_DATA:
  261. case I2C_SMBUS_BLOCK_PROC_CALL:
  262. data->block[0] = len;
  263. for (i = 1; i <= len; i ++) {
  264. rd = RXFIFO_RD(smbus);
  265. if (rd & MRXFIFO_EMPTY) {
  266. err = -ENODATA;
  267. goto reset_out;
  268. }
  269. data->block[i] = rd & MRXFIFO_DATA_M;
  270. }
  271. break;
  272. }
  273. return 0;
  274. reset_out:
  275. reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR |
  276. (CLK_100K_DIV & CTL_CLK_M)));
  277. return err;
  278. }
  279. static u32 pasemi_smb_func(struct i2c_adapter *adapter)
  280. {
  281. return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
  282. I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
  283. I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
  284. I2C_FUNC_SMBUS_BLOCK_PROC_CALL | I2C_FUNC_I2C;
  285. }
  286. static const struct i2c_algorithm smbus_algorithm = {
  287. .master_xfer = pasemi_i2c_xfer,
  288. .smbus_xfer = pasemi_smb_xfer,
  289. .functionality = pasemi_smb_func,
  290. };
  291. static int pasemi_smb_probe(struct pci_dev *dev,
  292. const struct pci_device_id *id)
  293. {
  294. struct pasemi_smbus *smbus;
  295. int error;
  296. if (!(pci_resource_flags(dev, 0) & IORESOURCE_IO))
  297. return -ENODEV;
  298. smbus = kzalloc(sizeof(struct pasemi_smbus), GFP_KERNEL);
  299. if (!smbus)
  300. return -ENOMEM;
  301. smbus->dev = dev;
  302. smbus->base = pci_resource_start(dev, 0);
  303. smbus->size = pci_resource_len(dev, 0);
  304. if (!request_region(smbus->base, smbus->size,
  305. pasemi_smb_driver.name)) {
  306. error = -EBUSY;
  307. goto out_kfree;
  308. }
  309. smbus->adapter.owner = THIS_MODULE;
  310. snprintf(smbus->adapter.name, sizeof(smbus->adapter.name),
  311. "PA Semi SMBus adapter at 0x%lx", smbus->base);
  312. smbus->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
  313. smbus->adapter.algo = &smbus_algorithm;
  314. smbus->adapter.algo_data = smbus;
  315. smbus->adapter.nr = PCI_FUNC(dev->devfn);
  316. /* set up the sysfs linkage to our parent device */
  317. smbus->adapter.dev.parent = &dev->dev;
  318. reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR |
  319. (CLK_100K_DIV & CTL_CLK_M)));
  320. error = i2c_add_numbered_adapter(&smbus->adapter);
  321. if (error)
  322. goto out_release_region;
  323. pci_set_drvdata(dev, smbus);
  324. return 0;
  325. out_release_region:
  326. release_region(smbus->base, smbus->size);
  327. out_kfree:
  328. kfree(smbus);
  329. return error;
  330. }
  331. static void pasemi_smb_remove(struct pci_dev *dev)
  332. {
  333. struct pasemi_smbus *smbus = pci_get_drvdata(dev);
  334. i2c_del_adapter(&smbus->adapter);
  335. release_region(smbus->base, smbus->size);
  336. kfree(smbus);
  337. }
  338. static const struct pci_device_id pasemi_smb_ids[] = {
  339. { PCI_DEVICE(0x1959, 0xa003) },
  340. { 0, }
  341. };
  342. MODULE_DEVICE_TABLE(pci, pasemi_smb_ids);
  343. static struct pci_driver pasemi_smb_driver = {
  344. .name = "i2c-pasemi",
  345. .id_table = pasemi_smb_ids,
  346. .probe = pasemi_smb_probe,
  347. .remove = pasemi_smb_remove,
  348. };
  349. module_pci_driver(pasemi_smb_driver);
  350. MODULE_LICENSE("GPL");
  351. MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
  352. MODULE_DESCRIPTION("PA Semi PWRficient SMBus driver");