i2c-sis96x.c 8.3 KB

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  1. /*
  2. Copyright (c) 2003 Mark M. Hoffman <mhoffman@lightlink.com>
  3. This program is free software; you can redistribute it and/or modify
  4. it under the terms of the GNU General Public License as published by
  5. the Free Software Foundation; either version 2 of the License, or
  6. (at your option) any later version.
  7. This program is distributed in the hope that it will be useful,
  8. but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. GNU General Public License for more details.
  11. */
  12. /*
  13. This module must be considered BETA unless and until
  14. the chipset manufacturer releases a datasheet.
  15. The register definitions are based on the SiS630.
  16. This module relies on quirk_sis_96x_smbus (drivers/pci/quirks.c)
  17. for just about every machine for which users have reported.
  18. If this module isn't detecting your 96x south bridge, have a
  19. look there.
  20. We assume there can only be one SiS96x with one SMBus interface.
  21. */
  22. #include <linux/module.h>
  23. #include <linux/pci.h>
  24. #include <linux/kernel.h>
  25. #include <linux/delay.h>
  26. #include <linux/stddef.h>
  27. #include <linux/ioport.h>
  28. #include <linux/i2c.h>
  29. #include <linux/acpi.h>
  30. #include <linux/io.h>
  31. /* base address register in PCI config space */
  32. #define SIS96x_BAR 0x04
  33. /* SiS96x SMBus registers */
  34. #define SMB_STS 0x00
  35. #define SMB_EN 0x01
  36. #define SMB_CNT 0x02
  37. #define SMB_HOST_CNT 0x03
  38. #define SMB_ADDR 0x04
  39. #define SMB_CMD 0x05
  40. #define SMB_PCOUNT 0x06
  41. #define SMB_COUNT 0x07
  42. #define SMB_BYTE 0x08
  43. #define SMB_DEV_ADDR 0x10
  44. #define SMB_DB0 0x11
  45. #define SMB_DB1 0x12
  46. #define SMB_SAA 0x13
  47. /* register count for request_region */
  48. #define SMB_IOSIZE 0x20
  49. /* Other settings */
  50. #define MAX_TIMEOUT 500
  51. /* SiS96x SMBus constants */
  52. #define SIS96x_QUICK 0x00
  53. #define SIS96x_BYTE 0x01
  54. #define SIS96x_BYTE_DATA 0x02
  55. #define SIS96x_WORD_DATA 0x03
  56. #define SIS96x_PROC_CALL 0x04
  57. #define SIS96x_BLOCK_DATA 0x05
  58. static struct pci_driver sis96x_driver;
  59. static struct i2c_adapter sis96x_adapter;
  60. static u16 sis96x_smbus_base;
  61. static inline u8 sis96x_read(u8 reg)
  62. {
  63. return inb(sis96x_smbus_base + reg) ;
  64. }
  65. static inline void sis96x_write(u8 reg, u8 data)
  66. {
  67. outb(data, sis96x_smbus_base + reg) ;
  68. }
  69. /* Execute a SMBus transaction.
  70. int size is from SIS96x_QUICK to SIS96x_BLOCK_DATA
  71. */
  72. static int sis96x_transaction(int size)
  73. {
  74. int temp;
  75. int result = 0;
  76. int timeout = 0;
  77. dev_dbg(&sis96x_adapter.dev, "SMBus transaction %d\n", size);
  78. /* Make sure the SMBus host is ready to start transmitting */
  79. if (((temp = sis96x_read(SMB_CNT)) & 0x03) != 0x00) {
  80. dev_dbg(&sis96x_adapter.dev, "SMBus busy (0x%02x). "
  81. "Resetting...\n", temp);
  82. /* kill the transaction */
  83. sis96x_write(SMB_HOST_CNT, 0x20);
  84. /* check it again */
  85. if (((temp = sis96x_read(SMB_CNT)) & 0x03) != 0x00) {
  86. dev_dbg(&sis96x_adapter.dev, "Failed (0x%02x)\n", temp);
  87. return -EBUSY;
  88. } else {
  89. dev_dbg(&sis96x_adapter.dev, "Successful\n");
  90. }
  91. }
  92. /* Turn off timeout interrupts, set fast host clock */
  93. sis96x_write(SMB_CNT, 0x20);
  94. /* clear all (sticky) status flags */
  95. temp = sis96x_read(SMB_STS);
  96. sis96x_write(SMB_STS, temp & 0x1e);
  97. /* start the transaction by setting bit 4 and size bits */
  98. sis96x_write(SMB_HOST_CNT, 0x10 | (size & 0x07));
  99. /* We will always wait for a fraction of a second! */
  100. do {
  101. msleep(1);
  102. temp = sis96x_read(SMB_STS);
  103. } while (!(temp & 0x0e) && (timeout++ < MAX_TIMEOUT));
  104. /* If the SMBus is still busy, we give up */
  105. if (timeout > MAX_TIMEOUT) {
  106. dev_dbg(&sis96x_adapter.dev, "SMBus Timeout! (0x%02x)\n", temp);
  107. result = -ETIMEDOUT;
  108. }
  109. /* device error - probably missing ACK */
  110. if (temp & 0x02) {
  111. dev_dbg(&sis96x_adapter.dev, "Failed bus transaction!\n");
  112. result = -ENXIO;
  113. }
  114. /* bus collision */
  115. if (temp & 0x04) {
  116. dev_dbg(&sis96x_adapter.dev, "Bus collision!\n");
  117. result = -EIO;
  118. }
  119. /* Finish up by resetting the bus */
  120. sis96x_write(SMB_STS, temp);
  121. if ((temp = sis96x_read(SMB_STS))) {
  122. dev_dbg(&sis96x_adapter.dev, "Failed reset at "
  123. "end of transaction! (0x%02x)\n", temp);
  124. }
  125. return result;
  126. }
  127. /* Return negative errno on error. */
  128. static s32 sis96x_access(struct i2c_adapter * adap, u16 addr,
  129. unsigned short flags, char read_write,
  130. u8 command, int size, union i2c_smbus_data * data)
  131. {
  132. int status;
  133. switch (size) {
  134. case I2C_SMBUS_QUICK:
  135. sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
  136. size = SIS96x_QUICK;
  137. break;
  138. case I2C_SMBUS_BYTE:
  139. sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
  140. if (read_write == I2C_SMBUS_WRITE)
  141. sis96x_write(SMB_CMD, command);
  142. size = SIS96x_BYTE;
  143. break;
  144. case I2C_SMBUS_BYTE_DATA:
  145. sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
  146. sis96x_write(SMB_CMD, command);
  147. if (read_write == I2C_SMBUS_WRITE)
  148. sis96x_write(SMB_BYTE, data->byte);
  149. size = SIS96x_BYTE_DATA;
  150. break;
  151. case I2C_SMBUS_PROC_CALL:
  152. case I2C_SMBUS_WORD_DATA:
  153. sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
  154. sis96x_write(SMB_CMD, command);
  155. if (read_write == I2C_SMBUS_WRITE) {
  156. sis96x_write(SMB_BYTE, data->word & 0xff);
  157. sis96x_write(SMB_BYTE + 1, (data->word & 0xff00) >> 8);
  158. }
  159. size = (size == I2C_SMBUS_PROC_CALL ?
  160. SIS96x_PROC_CALL : SIS96x_WORD_DATA);
  161. break;
  162. default:
  163. dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
  164. return -EOPNOTSUPP;
  165. }
  166. status = sis96x_transaction(size);
  167. if (status)
  168. return status;
  169. if ((size != SIS96x_PROC_CALL) &&
  170. ((read_write == I2C_SMBUS_WRITE) || (size == SIS96x_QUICK)))
  171. return 0;
  172. switch (size) {
  173. case SIS96x_BYTE:
  174. case SIS96x_BYTE_DATA:
  175. data->byte = sis96x_read(SMB_BYTE);
  176. break;
  177. case SIS96x_WORD_DATA:
  178. case SIS96x_PROC_CALL:
  179. data->word = sis96x_read(SMB_BYTE) +
  180. (sis96x_read(SMB_BYTE + 1) << 8);
  181. break;
  182. }
  183. return 0;
  184. }
  185. static u32 sis96x_func(struct i2c_adapter *adapter)
  186. {
  187. return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
  188. I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
  189. I2C_FUNC_SMBUS_PROC_CALL;
  190. }
  191. static const struct i2c_algorithm smbus_algorithm = {
  192. .smbus_xfer = sis96x_access,
  193. .functionality = sis96x_func,
  194. };
  195. static struct i2c_adapter sis96x_adapter = {
  196. .owner = THIS_MODULE,
  197. .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
  198. .algo = &smbus_algorithm,
  199. };
  200. static const struct pci_device_id sis96x_ids[] = {
  201. { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_SMBUS) },
  202. { 0, }
  203. };
  204. MODULE_DEVICE_TABLE (pci, sis96x_ids);
  205. static int sis96x_probe(struct pci_dev *dev,
  206. const struct pci_device_id *id)
  207. {
  208. u16 ww = 0;
  209. int retval;
  210. if (sis96x_smbus_base) {
  211. dev_err(&dev->dev, "Only one device supported.\n");
  212. return -EBUSY;
  213. }
  214. pci_read_config_word(dev, PCI_CLASS_DEVICE, &ww);
  215. if (PCI_CLASS_SERIAL_SMBUS != ww) {
  216. dev_err(&dev->dev, "Unsupported device class 0x%04x!\n", ww);
  217. return -ENODEV;
  218. }
  219. sis96x_smbus_base = pci_resource_start(dev, SIS96x_BAR);
  220. if (!sis96x_smbus_base) {
  221. dev_err(&dev->dev, "SiS96x SMBus base address "
  222. "not initialized!\n");
  223. return -EINVAL;
  224. }
  225. dev_info(&dev->dev, "SiS96x SMBus base address: 0x%04x\n",
  226. sis96x_smbus_base);
  227. retval = acpi_check_resource_conflict(&dev->resource[SIS96x_BAR]);
  228. if (retval)
  229. return -ENODEV;
  230. /* Everything is happy, let's grab the memory and set things up. */
  231. if (!request_region(sis96x_smbus_base, SMB_IOSIZE,
  232. sis96x_driver.name)) {
  233. dev_err(&dev->dev, "SMBus registers 0x%04x-0x%04x "
  234. "already in use!\n", sis96x_smbus_base,
  235. sis96x_smbus_base + SMB_IOSIZE - 1);
  236. sis96x_smbus_base = 0;
  237. return -EINVAL;
  238. }
  239. /* set up the sysfs linkage to our parent device */
  240. sis96x_adapter.dev.parent = &dev->dev;
  241. snprintf(sis96x_adapter.name, sizeof(sis96x_adapter.name),
  242. "SiS96x SMBus adapter at 0x%04x", sis96x_smbus_base);
  243. if ((retval = i2c_add_adapter(&sis96x_adapter))) {
  244. dev_err(&dev->dev, "Couldn't register adapter!\n");
  245. release_region(sis96x_smbus_base, SMB_IOSIZE);
  246. sis96x_smbus_base = 0;
  247. }
  248. return retval;
  249. }
  250. static void sis96x_remove(struct pci_dev *dev)
  251. {
  252. if (sis96x_smbus_base) {
  253. i2c_del_adapter(&sis96x_adapter);
  254. release_region(sis96x_smbus_base, SMB_IOSIZE);
  255. sis96x_smbus_base = 0;
  256. }
  257. }
  258. static struct pci_driver sis96x_driver = {
  259. .name = "sis96x_smbus",
  260. .id_table = sis96x_ids,
  261. .probe = sis96x_probe,
  262. .remove = sis96x_remove,
  263. };
  264. module_pci_driver(sis96x_driver);
  265. MODULE_AUTHOR("Mark M. Hoffman <mhoffman@lightlink.com>");
  266. MODULE_DESCRIPTION("SiS96x SMBus driver");
  267. MODULE_LICENSE("GPL");