lpc32xx_ts.c 10 KB

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  1. /*
  2. * LPC32xx built-in touchscreen driver
  3. *
  4. * Copyright (C) 2010 NXP Semiconductors
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <linux/platform_device.h>
  17. #include <linux/input.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/module.h>
  20. #include <linux/clk.h>
  21. #include <linux/io.h>
  22. #include <linux/slab.h>
  23. #include <linux/of.h>
  24. /*
  25. * Touchscreen controller register offsets
  26. */
  27. #define LPC32XX_TSC_STAT 0x00
  28. #define LPC32XX_TSC_SEL 0x04
  29. #define LPC32XX_TSC_CON 0x08
  30. #define LPC32XX_TSC_FIFO 0x0C
  31. #define LPC32XX_TSC_DTR 0x10
  32. #define LPC32XX_TSC_RTR 0x14
  33. #define LPC32XX_TSC_UTR 0x18
  34. #define LPC32XX_TSC_TTR 0x1C
  35. #define LPC32XX_TSC_DXP 0x20
  36. #define LPC32XX_TSC_MIN_X 0x24
  37. #define LPC32XX_TSC_MAX_X 0x28
  38. #define LPC32XX_TSC_MIN_Y 0x2C
  39. #define LPC32XX_TSC_MAX_Y 0x30
  40. #define LPC32XX_TSC_AUX_UTR 0x34
  41. #define LPC32XX_TSC_AUX_MIN 0x38
  42. #define LPC32XX_TSC_AUX_MAX 0x3C
  43. #define LPC32XX_TSC_STAT_FIFO_OVRRN (1 << 8)
  44. #define LPC32XX_TSC_STAT_FIFO_EMPTY (1 << 7)
  45. #define LPC32XX_TSC_SEL_DEFVAL 0x0284
  46. #define LPC32XX_TSC_ADCCON_IRQ_TO_FIFO_4 (0x1 << 11)
  47. #define LPC32XX_TSC_ADCCON_X_SAMPLE_SIZE(s) ((10 - (s)) << 7)
  48. #define LPC32XX_TSC_ADCCON_Y_SAMPLE_SIZE(s) ((10 - (s)) << 4)
  49. #define LPC32XX_TSC_ADCCON_POWER_UP (1 << 2)
  50. #define LPC32XX_TSC_ADCCON_AUTO_EN (1 << 0)
  51. #define LPC32XX_TSC_FIFO_TS_P_LEVEL (1 << 31)
  52. #define LPC32XX_TSC_FIFO_NORMALIZE_X_VAL(x) (((x) & 0x03FF0000) >> 16)
  53. #define LPC32XX_TSC_FIFO_NORMALIZE_Y_VAL(y) ((y) & 0x000003FF)
  54. #define LPC32XX_TSC_ADCDAT_VALUE_MASK 0x000003FF
  55. #define LPC32XX_TSC_MIN_XY_VAL 0x0
  56. #define LPC32XX_TSC_MAX_XY_VAL 0x3FF
  57. #define MOD_NAME "ts-lpc32xx"
  58. #define tsc_readl(dev, reg) \
  59. __raw_readl((dev)->tsc_base + (reg))
  60. #define tsc_writel(dev, reg, val) \
  61. __raw_writel((val), (dev)->tsc_base + (reg))
  62. struct lpc32xx_tsc {
  63. struct input_dev *dev;
  64. void __iomem *tsc_base;
  65. int irq;
  66. struct clk *clk;
  67. };
  68. static void lpc32xx_fifo_clear(struct lpc32xx_tsc *tsc)
  69. {
  70. while (!(tsc_readl(tsc, LPC32XX_TSC_STAT) &
  71. LPC32XX_TSC_STAT_FIFO_EMPTY))
  72. tsc_readl(tsc, LPC32XX_TSC_FIFO);
  73. }
  74. static irqreturn_t lpc32xx_ts_interrupt(int irq, void *dev_id)
  75. {
  76. u32 tmp, rv[4], xs[4], ys[4];
  77. int idx;
  78. struct lpc32xx_tsc *tsc = dev_id;
  79. struct input_dev *input = tsc->dev;
  80. tmp = tsc_readl(tsc, LPC32XX_TSC_STAT);
  81. if (tmp & LPC32XX_TSC_STAT_FIFO_OVRRN) {
  82. /* FIFO overflow - throw away samples */
  83. lpc32xx_fifo_clear(tsc);
  84. return IRQ_HANDLED;
  85. }
  86. /*
  87. * Gather and normalize 4 samples. Pen-up events may have less
  88. * than 4 samples, but its ok to pop 4 and let the last sample
  89. * pen status check drop the samples.
  90. */
  91. idx = 0;
  92. while (idx < 4 &&
  93. !(tsc_readl(tsc, LPC32XX_TSC_STAT) &
  94. LPC32XX_TSC_STAT_FIFO_EMPTY)) {
  95. tmp = tsc_readl(tsc, LPC32XX_TSC_FIFO);
  96. xs[idx] = LPC32XX_TSC_ADCDAT_VALUE_MASK -
  97. LPC32XX_TSC_FIFO_NORMALIZE_X_VAL(tmp);
  98. ys[idx] = LPC32XX_TSC_ADCDAT_VALUE_MASK -
  99. LPC32XX_TSC_FIFO_NORMALIZE_Y_VAL(tmp);
  100. rv[idx] = tmp;
  101. idx++;
  102. }
  103. /* Data is only valid if pen is still down in last sample */
  104. if (!(rv[3] & LPC32XX_TSC_FIFO_TS_P_LEVEL) && idx == 4) {
  105. /* Use average of 2nd and 3rd sample for position */
  106. input_report_abs(input, ABS_X, (xs[1] + xs[2]) / 2);
  107. input_report_abs(input, ABS_Y, (ys[1] + ys[2]) / 2);
  108. input_report_key(input, BTN_TOUCH, 1);
  109. } else {
  110. input_report_key(input, BTN_TOUCH, 0);
  111. }
  112. input_sync(input);
  113. return IRQ_HANDLED;
  114. }
  115. static void lpc32xx_stop_tsc(struct lpc32xx_tsc *tsc)
  116. {
  117. /* Disable auto mode */
  118. tsc_writel(tsc, LPC32XX_TSC_CON,
  119. tsc_readl(tsc, LPC32XX_TSC_CON) &
  120. ~LPC32XX_TSC_ADCCON_AUTO_EN);
  121. clk_disable_unprepare(tsc->clk);
  122. }
  123. static void lpc32xx_setup_tsc(struct lpc32xx_tsc *tsc)
  124. {
  125. u32 tmp;
  126. clk_prepare_enable(tsc->clk);
  127. tmp = tsc_readl(tsc, LPC32XX_TSC_CON) & ~LPC32XX_TSC_ADCCON_POWER_UP;
  128. /* Set the TSC FIFO depth to 4 samples @ 10-bits per sample (max) */
  129. tmp = LPC32XX_TSC_ADCCON_IRQ_TO_FIFO_4 |
  130. LPC32XX_TSC_ADCCON_X_SAMPLE_SIZE(10) |
  131. LPC32XX_TSC_ADCCON_Y_SAMPLE_SIZE(10);
  132. tsc_writel(tsc, LPC32XX_TSC_CON, tmp);
  133. /* These values are all preset */
  134. tsc_writel(tsc, LPC32XX_TSC_SEL, LPC32XX_TSC_SEL_DEFVAL);
  135. tsc_writel(tsc, LPC32XX_TSC_MIN_X, LPC32XX_TSC_MIN_XY_VAL);
  136. tsc_writel(tsc, LPC32XX_TSC_MAX_X, LPC32XX_TSC_MAX_XY_VAL);
  137. tsc_writel(tsc, LPC32XX_TSC_MIN_Y, LPC32XX_TSC_MIN_XY_VAL);
  138. tsc_writel(tsc, LPC32XX_TSC_MAX_Y, LPC32XX_TSC_MAX_XY_VAL);
  139. /* Aux support is not used */
  140. tsc_writel(tsc, LPC32XX_TSC_AUX_UTR, 0);
  141. tsc_writel(tsc, LPC32XX_TSC_AUX_MIN, 0);
  142. tsc_writel(tsc, LPC32XX_TSC_AUX_MAX, 0);
  143. /*
  144. * Set sample rate to about 240Hz per X/Y pair. A single measurement
  145. * consists of 4 pairs which gives about a 60Hz sample rate based on
  146. * a stable 32768Hz clock source. Values are in clocks.
  147. * Rate is (32768 / (RTR + XCONV + RTR + YCONV + DXP + TTR + UTR) / 4
  148. */
  149. tsc_writel(tsc, LPC32XX_TSC_RTR, 0x2);
  150. tsc_writel(tsc, LPC32XX_TSC_DTR, 0x2);
  151. tsc_writel(tsc, LPC32XX_TSC_TTR, 0x10);
  152. tsc_writel(tsc, LPC32XX_TSC_DXP, 0x4);
  153. tsc_writel(tsc, LPC32XX_TSC_UTR, 88);
  154. lpc32xx_fifo_clear(tsc);
  155. /* Enable automatic ts event capture */
  156. tsc_writel(tsc, LPC32XX_TSC_CON, tmp | LPC32XX_TSC_ADCCON_AUTO_EN);
  157. }
  158. static int lpc32xx_ts_open(struct input_dev *dev)
  159. {
  160. struct lpc32xx_tsc *tsc = input_get_drvdata(dev);
  161. lpc32xx_setup_tsc(tsc);
  162. return 0;
  163. }
  164. static void lpc32xx_ts_close(struct input_dev *dev)
  165. {
  166. struct lpc32xx_tsc *tsc = input_get_drvdata(dev);
  167. lpc32xx_stop_tsc(tsc);
  168. }
  169. static int lpc32xx_ts_probe(struct platform_device *pdev)
  170. {
  171. struct lpc32xx_tsc *tsc;
  172. struct input_dev *input;
  173. struct resource *res;
  174. resource_size_t size;
  175. int irq;
  176. int error;
  177. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  178. if (!res) {
  179. dev_err(&pdev->dev, "Can't get memory resource\n");
  180. return -ENOENT;
  181. }
  182. irq = platform_get_irq(pdev, 0);
  183. if (irq < 0) {
  184. dev_err(&pdev->dev, "Can't get interrupt resource\n");
  185. return irq;
  186. }
  187. tsc = kzalloc(sizeof(*tsc), GFP_KERNEL);
  188. input = input_allocate_device();
  189. if (!tsc || !input) {
  190. dev_err(&pdev->dev, "failed allocating memory\n");
  191. error = -ENOMEM;
  192. goto err_free_mem;
  193. }
  194. tsc->dev = input;
  195. tsc->irq = irq;
  196. size = resource_size(res);
  197. if (!request_mem_region(res->start, size, pdev->name)) {
  198. dev_err(&pdev->dev, "TSC registers are not free\n");
  199. error = -EBUSY;
  200. goto err_free_mem;
  201. }
  202. tsc->tsc_base = ioremap(res->start, size);
  203. if (!tsc->tsc_base) {
  204. dev_err(&pdev->dev, "Can't map memory\n");
  205. error = -ENOMEM;
  206. goto err_release_mem;
  207. }
  208. tsc->clk = clk_get(&pdev->dev, NULL);
  209. if (IS_ERR(tsc->clk)) {
  210. dev_err(&pdev->dev, "failed getting clock\n");
  211. error = PTR_ERR(tsc->clk);
  212. goto err_unmap;
  213. }
  214. input->name = MOD_NAME;
  215. input->phys = "lpc32xx/input0";
  216. input->id.bustype = BUS_HOST;
  217. input->id.vendor = 0x0001;
  218. input->id.product = 0x0002;
  219. input->id.version = 0x0100;
  220. input->dev.parent = &pdev->dev;
  221. input->open = lpc32xx_ts_open;
  222. input->close = lpc32xx_ts_close;
  223. input->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
  224. input->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
  225. input_set_abs_params(input, ABS_X, LPC32XX_TSC_MIN_XY_VAL,
  226. LPC32XX_TSC_MAX_XY_VAL, 0, 0);
  227. input_set_abs_params(input, ABS_Y, LPC32XX_TSC_MIN_XY_VAL,
  228. LPC32XX_TSC_MAX_XY_VAL, 0, 0);
  229. input_set_drvdata(input, tsc);
  230. error = request_irq(tsc->irq, lpc32xx_ts_interrupt,
  231. 0, pdev->name, tsc);
  232. if (error) {
  233. dev_err(&pdev->dev, "failed requesting interrupt\n");
  234. goto err_put_clock;
  235. }
  236. error = input_register_device(input);
  237. if (error) {
  238. dev_err(&pdev->dev, "failed registering input device\n");
  239. goto err_free_irq;
  240. }
  241. platform_set_drvdata(pdev, tsc);
  242. device_init_wakeup(&pdev->dev, 1);
  243. return 0;
  244. err_free_irq:
  245. free_irq(tsc->irq, tsc);
  246. err_put_clock:
  247. clk_put(tsc->clk);
  248. err_unmap:
  249. iounmap(tsc->tsc_base);
  250. err_release_mem:
  251. release_mem_region(res->start, size);
  252. err_free_mem:
  253. input_free_device(input);
  254. kfree(tsc);
  255. return error;
  256. }
  257. static int lpc32xx_ts_remove(struct platform_device *pdev)
  258. {
  259. struct lpc32xx_tsc *tsc = platform_get_drvdata(pdev);
  260. struct resource *res;
  261. device_init_wakeup(&pdev->dev, 0);
  262. free_irq(tsc->irq, tsc);
  263. input_unregister_device(tsc->dev);
  264. clk_put(tsc->clk);
  265. iounmap(tsc->tsc_base);
  266. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  267. release_mem_region(res->start, resource_size(res));
  268. kfree(tsc);
  269. return 0;
  270. }
  271. #ifdef CONFIG_PM
  272. static int lpc32xx_ts_suspend(struct device *dev)
  273. {
  274. struct lpc32xx_tsc *tsc = dev_get_drvdata(dev);
  275. struct input_dev *input = tsc->dev;
  276. /*
  277. * Suspend and resume can be called when the device hasn't been
  278. * enabled. If there are no users that have the device open, then
  279. * avoid calling the TSC stop and start functions as the TSC
  280. * isn't yet clocked.
  281. */
  282. mutex_lock(&input->mutex);
  283. if (input->users) {
  284. if (device_may_wakeup(dev))
  285. enable_irq_wake(tsc->irq);
  286. else
  287. lpc32xx_stop_tsc(tsc);
  288. }
  289. mutex_unlock(&input->mutex);
  290. return 0;
  291. }
  292. static int lpc32xx_ts_resume(struct device *dev)
  293. {
  294. struct lpc32xx_tsc *tsc = dev_get_drvdata(dev);
  295. struct input_dev *input = tsc->dev;
  296. mutex_lock(&input->mutex);
  297. if (input->users) {
  298. if (device_may_wakeup(dev))
  299. disable_irq_wake(tsc->irq);
  300. else
  301. lpc32xx_setup_tsc(tsc);
  302. }
  303. mutex_unlock(&input->mutex);
  304. return 0;
  305. }
  306. static const struct dev_pm_ops lpc32xx_ts_pm_ops = {
  307. .suspend = lpc32xx_ts_suspend,
  308. .resume = lpc32xx_ts_resume,
  309. };
  310. #define LPC32XX_TS_PM_OPS (&lpc32xx_ts_pm_ops)
  311. #else
  312. #define LPC32XX_TS_PM_OPS NULL
  313. #endif
  314. #ifdef CONFIG_OF
  315. static const struct of_device_id lpc32xx_tsc_of_match[] = {
  316. { .compatible = "nxp,lpc3220-tsc", },
  317. { },
  318. };
  319. MODULE_DEVICE_TABLE(of, lpc32xx_tsc_of_match);
  320. #endif
  321. static struct platform_driver lpc32xx_ts_driver = {
  322. .probe = lpc32xx_ts_probe,
  323. .remove = lpc32xx_ts_remove,
  324. .driver = {
  325. .name = MOD_NAME,
  326. .pm = LPC32XX_TS_PM_OPS,
  327. .of_match_table = of_match_ptr(lpc32xx_tsc_of_match),
  328. },
  329. };
  330. module_platform_driver(lpc32xx_ts_driver);
  331. MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com");
  332. MODULE_DESCRIPTION("LPC32XX TSC Driver");
  333. MODULE_LICENSE("GPL");
  334. MODULE_ALIAS("platform:lpc32xx_ts");