shmobile-ipmmu.c 3.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129
  1. /*
  2. * IPMMU/IPMMUI
  3. * Copyright (C) 2012 Hideki EIRAKU
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; version 2 of the License.
  8. */
  9. #include <linux/err.h>
  10. #include <linux/export.h>
  11. #include <linux/io.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/slab.h>
  14. #include <linux/platform_data/sh_ipmmu.h>
  15. #include "shmobile-ipmmu.h"
  16. #define IMCTR1 0x000
  17. #define IMCTR2 0x004
  18. #define IMASID 0x010
  19. #define IMTTBR 0x014
  20. #define IMTTBCR 0x018
  21. #define IMCTR1_TLBEN (1 << 0)
  22. #define IMCTR1_FLUSH (1 << 1)
  23. static void ipmmu_reg_write(struct shmobile_ipmmu *ipmmu, unsigned long reg_off,
  24. unsigned long data)
  25. {
  26. iowrite32(data, ipmmu->ipmmu_base + reg_off);
  27. }
  28. void ipmmu_tlb_flush(struct shmobile_ipmmu *ipmmu)
  29. {
  30. if (!ipmmu)
  31. return;
  32. spin_lock(&ipmmu->flush_lock);
  33. if (ipmmu->tlb_enabled)
  34. ipmmu_reg_write(ipmmu, IMCTR1, IMCTR1_FLUSH | IMCTR1_TLBEN);
  35. else
  36. ipmmu_reg_write(ipmmu, IMCTR1, IMCTR1_FLUSH);
  37. spin_unlock(&ipmmu->flush_lock);
  38. }
  39. void ipmmu_tlb_set(struct shmobile_ipmmu *ipmmu, unsigned long phys, int size,
  40. int asid)
  41. {
  42. if (!ipmmu)
  43. return;
  44. spin_lock(&ipmmu->flush_lock);
  45. switch (size) {
  46. default:
  47. ipmmu->tlb_enabled = 0;
  48. break;
  49. case 0x2000:
  50. ipmmu_reg_write(ipmmu, IMTTBCR, 1);
  51. ipmmu->tlb_enabled = 1;
  52. break;
  53. case 0x1000:
  54. ipmmu_reg_write(ipmmu, IMTTBCR, 2);
  55. ipmmu->tlb_enabled = 1;
  56. break;
  57. case 0x800:
  58. ipmmu_reg_write(ipmmu, IMTTBCR, 3);
  59. ipmmu->tlb_enabled = 1;
  60. break;
  61. case 0x400:
  62. ipmmu_reg_write(ipmmu, IMTTBCR, 4);
  63. ipmmu->tlb_enabled = 1;
  64. break;
  65. case 0x200:
  66. ipmmu_reg_write(ipmmu, IMTTBCR, 5);
  67. ipmmu->tlb_enabled = 1;
  68. break;
  69. case 0x100:
  70. ipmmu_reg_write(ipmmu, IMTTBCR, 6);
  71. ipmmu->tlb_enabled = 1;
  72. break;
  73. case 0x80:
  74. ipmmu_reg_write(ipmmu, IMTTBCR, 7);
  75. ipmmu->tlb_enabled = 1;
  76. break;
  77. }
  78. ipmmu_reg_write(ipmmu, IMTTBR, phys);
  79. ipmmu_reg_write(ipmmu, IMASID, asid);
  80. spin_unlock(&ipmmu->flush_lock);
  81. }
  82. static int ipmmu_probe(struct platform_device *pdev)
  83. {
  84. struct shmobile_ipmmu *ipmmu;
  85. struct resource *res;
  86. struct shmobile_ipmmu_platform_data *pdata = pdev->dev.platform_data;
  87. ipmmu = devm_kzalloc(&pdev->dev, sizeof(*ipmmu), GFP_KERNEL);
  88. if (!ipmmu) {
  89. dev_err(&pdev->dev, "cannot allocate device data\n");
  90. return -ENOMEM;
  91. }
  92. spin_lock_init(&ipmmu->flush_lock);
  93. ipmmu->dev = &pdev->dev;
  94. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  95. ipmmu->ipmmu_base = devm_ioremap_resource(&pdev->dev, res);
  96. if (IS_ERR(ipmmu->ipmmu_base))
  97. return PTR_ERR(ipmmu->ipmmu_base);
  98. ipmmu->dev_names = pdata->dev_names;
  99. ipmmu->num_dev_names = pdata->num_dev_names;
  100. platform_set_drvdata(pdev, ipmmu);
  101. ipmmu_reg_write(ipmmu, IMCTR1, 0x0); /* disable TLB */
  102. ipmmu_reg_write(ipmmu, IMCTR2, 0x0); /* disable PMB */
  103. return ipmmu_iommu_init(ipmmu);
  104. }
  105. static struct platform_driver ipmmu_driver = {
  106. .probe = ipmmu_probe,
  107. .driver = {
  108. .name = "ipmmu",
  109. },
  110. };
  111. static int __init ipmmu_init(void)
  112. {
  113. return platform_driver_register(&ipmmu_driver);
  114. }
  115. subsys_initcall(ipmmu_init);