irq-atmel-aic.c 7.2 KB

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  1. /*
  2. * Atmel AT91 AIC (Advanced Interrupt Controller) driver
  3. *
  4. * Copyright (C) 2004 SAN People
  5. * Copyright (C) 2004 ATMEL
  6. * Copyright (C) Rick Bronson
  7. * Copyright (C) 2014 Free Electrons
  8. *
  9. * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
  10. *
  11. * This file is licensed under the terms of the GNU General Public
  12. * License version 2. This program is licensed "as is" without any
  13. * warranty of any kind, whether express or implied.
  14. */
  15. #include <linux/init.h>
  16. #include <linux/module.h>
  17. #include <linux/mm.h>
  18. #include <linux/bitmap.h>
  19. #include <linux/types.h>
  20. #include <linux/irq.h>
  21. #include <linux/irqchip.h>
  22. #include <linux/of.h>
  23. #include <linux/of_address.h>
  24. #include <linux/of_irq.h>
  25. #include <linux/irqdomain.h>
  26. #include <linux/err.h>
  27. #include <linux/slab.h>
  28. #include <linux/io.h>
  29. #include <asm/exception.h>
  30. #include <asm/mach/irq.h>
  31. #include "irq-atmel-aic-common.h"
  32. /* Number of irq lines managed by AIC */
  33. #define NR_AIC_IRQS 32
  34. #define AT91_AIC_SMR(n) ((n) * 4)
  35. #define AT91_AIC_SVR(n) (0x80 + ((n) * 4))
  36. #define AT91_AIC_IVR 0x100
  37. #define AT91_AIC_FVR 0x104
  38. #define AT91_AIC_ISR 0x108
  39. #define AT91_AIC_IPR 0x10c
  40. #define AT91_AIC_IMR 0x110
  41. #define AT91_AIC_CISR 0x114
  42. #define AT91_AIC_IECR 0x120
  43. #define AT91_AIC_IDCR 0x124
  44. #define AT91_AIC_ICCR 0x128
  45. #define AT91_AIC_ISCR 0x12c
  46. #define AT91_AIC_EOICR 0x130
  47. #define AT91_AIC_SPU 0x134
  48. #define AT91_AIC_DCR 0x138
  49. static struct irq_domain *aic_domain;
  50. static asmlinkage void __exception_irq_entry
  51. aic_handle(struct pt_regs *regs)
  52. {
  53. struct irq_domain_chip_generic *dgc = aic_domain->gc;
  54. struct irq_chip_generic *gc = dgc->gc[0];
  55. u32 irqnr;
  56. u32 irqstat;
  57. irqnr = irq_reg_readl(gc, AT91_AIC_IVR);
  58. irqstat = irq_reg_readl(gc, AT91_AIC_ISR);
  59. if (!irqstat)
  60. irq_reg_writel(gc, 0, AT91_AIC_EOICR);
  61. else
  62. handle_domain_irq(aic_domain, irqnr, regs);
  63. }
  64. static int aic_retrigger(struct irq_data *d)
  65. {
  66. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  67. /* Enable interrupt on AIC5 */
  68. irq_gc_lock(gc);
  69. irq_reg_writel(gc, d->mask, AT91_AIC_ISCR);
  70. irq_gc_unlock(gc);
  71. return 0;
  72. }
  73. static int aic_set_type(struct irq_data *d, unsigned type)
  74. {
  75. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  76. unsigned int smr;
  77. int ret;
  78. smr = irq_reg_readl(gc, AT91_AIC_SMR(d->hwirq));
  79. ret = aic_common_set_type(d, type, &smr);
  80. if (ret)
  81. return ret;
  82. irq_reg_writel(gc, smr, AT91_AIC_SMR(d->hwirq));
  83. return 0;
  84. }
  85. #ifdef CONFIG_PM
  86. static void aic_suspend(struct irq_data *d)
  87. {
  88. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  89. irq_gc_lock(gc);
  90. irq_reg_writel(gc, gc->mask_cache, AT91_AIC_IDCR);
  91. irq_reg_writel(gc, gc->wake_active, AT91_AIC_IECR);
  92. irq_gc_unlock(gc);
  93. }
  94. static void aic_resume(struct irq_data *d)
  95. {
  96. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  97. irq_gc_lock(gc);
  98. irq_reg_writel(gc, gc->wake_active, AT91_AIC_IDCR);
  99. irq_reg_writel(gc, gc->mask_cache, AT91_AIC_IECR);
  100. irq_gc_unlock(gc);
  101. }
  102. static void aic_pm_shutdown(struct irq_data *d)
  103. {
  104. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  105. irq_gc_lock(gc);
  106. irq_reg_writel(gc, 0xffffffff, AT91_AIC_IDCR);
  107. irq_reg_writel(gc, 0xffffffff, AT91_AIC_ICCR);
  108. irq_gc_unlock(gc);
  109. }
  110. #else
  111. #define aic_suspend NULL
  112. #define aic_resume NULL
  113. #define aic_pm_shutdown NULL
  114. #endif /* CONFIG_PM */
  115. static void __init aic_hw_init(struct irq_domain *domain)
  116. {
  117. struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
  118. int i;
  119. /*
  120. * Perform 8 End Of Interrupt Command to make sure AIC
  121. * will not Lock out nIRQ
  122. */
  123. for (i = 0; i < 8; i++)
  124. irq_reg_writel(gc, 0, AT91_AIC_EOICR);
  125. /*
  126. * Spurious Interrupt ID in Spurious Vector Register.
  127. * When there is no current interrupt, the IRQ Vector Register
  128. * reads the value stored in AIC_SPU
  129. */
  130. irq_reg_writel(gc, 0xffffffff, AT91_AIC_SPU);
  131. /* No debugging in AIC: Debug (Protect) Control Register */
  132. irq_reg_writel(gc, 0, AT91_AIC_DCR);
  133. /* Disable and clear all interrupts initially */
  134. irq_reg_writel(gc, 0xffffffff, AT91_AIC_IDCR);
  135. irq_reg_writel(gc, 0xffffffff, AT91_AIC_ICCR);
  136. for (i = 0; i < 32; i++)
  137. irq_reg_writel(gc, i, AT91_AIC_SVR(i));
  138. }
  139. static int aic_irq_domain_xlate(struct irq_domain *d,
  140. struct device_node *ctrlr,
  141. const u32 *intspec, unsigned int intsize,
  142. irq_hw_number_t *out_hwirq,
  143. unsigned int *out_type)
  144. {
  145. struct irq_domain_chip_generic *dgc = d->gc;
  146. struct irq_chip_generic *gc;
  147. unsigned long flags;
  148. unsigned smr;
  149. int idx;
  150. int ret;
  151. if (!dgc)
  152. return -EINVAL;
  153. ret = aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize,
  154. out_hwirq, out_type);
  155. if (ret)
  156. return ret;
  157. idx = intspec[0] / dgc->irqs_per_chip;
  158. if (idx >= dgc->num_chips)
  159. return -EINVAL;
  160. gc = dgc->gc[idx];
  161. irq_gc_lock_irqsave(gc, flags);
  162. smr = irq_reg_readl(gc, AT91_AIC_SMR(*out_hwirq));
  163. ret = aic_common_set_priority(intspec[2], &smr);
  164. if (!ret)
  165. irq_reg_writel(gc, smr, AT91_AIC_SMR(*out_hwirq));
  166. irq_gc_unlock_irqrestore(gc, flags);
  167. return ret;
  168. }
  169. static const struct irq_domain_ops aic_irq_ops = {
  170. .map = irq_map_generic_chip,
  171. .xlate = aic_irq_domain_xlate,
  172. };
  173. static void __init at91rm9200_aic_irq_fixup(struct device_node *root)
  174. {
  175. aic_common_rtc_irq_fixup(root);
  176. }
  177. static void __init at91sam9260_aic_irq_fixup(struct device_node *root)
  178. {
  179. aic_common_rtt_irq_fixup(root);
  180. }
  181. static void __init at91sam9g45_aic_irq_fixup(struct device_node *root)
  182. {
  183. aic_common_rtc_irq_fixup(root);
  184. aic_common_rtt_irq_fixup(root);
  185. }
  186. static const struct of_device_id aic_irq_fixups[] __initconst = {
  187. { .compatible = "atmel,at91rm9200", .data = at91rm9200_aic_irq_fixup },
  188. { .compatible = "atmel,at91sam9g45", .data = at91sam9g45_aic_irq_fixup },
  189. { .compatible = "atmel,at91sam9n12", .data = at91rm9200_aic_irq_fixup },
  190. { .compatible = "atmel,at91sam9rl", .data = at91sam9g45_aic_irq_fixup },
  191. { .compatible = "atmel,at91sam9x5", .data = at91rm9200_aic_irq_fixup },
  192. { .compatible = "atmel,at91sam9260", .data = at91sam9260_aic_irq_fixup },
  193. { .compatible = "atmel,at91sam9261", .data = at91sam9260_aic_irq_fixup },
  194. { .compatible = "atmel,at91sam9263", .data = at91sam9260_aic_irq_fixup },
  195. { .compatible = "atmel,at91sam9g20", .data = at91sam9260_aic_irq_fixup },
  196. { /* sentinel */ },
  197. };
  198. static int __init aic_of_init(struct device_node *node,
  199. struct device_node *parent)
  200. {
  201. struct irq_chip_generic *gc;
  202. struct irq_domain *domain;
  203. if (aic_domain)
  204. return -EEXIST;
  205. domain = aic_common_of_init(node, &aic_irq_ops, "atmel-aic",
  206. NR_AIC_IRQS);
  207. if (IS_ERR(domain))
  208. return PTR_ERR(domain);
  209. aic_common_irq_fixup(aic_irq_fixups);
  210. aic_domain = domain;
  211. gc = irq_get_domain_generic_chip(domain, 0);
  212. gc->chip_types[0].regs.eoi = AT91_AIC_EOICR;
  213. gc->chip_types[0].regs.enable = AT91_AIC_IECR;
  214. gc->chip_types[0].regs.disable = AT91_AIC_IDCR;
  215. gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
  216. gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
  217. gc->chip_types[0].chip.irq_retrigger = aic_retrigger;
  218. gc->chip_types[0].chip.irq_set_type = aic_set_type;
  219. gc->chip_types[0].chip.irq_suspend = aic_suspend;
  220. gc->chip_types[0].chip.irq_resume = aic_resume;
  221. gc->chip_types[0].chip.irq_pm_shutdown = aic_pm_shutdown;
  222. aic_hw_init(domain);
  223. set_handle_irq(aic_handle);
  224. return 0;
  225. }
  226. IRQCHIP_DECLARE(at91rm9200_aic, "atmel,at91rm9200-aic", aic_of_init);