irq-orion.c 5.7 KB

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  1. /*
  2. * Marvell Orion SoCs IRQ chip driver.
  3. *
  4. * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  5. *
  6. * This file is licensed under the terms of the GNU General Public
  7. * License version 2. This program is licensed "as is" without any
  8. * warranty of any kind, whether express or implied.
  9. */
  10. #include <linux/io.h>
  11. #include <linux/irq.h>
  12. #include <linux/irqchip.h>
  13. #include <linux/of.h>
  14. #include <linux/of_address.h>
  15. #include <linux/of_irq.h>
  16. #include <asm/exception.h>
  17. #include <asm/mach/irq.h>
  18. /*
  19. * Orion SoC main interrupt controller
  20. */
  21. #define ORION_IRQS_PER_CHIP 32
  22. #define ORION_IRQ_CAUSE 0x00
  23. #define ORION_IRQ_MASK 0x04
  24. #define ORION_IRQ_FIQ_MASK 0x08
  25. #define ORION_IRQ_ENDP_MASK 0x0c
  26. static struct irq_domain *orion_irq_domain;
  27. static void
  28. __exception_irq_entry orion_handle_irq(struct pt_regs *regs)
  29. {
  30. struct irq_domain_chip_generic *dgc = orion_irq_domain->gc;
  31. int n, base = 0;
  32. for (n = 0; n < dgc->num_chips; n++, base += ORION_IRQS_PER_CHIP) {
  33. struct irq_chip_generic *gc =
  34. irq_get_domain_generic_chip(orion_irq_domain, base);
  35. u32 stat = readl_relaxed(gc->reg_base + ORION_IRQ_CAUSE) &
  36. gc->mask_cache;
  37. while (stat) {
  38. u32 hwirq = __fls(stat);
  39. handle_domain_irq(orion_irq_domain,
  40. gc->irq_base + hwirq, regs);
  41. stat &= ~(1 << hwirq);
  42. }
  43. }
  44. }
  45. static int __init orion_irq_init(struct device_node *np,
  46. struct device_node *parent)
  47. {
  48. unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
  49. int n, ret, base, num_chips = 0;
  50. struct resource r;
  51. /* count number of irq chips by valid reg addresses */
  52. while (of_address_to_resource(np, num_chips, &r) == 0)
  53. num_chips++;
  54. orion_irq_domain = irq_domain_add_linear(np,
  55. num_chips * ORION_IRQS_PER_CHIP,
  56. &irq_generic_chip_ops, NULL);
  57. if (!orion_irq_domain)
  58. panic("%s: unable to add irq domain\n", np->name);
  59. ret = irq_alloc_domain_generic_chips(orion_irq_domain,
  60. ORION_IRQS_PER_CHIP, 1, np->name,
  61. handle_level_irq, clr, 0,
  62. IRQ_GC_INIT_MASK_CACHE);
  63. if (ret)
  64. panic("%s: unable to alloc irq domain gc\n", np->name);
  65. for (n = 0, base = 0; n < num_chips; n++, base += ORION_IRQS_PER_CHIP) {
  66. struct irq_chip_generic *gc =
  67. irq_get_domain_generic_chip(orion_irq_domain, base);
  68. of_address_to_resource(np, n, &r);
  69. if (!request_mem_region(r.start, resource_size(&r), np->name))
  70. panic("%s: unable to request mem region %d",
  71. np->name, n);
  72. gc->reg_base = ioremap(r.start, resource_size(&r));
  73. if (!gc->reg_base)
  74. panic("%s: unable to map resource %d", np->name, n);
  75. gc->chip_types[0].regs.mask = ORION_IRQ_MASK;
  76. gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
  77. gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
  78. /* mask all interrupts */
  79. writel(0, gc->reg_base + ORION_IRQ_MASK);
  80. }
  81. set_handle_irq(orion_handle_irq);
  82. return 0;
  83. }
  84. IRQCHIP_DECLARE(orion_intc, "marvell,orion-intc", orion_irq_init);
  85. /*
  86. * Orion SoC bridge interrupt controller
  87. */
  88. #define ORION_BRIDGE_IRQ_CAUSE 0x00
  89. #define ORION_BRIDGE_IRQ_MASK 0x04
  90. static void orion_bridge_irq_handler(struct irq_desc *desc)
  91. {
  92. struct irq_domain *d = irq_desc_get_handler_data(desc);
  93. struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, 0);
  94. u32 stat = readl_relaxed(gc->reg_base + ORION_BRIDGE_IRQ_CAUSE) &
  95. gc->mask_cache;
  96. while (stat) {
  97. u32 hwirq = __fls(stat);
  98. generic_handle_irq(irq_find_mapping(d, gc->irq_base + hwirq));
  99. stat &= ~(1 << hwirq);
  100. }
  101. }
  102. /*
  103. * Bridge IRQ_CAUSE is asserted regardless of IRQ_MASK register.
  104. * To avoid interrupt events on stale irqs, we clear them before unmask.
  105. */
  106. static unsigned int orion_bridge_irq_startup(struct irq_data *d)
  107. {
  108. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  109. ct->chip.irq_ack(d);
  110. ct->chip.irq_unmask(d);
  111. return 0;
  112. }
  113. static int __init orion_bridge_irq_init(struct device_node *np,
  114. struct device_node *parent)
  115. {
  116. unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
  117. struct resource r;
  118. struct irq_domain *domain;
  119. struct irq_chip_generic *gc;
  120. int ret, irq, nrirqs = 32;
  121. /* get optional number of interrupts provided */
  122. of_property_read_u32(np, "marvell,#interrupts", &nrirqs);
  123. domain = irq_domain_add_linear(np, nrirqs,
  124. &irq_generic_chip_ops, NULL);
  125. if (!domain) {
  126. pr_err("%s: unable to add irq domain\n", np->name);
  127. return -ENOMEM;
  128. }
  129. ret = irq_alloc_domain_generic_chips(domain, nrirqs, 1, np->name,
  130. handle_edge_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE);
  131. if (ret) {
  132. pr_err("%s: unable to alloc irq domain gc\n", np->name);
  133. return ret;
  134. }
  135. ret = of_address_to_resource(np, 0, &r);
  136. if (ret) {
  137. pr_err("%s: unable to get resource\n", np->name);
  138. return ret;
  139. }
  140. if (!request_mem_region(r.start, resource_size(&r), np->name)) {
  141. pr_err("%s: unable to request mem region\n", np->name);
  142. return -ENOMEM;
  143. }
  144. /* Map the parent interrupt for the chained handler */
  145. irq = irq_of_parse_and_map(np, 0);
  146. if (irq <= 0) {
  147. pr_err("%s: unable to parse irq\n", np->name);
  148. return -EINVAL;
  149. }
  150. gc = irq_get_domain_generic_chip(domain, 0);
  151. gc->reg_base = ioremap(r.start, resource_size(&r));
  152. if (!gc->reg_base) {
  153. pr_err("%s: unable to map resource\n", np->name);
  154. return -ENOMEM;
  155. }
  156. gc->chip_types[0].regs.ack = ORION_BRIDGE_IRQ_CAUSE;
  157. gc->chip_types[0].regs.mask = ORION_BRIDGE_IRQ_MASK;
  158. gc->chip_types[0].chip.irq_startup = orion_bridge_irq_startup;
  159. gc->chip_types[0].chip.irq_ack = irq_gc_ack_clr_bit;
  160. gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
  161. gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
  162. /* mask and clear all interrupts */
  163. writel(0, gc->reg_base + ORION_BRIDGE_IRQ_MASK);
  164. writel(0, gc->reg_base + ORION_BRIDGE_IRQ_CAUSE);
  165. irq_set_chained_handler_and_data(irq, orion_bridge_irq_handler,
  166. domain);
  167. return 0;
  168. }
  169. IRQCHIP_DECLARE(orion_bridge_intc,
  170. "marvell,orion-bridge-intc", orion_bridge_irq_init);