irq-sirfsoc.c 3.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130
  1. /*
  2. * interrupt controller support for CSR SiRFprimaII
  3. *
  4. * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
  5. *
  6. * Licensed under GPLv2 or later.
  7. */
  8. #include <linux/init.h>
  9. #include <linux/io.h>
  10. #include <linux/irq.h>
  11. #include <linux/of.h>
  12. #include <linux/of_address.h>
  13. #include <linux/irqchip.h>
  14. #include <linux/irqdomain.h>
  15. #include <linux/syscore_ops.h>
  16. #include <asm/mach/irq.h>
  17. #include <asm/exception.h>
  18. #define SIRFSOC_INT_RISC_MASK0 0x0018
  19. #define SIRFSOC_INT_RISC_MASK1 0x001C
  20. #define SIRFSOC_INT_RISC_LEVEL0 0x0020
  21. #define SIRFSOC_INT_RISC_LEVEL1 0x0024
  22. #define SIRFSOC_INIT_IRQ_ID 0x0038
  23. #define SIRFSOC_INT_BASE_OFFSET 0x0004
  24. #define SIRFSOC_NUM_IRQS 64
  25. #define SIRFSOC_NUM_BANKS (SIRFSOC_NUM_IRQS / 32)
  26. static struct irq_domain *sirfsoc_irqdomain;
  27. static __init void sirfsoc_alloc_gc(void __iomem *base)
  28. {
  29. unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
  30. unsigned int set = IRQ_LEVEL;
  31. struct irq_chip_generic *gc;
  32. struct irq_chip_type *ct;
  33. int i;
  34. irq_alloc_domain_generic_chips(sirfsoc_irqdomain, 32, 1, "irq_sirfsoc",
  35. handle_level_irq, clr, set,
  36. IRQ_GC_INIT_MASK_CACHE);
  37. for (i = 0; i < SIRFSOC_NUM_BANKS; i++) {
  38. gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, i * 32);
  39. gc->reg_base = base + i * SIRFSOC_INT_BASE_OFFSET;
  40. ct = gc->chip_types;
  41. ct->chip.irq_mask = irq_gc_mask_clr_bit;
  42. ct->chip.irq_unmask = irq_gc_mask_set_bit;
  43. ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
  44. }
  45. }
  46. static void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
  47. {
  48. void __iomem *base = sirfsoc_irqdomain->host_data;
  49. u32 irqstat;
  50. irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
  51. handle_domain_irq(sirfsoc_irqdomain, irqstat & 0xff, regs);
  52. }
  53. static int __init sirfsoc_irq_init(struct device_node *np,
  54. struct device_node *parent)
  55. {
  56. void __iomem *base = of_iomap(np, 0);
  57. if (!base)
  58. panic("unable to map intc cpu registers\n");
  59. sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS,
  60. &irq_generic_chip_ops, base);
  61. sirfsoc_alloc_gc(base);
  62. writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0);
  63. writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1);
  64. writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0);
  65. writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1);
  66. set_handle_irq(sirfsoc_handle_irq);
  67. return 0;
  68. }
  69. IRQCHIP_DECLARE(sirfsoc_intc, "sirf,prima2-intc", sirfsoc_irq_init);
  70. struct sirfsoc_irq_status {
  71. u32 mask0;
  72. u32 mask1;
  73. u32 level0;
  74. u32 level1;
  75. };
  76. static struct sirfsoc_irq_status sirfsoc_irq_st;
  77. static int sirfsoc_irq_suspend(void)
  78. {
  79. void __iomem *base = sirfsoc_irqdomain->host_data;
  80. sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0);
  81. sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1);
  82. sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0);
  83. sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1);
  84. return 0;
  85. }
  86. static void sirfsoc_irq_resume(void)
  87. {
  88. void __iomem *base = sirfsoc_irqdomain->host_data;
  89. writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0);
  90. writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1);
  91. writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0);
  92. writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1);
  93. }
  94. static struct syscore_ops sirfsoc_irq_syscore_ops = {
  95. .suspend = sirfsoc_irq_suspend,
  96. .resume = sirfsoc_irq_resume,
  97. };
  98. static int __init sirfsoc_irq_pm_init(void)
  99. {
  100. if (!sirfsoc_irqdomain)
  101. return 0;
  102. register_syscore_ops(&sirfsoc_irq_syscore_ops);
  103. return 0;
  104. }
  105. device_initcall(sirfsoc_irq_pm_init);