omap-mailbox.c 22 KB

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  1. /*
  2. * OMAP mailbox driver
  3. *
  4. * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
  5. * Copyright (C) 2013-2014 Texas Instruments Inc.
  6. *
  7. * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
  8. * Suman Anna <s-anna@ti.com>
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License
  12. * version 2 as published by the Free Software Foundation.
  13. *
  14. * This program is distributed in the hope that it will be useful, but
  15. * WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  17. * General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  22. * 02110-1301 USA
  23. *
  24. */
  25. #include <linux/interrupt.h>
  26. #include <linux/spinlock.h>
  27. #include <linux/mutex.h>
  28. #include <linux/slab.h>
  29. #include <linux/kfifo.h>
  30. #include <linux/err.h>
  31. #include <linux/module.h>
  32. #include <linux/of_device.h>
  33. #include <linux/platform_device.h>
  34. #include <linux/pm_runtime.h>
  35. #include <linux/platform_data/mailbox-omap.h>
  36. #include <linux/omap-mailbox.h>
  37. #include <linux/mailbox_controller.h>
  38. #include <linux/mailbox_client.h>
  39. #include "mailbox.h"
  40. #define MAILBOX_REVISION 0x000
  41. #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
  42. #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
  43. #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
  44. #define OMAP2_MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
  45. #define OMAP2_MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
  46. #define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u))
  47. #define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u))
  48. #define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u))
  49. #define MAILBOX_IRQSTATUS(type, u) (type ? OMAP4_MAILBOX_IRQSTATUS(u) : \
  50. OMAP2_MAILBOX_IRQSTATUS(u))
  51. #define MAILBOX_IRQENABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE(u) : \
  52. OMAP2_MAILBOX_IRQENABLE(u))
  53. #define MAILBOX_IRQDISABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE_CLR(u) \
  54. : OMAP2_MAILBOX_IRQENABLE(u))
  55. #define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
  56. #define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
  57. #define MBOX_REG_SIZE 0x120
  58. #define OMAP4_MBOX_REG_SIZE 0x130
  59. #define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
  60. #define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
  61. struct omap_mbox_fifo {
  62. unsigned long msg;
  63. unsigned long fifo_stat;
  64. unsigned long msg_stat;
  65. unsigned long irqenable;
  66. unsigned long irqstatus;
  67. unsigned long irqdisable;
  68. u32 intr_bit;
  69. };
  70. struct omap_mbox_queue {
  71. spinlock_t lock;
  72. struct kfifo fifo;
  73. struct work_struct work;
  74. struct omap_mbox *mbox;
  75. bool full;
  76. };
  77. struct omap_mbox_device {
  78. struct device *dev;
  79. struct mutex cfg_lock;
  80. void __iomem *mbox_base;
  81. u32 num_users;
  82. u32 num_fifos;
  83. struct omap_mbox **mboxes;
  84. struct mbox_controller controller;
  85. struct list_head elem;
  86. };
  87. struct omap_mbox_fifo_info {
  88. int tx_id;
  89. int tx_usr;
  90. int tx_irq;
  91. int rx_id;
  92. int rx_usr;
  93. int rx_irq;
  94. const char *name;
  95. bool send_no_irq;
  96. };
  97. struct omap_mbox {
  98. const char *name;
  99. int irq;
  100. struct omap_mbox_queue *rxq;
  101. struct device *dev;
  102. struct omap_mbox_device *parent;
  103. struct omap_mbox_fifo tx_fifo;
  104. struct omap_mbox_fifo rx_fifo;
  105. u32 ctx[OMAP4_MBOX_NR_REGS];
  106. u32 intr_type;
  107. struct mbox_chan *chan;
  108. bool send_no_irq;
  109. };
  110. /* global variables for the mailbox devices */
  111. static DEFINE_MUTEX(omap_mbox_devices_lock);
  112. static LIST_HEAD(omap_mbox_devices);
  113. static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE;
  114. module_param(mbox_kfifo_size, uint, S_IRUGO);
  115. MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo (bytes)");
  116. static struct omap_mbox *mbox_chan_to_omap_mbox(struct mbox_chan *chan)
  117. {
  118. if (!chan || !chan->con_priv)
  119. return NULL;
  120. return (struct omap_mbox *)chan->con_priv;
  121. }
  122. static inline
  123. unsigned int mbox_read_reg(struct omap_mbox_device *mdev, size_t ofs)
  124. {
  125. return __raw_readl(mdev->mbox_base + ofs);
  126. }
  127. static inline
  128. void mbox_write_reg(struct omap_mbox_device *mdev, u32 val, size_t ofs)
  129. {
  130. __raw_writel(val, mdev->mbox_base + ofs);
  131. }
  132. /* Mailbox FIFO handle functions */
  133. static mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox)
  134. {
  135. struct omap_mbox_fifo *fifo = &mbox->rx_fifo;
  136. return (mbox_msg_t) mbox_read_reg(mbox->parent, fifo->msg);
  137. }
  138. static void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
  139. {
  140. struct omap_mbox_fifo *fifo = &mbox->tx_fifo;
  141. mbox_write_reg(mbox->parent, msg, fifo->msg);
  142. }
  143. static int mbox_fifo_empty(struct omap_mbox *mbox)
  144. {
  145. struct omap_mbox_fifo *fifo = &mbox->rx_fifo;
  146. return (mbox_read_reg(mbox->parent, fifo->msg_stat) == 0);
  147. }
  148. static int mbox_fifo_full(struct omap_mbox *mbox)
  149. {
  150. struct omap_mbox_fifo *fifo = &mbox->tx_fifo;
  151. return mbox_read_reg(mbox->parent, fifo->fifo_stat);
  152. }
  153. /* Mailbox IRQ handle functions */
  154. static void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
  155. {
  156. struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
  157. &mbox->tx_fifo : &mbox->rx_fifo;
  158. u32 bit = fifo->intr_bit;
  159. u32 irqstatus = fifo->irqstatus;
  160. mbox_write_reg(mbox->parent, bit, irqstatus);
  161. /* Flush posted write for irq status to avoid spurious interrupts */
  162. mbox_read_reg(mbox->parent, irqstatus);
  163. }
  164. static int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
  165. {
  166. struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
  167. &mbox->tx_fifo : &mbox->rx_fifo;
  168. u32 bit = fifo->intr_bit;
  169. u32 irqenable = fifo->irqenable;
  170. u32 irqstatus = fifo->irqstatus;
  171. u32 enable = mbox_read_reg(mbox->parent, irqenable);
  172. u32 status = mbox_read_reg(mbox->parent, irqstatus);
  173. return (int)(enable & status & bit);
  174. }
  175. void omap_mbox_save_ctx(struct mbox_chan *chan)
  176. {
  177. int i;
  178. int nr_regs;
  179. struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
  180. if (WARN_ON(!mbox))
  181. return;
  182. if (mbox->intr_type)
  183. nr_regs = OMAP4_MBOX_NR_REGS;
  184. else
  185. nr_regs = MBOX_NR_REGS;
  186. for (i = 0; i < nr_regs; i++) {
  187. mbox->ctx[i] = mbox_read_reg(mbox->parent, i * sizeof(u32));
  188. dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
  189. i, mbox->ctx[i]);
  190. }
  191. }
  192. EXPORT_SYMBOL(omap_mbox_save_ctx);
  193. void omap_mbox_restore_ctx(struct mbox_chan *chan)
  194. {
  195. int i;
  196. int nr_regs;
  197. struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
  198. if (WARN_ON(!mbox))
  199. return;
  200. if (mbox->intr_type)
  201. nr_regs = OMAP4_MBOX_NR_REGS;
  202. else
  203. nr_regs = MBOX_NR_REGS;
  204. for (i = 0; i < nr_regs; i++) {
  205. mbox_write_reg(mbox->parent, mbox->ctx[i], i * sizeof(u32));
  206. dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
  207. i, mbox->ctx[i]);
  208. }
  209. }
  210. EXPORT_SYMBOL(omap_mbox_restore_ctx);
  211. static void _omap_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
  212. {
  213. u32 l;
  214. struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
  215. &mbox->tx_fifo : &mbox->rx_fifo;
  216. u32 bit = fifo->intr_bit;
  217. u32 irqenable = fifo->irqenable;
  218. l = mbox_read_reg(mbox->parent, irqenable);
  219. l |= bit;
  220. mbox_write_reg(mbox->parent, l, irqenable);
  221. }
  222. static void _omap_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
  223. {
  224. struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
  225. &mbox->tx_fifo : &mbox->rx_fifo;
  226. u32 bit = fifo->intr_bit;
  227. u32 irqdisable = fifo->irqdisable;
  228. /*
  229. * Read and update the interrupt configuration register for pre-OMAP4.
  230. * OMAP4 and later SoCs have a dedicated interrupt disabling register.
  231. */
  232. if (!mbox->intr_type)
  233. bit = mbox_read_reg(mbox->parent, irqdisable) & ~bit;
  234. mbox_write_reg(mbox->parent, bit, irqdisable);
  235. }
  236. void omap_mbox_enable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq)
  237. {
  238. struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
  239. if (WARN_ON(!mbox))
  240. return;
  241. _omap_mbox_enable_irq(mbox, irq);
  242. }
  243. EXPORT_SYMBOL(omap_mbox_enable_irq);
  244. void omap_mbox_disable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq)
  245. {
  246. struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
  247. if (WARN_ON(!mbox))
  248. return;
  249. _omap_mbox_disable_irq(mbox, irq);
  250. }
  251. EXPORT_SYMBOL(omap_mbox_disable_irq);
  252. /*
  253. * Message receiver(workqueue)
  254. */
  255. static void mbox_rx_work(struct work_struct *work)
  256. {
  257. struct omap_mbox_queue *mq =
  258. container_of(work, struct omap_mbox_queue, work);
  259. mbox_msg_t msg;
  260. int len;
  261. while (kfifo_len(&mq->fifo) >= sizeof(msg)) {
  262. len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
  263. WARN_ON(len != sizeof(msg));
  264. mbox_chan_received_data(mq->mbox->chan, (void *)msg);
  265. spin_lock_irq(&mq->lock);
  266. if (mq->full) {
  267. mq->full = false;
  268. _omap_mbox_enable_irq(mq->mbox, IRQ_RX);
  269. }
  270. spin_unlock_irq(&mq->lock);
  271. }
  272. }
  273. /*
  274. * Mailbox interrupt handler
  275. */
  276. static void __mbox_tx_interrupt(struct omap_mbox *mbox)
  277. {
  278. _omap_mbox_disable_irq(mbox, IRQ_TX);
  279. ack_mbox_irq(mbox, IRQ_TX);
  280. mbox_chan_txdone(mbox->chan, 0);
  281. }
  282. static void __mbox_rx_interrupt(struct omap_mbox *mbox)
  283. {
  284. struct omap_mbox_queue *mq = mbox->rxq;
  285. mbox_msg_t msg;
  286. int len;
  287. while (!mbox_fifo_empty(mbox)) {
  288. if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) {
  289. _omap_mbox_disable_irq(mbox, IRQ_RX);
  290. mq->full = true;
  291. goto nomem;
  292. }
  293. msg = mbox_fifo_read(mbox);
  294. len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
  295. WARN_ON(len != sizeof(msg));
  296. }
  297. /* no more messages in the fifo. clear IRQ source. */
  298. ack_mbox_irq(mbox, IRQ_RX);
  299. nomem:
  300. schedule_work(&mbox->rxq->work);
  301. }
  302. static irqreturn_t mbox_interrupt(int irq, void *p)
  303. {
  304. struct omap_mbox *mbox = p;
  305. if (is_mbox_irq(mbox, IRQ_TX))
  306. __mbox_tx_interrupt(mbox);
  307. if (is_mbox_irq(mbox, IRQ_RX))
  308. __mbox_rx_interrupt(mbox);
  309. return IRQ_HANDLED;
  310. }
  311. static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
  312. void (*work)(struct work_struct *))
  313. {
  314. struct omap_mbox_queue *mq;
  315. if (!work)
  316. return NULL;
  317. mq = kzalloc(sizeof(struct omap_mbox_queue), GFP_KERNEL);
  318. if (!mq)
  319. return NULL;
  320. spin_lock_init(&mq->lock);
  321. if (kfifo_alloc(&mq->fifo, mbox_kfifo_size, GFP_KERNEL))
  322. goto error;
  323. INIT_WORK(&mq->work, work);
  324. return mq;
  325. error:
  326. kfree(mq);
  327. return NULL;
  328. }
  329. static void mbox_queue_free(struct omap_mbox_queue *q)
  330. {
  331. kfifo_free(&q->fifo);
  332. kfree(q);
  333. }
  334. static int omap_mbox_startup(struct omap_mbox *mbox)
  335. {
  336. int ret = 0;
  337. struct omap_mbox_queue *mq;
  338. mq = mbox_queue_alloc(mbox, mbox_rx_work);
  339. if (!mq)
  340. return -ENOMEM;
  341. mbox->rxq = mq;
  342. mq->mbox = mbox;
  343. ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
  344. mbox->name, mbox);
  345. if (unlikely(ret)) {
  346. pr_err("failed to register mailbox interrupt:%d\n", ret);
  347. goto fail_request_irq;
  348. }
  349. if (mbox->send_no_irq)
  350. mbox->chan->txdone_method = TXDONE_BY_ACK;
  351. _omap_mbox_enable_irq(mbox, IRQ_RX);
  352. return 0;
  353. fail_request_irq:
  354. mbox_queue_free(mbox->rxq);
  355. return ret;
  356. }
  357. static void omap_mbox_fini(struct omap_mbox *mbox)
  358. {
  359. _omap_mbox_disable_irq(mbox, IRQ_RX);
  360. free_irq(mbox->irq, mbox);
  361. flush_work(&mbox->rxq->work);
  362. mbox_queue_free(mbox->rxq);
  363. }
  364. static struct omap_mbox *omap_mbox_device_find(struct omap_mbox_device *mdev,
  365. const char *mbox_name)
  366. {
  367. struct omap_mbox *_mbox, *mbox = NULL;
  368. struct omap_mbox **mboxes = mdev->mboxes;
  369. int i;
  370. if (!mboxes)
  371. return NULL;
  372. for (i = 0; (_mbox = mboxes[i]); i++) {
  373. if (!strcmp(_mbox->name, mbox_name)) {
  374. mbox = _mbox;
  375. break;
  376. }
  377. }
  378. return mbox;
  379. }
  380. struct mbox_chan *omap_mbox_request_channel(struct mbox_client *cl,
  381. const char *chan_name)
  382. {
  383. struct device *dev = cl->dev;
  384. struct omap_mbox *mbox = NULL;
  385. struct omap_mbox_device *mdev;
  386. struct mbox_chan *chan;
  387. unsigned long flags;
  388. int ret;
  389. if (!dev)
  390. return ERR_PTR(-ENODEV);
  391. if (dev->of_node) {
  392. pr_err("%s: please use mbox_request_channel(), this API is supported only for OMAP non-DT usage\n",
  393. __func__);
  394. return ERR_PTR(-ENODEV);
  395. }
  396. mutex_lock(&omap_mbox_devices_lock);
  397. list_for_each_entry(mdev, &omap_mbox_devices, elem) {
  398. mbox = omap_mbox_device_find(mdev, chan_name);
  399. if (mbox)
  400. break;
  401. }
  402. mutex_unlock(&omap_mbox_devices_lock);
  403. if (!mbox || !mbox->chan)
  404. return ERR_PTR(-ENOENT);
  405. chan = mbox->chan;
  406. spin_lock_irqsave(&chan->lock, flags);
  407. chan->msg_free = 0;
  408. chan->msg_count = 0;
  409. chan->active_req = NULL;
  410. chan->cl = cl;
  411. init_completion(&chan->tx_complete);
  412. spin_unlock_irqrestore(&chan->lock, flags);
  413. ret = chan->mbox->ops->startup(chan);
  414. if (ret) {
  415. pr_err("Unable to startup the chan (%d)\n", ret);
  416. mbox_free_channel(chan);
  417. chan = ERR_PTR(ret);
  418. }
  419. return chan;
  420. }
  421. EXPORT_SYMBOL(omap_mbox_request_channel);
  422. static struct class omap_mbox_class = { .name = "mbox", };
  423. static int omap_mbox_register(struct omap_mbox_device *mdev)
  424. {
  425. int ret;
  426. int i;
  427. struct omap_mbox **mboxes;
  428. if (!mdev || !mdev->mboxes)
  429. return -EINVAL;
  430. mboxes = mdev->mboxes;
  431. for (i = 0; mboxes[i]; i++) {
  432. struct omap_mbox *mbox = mboxes[i];
  433. mbox->dev = device_create(&omap_mbox_class, mdev->dev,
  434. 0, mbox, "%s", mbox->name);
  435. if (IS_ERR(mbox->dev)) {
  436. ret = PTR_ERR(mbox->dev);
  437. goto err_out;
  438. }
  439. }
  440. mutex_lock(&omap_mbox_devices_lock);
  441. list_add(&mdev->elem, &omap_mbox_devices);
  442. mutex_unlock(&omap_mbox_devices_lock);
  443. ret = mbox_controller_register(&mdev->controller);
  444. err_out:
  445. if (ret) {
  446. while (i--)
  447. device_unregister(mboxes[i]->dev);
  448. }
  449. return ret;
  450. }
  451. static int omap_mbox_unregister(struct omap_mbox_device *mdev)
  452. {
  453. int i;
  454. struct omap_mbox **mboxes;
  455. if (!mdev || !mdev->mboxes)
  456. return -EINVAL;
  457. mutex_lock(&omap_mbox_devices_lock);
  458. list_del(&mdev->elem);
  459. mutex_unlock(&omap_mbox_devices_lock);
  460. mbox_controller_unregister(&mdev->controller);
  461. mboxes = mdev->mboxes;
  462. for (i = 0; mboxes[i]; i++)
  463. device_unregister(mboxes[i]->dev);
  464. return 0;
  465. }
  466. static int omap_mbox_chan_startup(struct mbox_chan *chan)
  467. {
  468. struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
  469. struct omap_mbox_device *mdev = mbox->parent;
  470. int ret = 0;
  471. mutex_lock(&mdev->cfg_lock);
  472. pm_runtime_get_sync(mdev->dev);
  473. ret = omap_mbox_startup(mbox);
  474. if (ret)
  475. pm_runtime_put_sync(mdev->dev);
  476. mutex_unlock(&mdev->cfg_lock);
  477. return ret;
  478. }
  479. static void omap_mbox_chan_shutdown(struct mbox_chan *chan)
  480. {
  481. struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
  482. struct omap_mbox_device *mdev = mbox->parent;
  483. mutex_lock(&mdev->cfg_lock);
  484. omap_mbox_fini(mbox);
  485. pm_runtime_put_sync(mdev->dev);
  486. mutex_unlock(&mdev->cfg_lock);
  487. }
  488. static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, void *data)
  489. {
  490. int ret = -EBUSY;
  491. if (!mbox_fifo_full(mbox)) {
  492. _omap_mbox_enable_irq(mbox, IRQ_RX);
  493. mbox_fifo_write(mbox, (mbox_msg_t)data);
  494. ret = 0;
  495. _omap_mbox_disable_irq(mbox, IRQ_RX);
  496. /* we must read and ack the interrupt directly from here */
  497. mbox_fifo_read(mbox);
  498. ack_mbox_irq(mbox, IRQ_RX);
  499. }
  500. return ret;
  501. }
  502. static int omap_mbox_chan_send(struct omap_mbox *mbox, void *data)
  503. {
  504. int ret = -EBUSY;
  505. if (!mbox_fifo_full(mbox)) {
  506. mbox_fifo_write(mbox, (mbox_msg_t)data);
  507. ret = 0;
  508. }
  509. /* always enable the interrupt */
  510. _omap_mbox_enable_irq(mbox, IRQ_TX);
  511. return ret;
  512. }
  513. static int omap_mbox_chan_send_data(struct mbox_chan *chan, void *data)
  514. {
  515. struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
  516. int ret;
  517. if (!mbox)
  518. return -EINVAL;
  519. if (mbox->send_no_irq)
  520. ret = omap_mbox_chan_send_noirq(mbox, data);
  521. else
  522. ret = omap_mbox_chan_send(mbox, data);
  523. return ret;
  524. }
  525. static const struct mbox_chan_ops omap_mbox_chan_ops = {
  526. .startup = omap_mbox_chan_startup,
  527. .send_data = omap_mbox_chan_send_data,
  528. .shutdown = omap_mbox_chan_shutdown,
  529. };
  530. static const struct of_device_id omap_mailbox_of_match[] = {
  531. {
  532. .compatible = "ti,omap2-mailbox",
  533. .data = (void *)MBOX_INTR_CFG_TYPE1,
  534. },
  535. {
  536. .compatible = "ti,omap3-mailbox",
  537. .data = (void *)MBOX_INTR_CFG_TYPE1,
  538. },
  539. {
  540. .compatible = "ti,omap4-mailbox",
  541. .data = (void *)MBOX_INTR_CFG_TYPE2,
  542. },
  543. {
  544. /* end */
  545. },
  546. };
  547. MODULE_DEVICE_TABLE(of, omap_mailbox_of_match);
  548. static struct mbox_chan *omap_mbox_of_xlate(struct mbox_controller *controller,
  549. const struct of_phandle_args *sp)
  550. {
  551. phandle phandle = sp->args[0];
  552. struct device_node *node;
  553. struct omap_mbox_device *mdev;
  554. struct omap_mbox *mbox;
  555. mdev = container_of(controller, struct omap_mbox_device, controller);
  556. if (WARN_ON(!mdev))
  557. return ERR_PTR(-EINVAL);
  558. node = of_find_node_by_phandle(phandle);
  559. if (!node) {
  560. pr_err("%s: could not find node phandle 0x%x\n",
  561. __func__, phandle);
  562. return ERR_PTR(-ENODEV);
  563. }
  564. mbox = omap_mbox_device_find(mdev, node->name);
  565. of_node_put(node);
  566. return mbox ? mbox->chan : ERR_PTR(-ENOENT);
  567. }
  568. static int omap_mbox_probe(struct platform_device *pdev)
  569. {
  570. struct resource *mem;
  571. int ret;
  572. struct mbox_chan *chnls;
  573. struct omap_mbox **list, *mbox, *mboxblk;
  574. struct omap_mbox_pdata *pdata = pdev->dev.platform_data;
  575. struct omap_mbox_dev_info *info = NULL;
  576. struct omap_mbox_fifo_info *finfo, *finfoblk;
  577. struct omap_mbox_device *mdev;
  578. struct omap_mbox_fifo *fifo;
  579. struct device_node *node = pdev->dev.of_node;
  580. struct device_node *child;
  581. const struct of_device_id *match;
  582. u32 intr_type, info_count;
  583. u32 num_users, num_fifos;
  584. u32 tmp[3];
  585. u32 l;
  586. int i;
  587. if (!node && (!pdata || !pdata->info_cnt || !pdata->info)) {
  588. pr_err("%s: platform not supported\n", __func__);
  589. return -ENODEV;
  590. }
  591. if (node) {
  592. match = of_match_device(omap_mailbox_of_match, &pdev->dev);
  593. if (!match)
  594. return -ENODEV;
  595. intr_type = (u32)match->data;
  596. if (of_property_read_u32(node, "ti,mbox-num-users",
  597. &num_users))
  598. return -ENODEV;
  599. if (of_property_read_u32(node, "ti,mbox-num-fifos",
  600. &num_fifos))
  601. return -ENODEV;
  602. info_count = of_get_available_child_count(node);
  603. if (!info_count) {
  604. dev_err(&pdev->dev, "no available mbox devices found\n");
  605. return -ENODEV;
  606. }
  607. } else { /* non-DT device creation */
  608. info_count = pdata->info_cnt;
  609. info = pdata->info;
  610. intr_type = pdata->intr_type;
  611. num_users = pdata->num_users;
  612. num_fifos = pdata->num_fifos;
  613. }
  614. finfoblk = devm_kzalloc(&pdev->dev, info_count * sizeof(*finfoblk),
  615. GFP_KERNEL);
  616. if (!finfoblk)
  617. return -ENOMEM;
  618. finfo = finfoblk;
  619. child = NULL;
  620. for (i = 0; i < info_count; i++, finfo++) {
  621. if (node) {
  622. child = of_get_next_available_child(node, child);
  623. ret = of_property_read_u32_array(child, "ti,mbox-tx",
  624. tmp, ARRAY_SIZE(tmp));
  625. if (ret)
  626. return ret;
  627. finfo->tx_id = tmp[0];
  628. finfo->tx_irq = tmp[1];
  629. finfo->tx_usr = tmp[2];
  630. ret = of_property_read_u32_array(child, "ti,mbox-rx",
  631. tmp, ARRAY_SIZE(tmp));
  632. if (ret)
  633. return ret;
  634. finfo->rx_id = tmp[0];
  635. finfo->rx_irq = tmp[1];
  636. finfo->rx_usr = tmp[2];
  637. finfo->name = child->name;
  638. if (of_find_property(child, "ti,mbox-send-noirq", NULL))
  639. finfo->send_no_irq = true;
  640. } else {
  641. finfo->tx_id = info->tx_id;
  642. finfo->rx_id = info->rx_id;
  643. finfo->tx_usr = info->usr_id;
  644. finfo->tx_irq = info->irq_id;
  645. finfo->rx_usr = info->usr_id;
  646. finfo->rx_irq = info->irq_id;
  647. finfo->name = info->name;
  648. info++;
  649. }
  650. if (finfo->tx_id >= num_fifos || finfo->rx_id >= num_fifos ||
  651. finfo->tx_usr >= num_users || finfo->rx_usr >= num_users)
  652. return -EINVAL;
  653. }
  654. mdev = devm_kzalloc(&pdev->dev, sizeof(*mdev), GFP_KERNEL);
  655. if (!mdev)
  656. return -ENOMEM;
  657. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  658. mdev->mbox_base = devm_ioremap_resource(&pdev->dev, mem);
  659. if (IS_ERR(mdev->mbox_base))
  660. return PTR_ERR(mdev->mbox_base);
  661. /* allocate one extra for marking end of list */
  662. list = devm_kzalloc(&pdev->dev, (info_count + 1) * sizeof(*list),
  663. GFP_KERNEL);
  664. if (!list)
  665. return -ENOMEM;
  666. chnls = devm_kzalloc(&pdev->dev, (info_count + 1) * sizeof(*chnls),
  667. GFP_KERNEL);
  668. if (!chnls)
  669. return -ENOMEM;
  670. mboxblk = devm_kzalloc(&pdev->dev, info_count * sizeof(*mbox),
  671. GFP_KERNEL);
  672. if (!mboxblk)
  673. return -ENOMEM;
  674. mbox = mboxblk;
  675. finfo = finfoblk;
  676. for (i = 0; i < info_count; i++, finfo++) {
  677. fifo = &mbox->tx_fifo;
  678. fifo->msg = MAILBOX_MESSAGE(finfo->tx_id);
  679. fifo->fifo_stat = MAILBOX_FIFOSTATUS(finfo->tx_id);
  680. fifo->intr_bit = MAILBOX_IRQ_NOTFULL(finfo->tx_id);
  681. fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->tx_usr);
  682. fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->tx_usr);
  683. fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->tx_usr);
  684. fifo = &mbox->rx_fifo;
  685. fifo->msg = MAILBOX_MESSAGE(finfo->rx_id);
  686. fifo->msg_stat = MAILBOX_MSGSTATUS(finfo->rx_id);
  687. fifo->intr_bit = MAILBOX_IRQ_NEWMSG(finfo->rx_id);
  688. fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->rx_usr);
  689. fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->rx_usr);
  690. fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->rx_usr);
  691. mbox->send_no_irq = finfo->send_no_irq;
  692. mbox->intr_type = intr_type;
  693. mbox->parent = mdev;
  694. mbox->name = finfo->name;
  695. mbox->irq = platform_get_irq(pdev, finfo->tx_irq);
  696. if (mbox->irq < 0)
  697. return mbox->irq;
  698. mbox->chan = &chnls[i];
  699. chnls[i].con_priv = mbox;
  700. list[i] = mbox++;
  701. }
  702. mutex_init(&mdev->cfg_lock);
  703. mdev->dev = &pdev->dev;
  704. mdev->num_users = num_users;
  705. mdev->num_fifos = num_fifos;
  706. mdev->mboxes = list;
  707. /* OMAP does not have a Tx-Done IRQ, but rather a Tx-Ready IRQ */
  708. mdev->controller.txdone_irq = true;
  709. mdev->controller.dev = mdev->dev;
  710. mdev->controller.ops = &omap_mbox_chan_ops;
  711. mdev->controller.chans = chnls;
  712. mdev->controller.num_chans = info_count;
  713. mdev->controller.of_xlate = omap_mbox_of_xlate;
  714. ret = omap_mbox_register(mdev);
  715. if (ret)
  716. return ret;
  717. platform_set_drvdata(pdev, mdev);
  718. pm_runtime_enable(mdev->dev);
  719. ret = pm_runtime_get_sync(mdev->dev);
  720. if (ret < 0) {
  721. pm_runtime_put_noidle(mdev->dev);
  722. goto unregister;
  723. }
  724. /*
  725. * just print the raw revision register, the format is not
  726. * uniform across all SoCs
  727. */
  728. l = mbox_read_reg(mdev, MAILBOX_REVISION);
  729. dev_info(mdev->dev, "omap mailbox rev 0x%x\n", l);
  730. ret = pm_runtime_put_sync(mdev->dev);
  731. if (ret < 0)
  732. goto unregister;
  733. devm_kfree(&pdev->dev, finfoblk);
  734. return 0;
  735. unregister:
  736. pm_runtime_disable(mdev->dev);
  737. omap_mbox_unregister(mdev);
  738. return ret;
  739. }
  740. static int omap_mbox_remove(struct platform_device *pdev)
  741. {
  742. struct omap_mbox_device *mdev = platform_get_drvdata(pdev);
  743. pm_runtime_disable(mdev->dev);
  744. omap_mbox_unregister(mdev);
  745. return 0;
  746. }
  747. static struct platform_driver omap_mbox_driver = {
  748. .probe = omap_mbox_probe,
  749. .remove = omap_mbox_remove,
  750. .driver = {
  751. .name = "omap-mailbox",
  752. .of_match_table = of_match_ptr(omap_mailbox_of_match),
  753. },
  754. };
  755. static int __init omap_mbox_init(void)
  756. {
  757. int err;
  758. err = class_register(&omap_mbox_class);
  759. if (err)
  760. return err;
  761. /* kfifo size sanity check: alignment and minimal size */
  762. mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t));
  763. mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size,
  764. sizeof(mbox_msg_t));
  765. return platform_driver_register(&omap_mbox_driver);
  766. }
  767. subsys_initcall(omap_mbox_init);
  768. static void __exit omap_mbox_exit(void)
  769. {
  770. platform_driver_unregister(&omap_mbox_driver);
  771. class_unregister(&omap_mbox_class);
  772. }
  773. module_exit(omap_mbox_exit);
  774. MODULE_LICENSE("GPL v2");
  775. MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging");
  776. MODULE_AUTHOR("Toshihiro Kobayashi");
  777. MODULE_AUTHOR("Hiroshi DOYU");