drxk_map.h 37 KB

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  1. #define AUD_COMM_EXEC__A 0x1000000
  2. #define AUD_COMM_EXEC_STOP 0x0
  3. #define FEC_COMM_EXEC__A 0x1C00000
  4. #define FEC_COMM_EXEC_STOP 0x0
  5. #define FEC_COMM_EXEC_ACTIVE 0x1
  6. #define FEC_DI_COMM_EXEC__A 0x1C20000
  7. #define FEC_DI_COMM_EXEC_STOP 0x0
  8. #define FEC_DI_INPUT_CTL__A 0x1C20016
  9. #define FEC_RS_COMM_EXEC__A 0x1C30000
  10. #define FEC_RS_COMM_EXEC_STOP 0x0
  11. #define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012
  12. #define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013
  13. #define FEC_RS_NR_BIT_ERRORS__A 0x1C30014
  14. #define FEC_OC_MODE__A 0x1C40011
  15. #define FEC_OC_MODE_PARITY__M 0x1
  16. #define FEC_OC_DTO_MODE__A 0x1C40014
  17. #define FEC_OC_DTO_MODE_DYNAMIC__M 0x1
  18. #define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4
  19. #define FEC_OC_DTO_PERIOD__A 0x1C40015
  20. #define FEC_OC_DTO_BURST_LEN__A 0x1C40018
  21. #define FEC_OC_FCT_MODE__A 0x1C4001A
  22. #define FEC_OC_FCT_MODE__PRE 0x0
  23. #define FEC_OC_FCT_MODE_RAT_ENA__M 0x1
  24. #define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2
  25. #define FEC_OC_TMD_MODE__A 0x1C4001E
  26. #define FEC_OC_TMD_COUNT__A 0x1C4001F
  27. #define FEC_OC_TMD_HI_MARGIN__A 0x1C40020
  28. #define FEC_OC_TMD_LO_MARGIN__A 0x1C40021
  29. #define FEC_OC_TMD_INT_UPD_RATE__A 0x1C40023
  30. #define FEC_OC_AVR_PARM_A__A 0x1C40026
  31. #define FEC_OC_AVR_PARM_B__A 0x1C40027
  32. #define FEC_OC_RCN_GAIN__A 0x1C4002E
  33. #define FEC_OC_RCN_CTL_RATE_LO__A 0x1C40030
  34. #define FEC_OC_RCN_CTL_STEP_LO__A 0x1C40032
  35. #define FEC_OC_RCN_CTL_STEP_HI__A 0x1C40033
  36. #define FEC_OC_SNC_MODE__A 0x1C40040
  37. #define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10
  38. #define FEC_OC_SNC_LWM__A 0x1C40041
  39. #define FEC_OC_SNC_HWM__A 0x1C40042
  40. #define FEC_OC_SNC_UNLOCK__A 0x1C40043
  41. #define FEC_OC_SNC_FAIL_PERIOD__A 0x1C40046
  42. #define FEC_OC_IPR_MODE__A 0x1C40048
  43. #define FEC_OC_IPR_MODE_SERIAL__M 0x1
  44. #define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4
  45. #define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10
  46. #define FEC_OC_IPR_INVERT__A 0x1C40049
  47. #define FEC_OC_IPR_INVERT_MD0__M 0x1
  48. #define FEC_OC_IPR_INVERT_MD1__M 0x2
  49. #define FEC_OC_IPR_INVERT_MD2__M 0x4
  50. #define FEC_OC_IPR_INVERT_MD3__M 0x8
  51. #define FEC_OC_IPR_INVERT_MD4__M 0x10
  52. #define FEC_OC_IPR_INVERT_MD5__M 0x20
  53. #define FEC_OC_IPR_INVERT_MD6__M 0x40
  54. #define FEC_OC_IPR_INVERT_MD7__M 0x80
  55. #define FEC_OC_IPR_INVERT_MERR__M 0x100
  56. #define FEC_OC_IPR_INVERT_MSTRT__M 0x200
  57. #define FEC_OC_IPR_INVERT_MVAL__M 0x400
  58. #define FEC_OC_IPR_INVERT_MCLK__M 0x800
  59. #define FEC_OC_OCR_INVERT__A 0x1C40052
  60. #define IQM_COMM_EXEC__A 0x1800000
  61. #define IQM_COMM_EXEC_B_STOP 0x0
  62. #define IQM_COMM_EXEC_B_ACTIVE 0x1
  63. #define IQM_FS_RATE_OFS_LO__A 0x1820010
  64. #define IQM_FS_ADJ_SEL__A 0x1820014
  65. #define IQM_FS_ADJ_SEL_B_OFF 0x0
  66. #define IQM_FS_ADJ_SEL_B_QAM 0x1
  67. #define IQM_FS_ADJ_SEL_B_VSB 0x2
  68. #define IQM_FD_RATESEL__A 0x1830010
  69. #define IQM_RC_RATE_OFS_LO__A 0x1840010
  70. #define IQM_RC_RATE_OFS_LO__W 16
  71. #define IQM_RC_RATE_OFS_LO__M 0xFFFF
  72. #define IQM_RC_RATE_OFS_HI__M 0xFF
  73. #define IQM_RC_ADJ_SEL__A 0x1840014
  74. #define IQM_RC_ADJ_SEL_B_OFF 0x0
  75. #define IQM_RC_ADJ_SEL_B_QAM 0x1
  76. #define IQM_RC_ADJ_SEL_B_VSB 0x2
  77. #define IQM_RC_STRETCH__A 0x1840016
  78. #define IQM_CF_COMM_INT_MSK__A 0x1860006
  79. #define IQM_CF_SYMMETRIC__A 0x1860010
  80. #define IQM_CF_MIDTAP__A 0x1860011
  81. #define IQM_CF_MIDTAP_RE__B 0
  82. #define IQM_CF_MIDTAP_IM__B 1
  83. #define IQM_CF_OUT_ENA__A 0x1860012
  84. #define IQM_CF_OUT_ENA_QAM__B 1
  85. #define IQM_CF_OUT_ENA_OFDM__M 0x4
  86. #define IQM_CF_ADJ_SEL__A 0x1860013
  87. #define IQM_CF_SCALE__A 0x1860014
  88. #define IQM_CF_SCALE_SH__A 0x1860015
  89. #define IQM_CF_SCALE_SH__PRE 0x0
  90. #define IQM_CF_POW_MEAS_LEN__A 0x1860017
  91. #define IQM_CF_DS_ENA__A 0x1860019
  92. #define IQM_CF_TAP_RE0__A 0x1860020
  93. #define IQM_CF_TAP_IM0__A 0x1860040
  94. #define IQM_CF_CLP_VAL__A 0x1860060
  95. #define IQM_CF_DATATH__A 0x1860061
  96. #define IQM_CF_PKDTH__A 0x1860062
  97. #define IQM_CF_WND_LEN__A 0x1860063
  98. #define IQM_CF_DET_LCT__A 0x1860064
  99. #define IQM_CF_BYPASSDET__A 0x1860067
  100. #define IQM_AF_COMM_EXEC__A 0x1870000
  101. #define IQM_AF_COMM_EXEC_ACTIVE 0x1
  102. #define IQM_AF_CLKNEG__A 0x1870012
  103. #define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2
  104. #define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0
  105. #define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2
  106. #define IQM_AF_START_LOCK__A 0x187001B
  107. #define IQM_AF_PHASE0__A 0x187001C
  108. #define IQM_AF_PHASE1__A 0x187001D
  109. #define IQM_AF_PHASE2__A 0x187001E
  110. #define IQM_AF_CLP_LEN__A 0x1870023
  111. #define IQM_AF_CLP_TH__A 0x1870024
  112. #define IQM_AF_SNS_LEN__A 0x1870026
  113. #define IQM_AF_AGC_IF__A 0x1870028
  114. #define IQM_AF_AGC_RF__A 0x1870029
  115. #define IQM_AF_PDREF__A 0x187002B
  116. #define IQM_AF_PDREF__M 0x1F
  117. #define IQM_AF_STDBY__A 0x187002C
  118. #define IQM_AF_STDBY_STDBY_ADC_STANDBY 0x2
  119. #define IQM_AF_STDBY_STDBY_AMP_STANDBY 0x4
  120. #define IQM_AF_STDBY_STDBY_PD_STANDBY 0x8
  121. #define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10
  122. #define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20
  123. #define IQM_AF_AMUX__A 0x187002D
  124. #define IQM_AF_AMUX_SIGNAL2ADC 0x1
  125. #define IQM_AF_UPD_SEL__A 0x187002F
  126. #define IQM_AF_INC_LCT__A 0x1870034
  127. #define IQM_AF_INC_BYPASS__A 0x1870036
  128. #define OFDM_CP_COMM_EXEC__A 0x2800000
  129. #define OFDM_CP_COMM_EXEC_STOP 0x0
  130. #define OFDM_EC_SB_PRIOR__A 0x3410013
  131. #define OFDM_EC_SB_PRIOR_HI 0x0
  132. #define OFDM_EC_SB_PRIOR_LO 0x1
  133. #define OFDM_EC_VD_ERR_BIT_CNT__A 0x3420017
  134. #define OFDM_EC_VD_IN_BIT_CNT__A 0x3420018
  135. #define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054
  136. #define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3
  137. #define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2
  138. #define OFDM_EQ_TOP_TD_TPS_CODE_HP__A 0x3010056
  139. #define OFDM_EQ_TOP_TD_TPS_CODE_HP__M 0x7
  140. #define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8 0x4
  141. #define OFDM_EQ_TOP_TD_SQR_ERR_I__A 0x301005E
  142. #define OFDM_EQ_TOP_TD_SQR_ERR_Q__A 0x301005F
  143. #define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A 0x3010060
  144. #define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A 0x3010061
  145. #define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A 0x3010062
  146. #define OFDM_LC_COMM_EXEC__A 0x3800000
  147. #define OFDM_LC_COMM_EXEC_STOP 0x0
  148. #define OFDM_SC_COMM_EXEC__A 0x3C00000
  149. #define OFDM_SC_COMM_EXEC_STOP 0x0
  150. #define OFDM_SC_COMM_STATE__A 0x3C00001
  151. #define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040
  152. #define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041
  153. #define OFDM_SC_RA_RAM_CMD_ADDR__A 0x3C20042
  154. #define OFDM_SC_RA_RAM_CMD__A 0x3C20043
  155. #define OFDM_SC_RA_RAM_CMD_NULL 0x0
  156. #define OFDM_SC_RA_RAM_CMD_PROC_START 0x1
  157. #define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3
  158. #define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4
  159. #define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM 0x5
  160. #define OFDM_SC_RA_RAM_CMD_USER_IO 0x6
  161. #define OFDM_SC_RA_RAM_CMD_SET_TIMER 0x7
  162. #define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8
  163. #define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1
  164. #define OFDM_SC_RA_RAM_LOCKTRACK_MIN 0x1
  165. #define OFDM_SC_RA_RAM_OP_PARAM__A 0x3C20048
  166. #define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3
  167. #define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0
  168. #define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1
  169. #define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32 0x0
  170. #define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16 0x4
  171. #define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8 0x8
  172. #define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4 0xC
  173. #define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0
  174. #define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10
  175. #define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20
  176. #define OFDM_SC_RA_RAM_OP_PARAM_HIER_NO 0x0
  177. #define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1 0x40
  178. #define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2 0x80
  179. #define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0
  180. #define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0
  181. #define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200
  182. #define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400
  183. #define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600
  184. #define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800
  185. #define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0
  186. #define OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000
  187. #define OFDM_SC_RA_RAM_OP_AUTO_MODE__M 0x1
  188. #define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M 0x2
  189. #define OFDM_SC_RA_RAM_OP_AUTO_CONST__M 0x4
  190. #define OFDM_SC_RA_RAM_OP_AUTO_HIER__M 0x8
  191. #define OFDM_SC_RA_RAM_OP_AUTO_RATE__M 0x10
  192. #define OFDM_SC_RA_RAM_LOCK__A 0x3C2004B
  193. #define OFDM_SC_RA_RAM_LOCK_DEMOD__M 0x1
  194. #define OFDM_SC_RA_RAM_LOCK_FEC__M 0x2
  195. #define OFDM_SC_RA_RAM_LOCK_MPEG__M 0x4
  196. #define OFDM_SC_RA_RAM_LOCK_NODVBT__M 0x8
  197. #define OFDM_SC_RA_RAM_BE_OPT_DELAY__A 0x3C2004D
  198. #define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x3C2004E
  199. #define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F
  200. #define OFDM_SC_RA_RAM_ECHO_THRES_8K__B 0
  201. #define OFDM_SC_RA_RAM_ECHO_THRES_8K__M 0xFF
  202. #define OFDM_SC_RA_RAM_ECHO_THRES_2K__B 8
  203. #define OFDM_SC_RA_RAM_ECHO_THRES_2K__M 0xFF00
  204. #define OFDM_SC_RA_RAM_CONFIG__A 0x3C20050
  205. #define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M 0x800
  206. #define OFDM_SC_RA_RAM_FR_THRES_8K__A 0x3C2007D
  207. #define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x3C200E0
  208. #define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x3C200E1
  209. #define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x3C200E3
  210. #define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x3C200E4
  211. #define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A 0x3C200F8
  212. #define QAM_COMM_EXEC__A 0x1400000
  213. #define QAM_COMM_EXEC_STOP 0x0
  214. #define QAM_COMM_EXEC_ACTIVE 0x1
  215. #define QAM_TOP_ANNEX_A 0x0
  216. #define QAM_TOP_ANNEX_C 0x2
  217. #define QAM_SL_ERR_POWER__A 0x1430017
  218. #define QAM_DQ_QUAL_FUN0__A 0x1440018
  219. #define QAM_DQ_QUAL_FUN1__A 0x1440019
  220. #define QAM_DQ_QUAL_FUN2__A 0x144001A
  221. #define QAM_DQ_QUAL_FUN3__A 0x144001B
  222. #define QAM_DQ_QUAL_FUN4__A 0x144001C
  223. #define QAM_DQ_QUAL_FUN5__A 0x144001D
  224. #define QAM_LC_MODE__A 0x1450010
  225. #define QAM_LC_QUAL_TAB0__A 0x1450018
  226. #define QAM_LC_QUAL_TAB1__A 0x1450019
  227. #define QAM_LC_QUAL_TAB2__A 0x145001A
  228. #define QAM_LC_QUAL_TAB3__A 0x145001B
  229. #define QAM_LC_QUAL_TAB4__A 0x145001C
  230. #define QAM_LC_QUAL_TAB5__A 0x145001D
  231. #define QAM_LC_QUAL_TAB6__A 0x145001E
  232. #define QAM_LC_QUAL_TAB8__A 0x145001F
  233. #define QAM_LC_QUAL_TAB9__A 0x1450020
  234. #define QAM_LC_QUAL_TAB10__A 0x1450021
  235. #define QAM_LC_QUAL_TAB12__A 0x1450022
  236. #define QAM_LC_QUAL_TAB15__A 0x1450023
  237. #define QAM_LC_QUAL_TAB16__A 0x1450024
  238. #define QAM_LC_QUAL_TAB20__A 0x1450025
  239. #define QAM_LC_QUAL_TAB25__A 0x1450026
  240. #define QAM_LC_LPF_FACTORP__A 0x1450028
  241. #define QAM_LC_LPF_FACTORI__A 0x1450029
  242. #define QAM_LC_RATE_LIMIT__A 0x145002A
  243. #define QAM_LC_SYMBOL_FREQ__A 0x145002B
  244. #define QAM_SY_TIMEOUT__A 0x1470011
  245. #define QAM_SY_TIMEOUT__PRE 0x3A98
  246. #define QAM_SY_SYNC_LWM__A 0x1470012
  247. #define QAM_SY_SYNC_AWM__A 0x1470013
  248. #define QAM_SY_SYNC_HWM__A 0x1470014
  249. #define QAM_SY_SP_INV__A 0x1470017
  250. #define QAM_SY_SP_INV_SPECTRUM_INV_DIS 0x0
  251. #define SCU_COMM_EXEC__A 0x800000
  252. #define SCU_COMM_EXEC_STOP 0x0
  253. #define SCU_COMM_EXEC_ACTIVE 0x1
  254. #define SCU_COMM_EXEC_HOLD 0x2
  255. #define SCU_RAM_DRIVER_DEBUG__A 0x831EBF
  256. #define SCU_RAM_QAM_FSM_STEP_PERIOD__A 0x831EC4
  257. #define SCU_RAM_GPIO__A 0x831EC7
  258. #define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0
  259. #define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8
  260. #define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB
  261. #define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A 0x831F05
  262. #define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831F15
  263. #define SCU_RAM_AGC_KI_CYCLEN__A 0x831F17
  264. #define SCU_RAM_AGC_SNS_CYCLEN__A 0x831F18
  265. #define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831F19
  266. #define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831F1A
  267. #define SCU_RAM_AGC_RF_MAX__A 0x831F1B
  268. #define SCU_RAM_AGC_CONFIG__A 0x831F24
  269. #define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M 0x1
  270. #define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M 0x2
  271. #define SCU_RAM_AGC_CONFIG_INV_IF_POL__M 0x100
  272. #define SCU_RAM_AGC_CONFIG_INV_RF_POL__M 0x200
  273. #define SCU_RAM_AGC_KI__A 0x831F25
  274. #define SCU_RAM_AGC_KI_RF__B 4
  275. #define SCU_RAM_AGC_KI_RF__M 0xF0
  276. #define SCU_RAM_AGC_KI_IF__B 8
  277. #define SCU_RAM_AGC_KI_IF__M 0xF00
  278. #define SCU_RAM_AGC_KI_RED__A 0x831F26
  279. #define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2
  280. #define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC
  281. #define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4
  282. #define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30
  283. #define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831F27
  284. #define SCU_RAM_AGC_KI_MINGAIN__A 0x831F28
  285. #define SCU_RAM_AGC_KI_MAXGAIN__A 0x831F29
  286. #define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831F2A
  287. #define SCU_RAM_AGC_KI_MIN__A 0x831F2B
  288. #define SCU_RAM_AGC_KI_MAX__A 0x831F2C
  289. #define SCU_RAM_AGC_CLP_SUM__A 0x831F2D
  290. #define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831F2E
  291. #define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831F2F
  292. #define SCU_RAM_AGC_CLP_CYCLEN__A 0x831F30
  293. #define SCU_RAM_AGC_CLP_CYCCNT__A 0x831F31
  294. #define SCU_RAM_AGC_CLP_DIR_TO__A 0x831F32
  295. #define SCU_RAM_AGC_CLP_DIR_WD__A 0x831F33
  296. #define SCU_RAM_AGC_CLP_DIR_STP__A 0x831F34
  297. #define SCU_RAM_AGC_SNS_SUM__A 0x831F35
  298. #define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831F36
  299. #define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831F37
  300. #define SCU_RAM_AGC_SNS_CYCCNT__A 0x831F38
  301. #define SCU_RAM_AGC_SNS_DIR_TO__A 0x831F39
  302. #define SCU_RAM_AGC_SNS_DIR_WD__A 0x831F3A
  303. #define SCU_RAM_AGC_SNS_DIR_STP__A 0x831F3B
  304. #define SCU_RAM_AGC_INGAIN_TGT__A 0x831F3D
  305. #define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E
  306. #define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F
  307. #define SCU_RAM_AGC_IF_IACCU_HI__A 0x831F40
  308. #define SCU_RAM_AGC_IF_IACCU_LO__A 0x831F41
  309. #define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831F42
  310. #define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831F43
  311. #define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44
  312. #define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45
  313. #define SCU_RAM_AGC_RF_IACCU_LO__A 0x831F46
  314. #define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831F47
  315. #define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84
  316. #define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85
  317. #define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86
  318. #define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87
  319. #define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88
  320. #define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89
  321. #define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A
  322. #define SCU_RAM_QAM_FSM_RTH__A 0x831F8E
  323. #define SCU_RAM_QAM_FSM_FTH__A 0x831F8F
  324. #define SCU_RAM_QAM_FSM_PTH__A 0x831F90
  325. #define SCU_RAM_QAM_FSM_MTH__A 0x831F91
  326. #define SCU_RAM_QAM_FSM_CTH__A 0x831F92
  327. #define SCU_RAM_QAM_FSM_QTH__A 0x831F93
  328. #define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94
  329. #define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95
  330. #define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96
  331. #define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97
  332. #define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99
  333. #define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A
  334. #define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B
  335. #define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C
  336. #define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D
  337. #define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E
  338. #define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F
  339. #define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0
  340. #define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1
  341. #define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2
  342. #define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3
  343. #define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4
  344. #define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5
  345. #define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6
  346. #define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7
  347. #define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8
  348. #define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9
  349. #define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA
  350. #define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB
  351. #define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC
  352. #define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD
  353. #define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE
  354. #define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF
  355. #define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0
  356. #define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1
  357. #define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2
  358. #define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000
  359. #define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000
  360. #define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000
  361. #define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA
  362. #define SCU_RAM_DRIVER_VER_HI__A 0x831FEB
  363. #define SCU_RAM_DRIVER_VER_LO__A 0x831FEC
  364. #define SCU_RAM_PARAM_15__A 0x831FED
  365. #define SCU_RAM_PARAM_0__A 0x831FFC
  366. #define SCU_RAM_COMMAND__A 0x831FFD
  367. #define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1
  368. #define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2
  369. #define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3
  370. #define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4
  371. #define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5
  372. #define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9
  373. #define SCU_RAM_COMMAND_STANDARD_QAM 0x200
  374. #define SCU_RAM_COMMAND_STANDARD_OFDM 0x400
  375. #define SIO_TOP_COMM_KEY__A 0x41000F
  376. #define SIO_TOP_COMM_KEY_KEY 0xFABA
  377. #define SIO_TOP_JTAGID_LO__A 0x410012
  378. #define SIO_HI_RA_RAM_RES__A 0x420031
  379. #define SIO_HI_RA_RAM_CMD__A 0x420032
  380. #define SIO_HI_RA_RAM_CMD_RESET 0x2
  381. #define SIO_HI_RA_RAM_CMD_CONFIG 0x3
  382. #define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7
  383. #define SIO_HI_RA_RAM_PAR_1__A 0x420033
  384. #define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945
  385. #define SIO_HI_RA_RAM_PAR_2__A 0x420034
  386. #define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F
  387. #define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0
  388. #define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4
  389. #define SIO_HI_RA_RAM_PAR_3__A 0x420035
  390. #define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F
  391. #define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7
  392. #define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0
  393. #define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8
  394. #define SIO_HI_RA_RAM_PAR_4__A 0x420036
  395. #define SIO_HI_RA_RAM_PAR_5__A 0x420037
  396. #define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1
  397. #define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8
  398. #define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8
  399. #define SIO_HI_RA_RAM_PAR_6__A 0x420038
  400. #define SIO_CC_PLL_LOCK__A 0x450012
  401. #define SIO_CC_PWD_MODE__A 0x450015
  402. #define SIO_CC_PWD_MODE_LEVEL_NONE 0x0
  403. #define SIO_CC_PWD_MODE_LEVEL_OFDM 0x1
  404. #define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2
  405. #define SIO_CC_PWD_MODE_LEVEL_PLL 0x3
  406. #define SIO_CC_PWD_MODE_LEVEL_OSC 0x4
  407. #define SIO_CC_SOFT_RST__A 0x450016
  408. #define SIO_CC_SOFT_RST_OFDM__M 0x1
  409. #define SIO_CC_SOFT_RST_SYS__M 0x2
  410. #define SIO_CC_SOFT_RST_OSC__M 0x4
  411. #define SIO_CC_UPDATE__A 0x450017
  412. #define SIO_CC_UPDATE_KEY 0xFABA
  413. #define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010
  414. #define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0
  415. #define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1
  416. #define SIO_OFDM_SH_OFDM_RING_STATUS__A 0x470012
  417. #define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN 0x0
  418. #define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED 0x1
  419. #define SIO_BL_COMM_EXEC__A 0x480000
  420. #define SIO_BL_COMM_EXEC_ACTIVE 0x1
  421. #define SIO_BL_STATUS__A 0x480010
  422. #define SIO_BL_MODE__A 0x480011
  423. #define SIO_BL_MODE_DIRECT 0x0
  424. #define SIO_BL_MODE_CHAIN 0x1
  425. #define SIO_BL_ENABLE__A 0x480012
  426. #define SIO_BL_ENABLE_ON 0x1
  427. #define SIO_BL_TGT_HDR__A 0x480014
  428. #define SIO_BL_TGT_ADDR__A 0x480015
  429. #define SIO_BL_SRC_ADDR__A 0x480016
  430. #define SIO_BL_SRC_LEN__A 0x480017
  431. #define SIO_BL_CHAIN_ADDR__A 0x480018
  432. #define SIO_BL_CHAIN_LEN__A 0x480019
  433. #define SIO_PDR_MON_CFG__A 0x7F0010
  434. #define SIO_PDR_UIO_IN_HI__A 0x7F0015
  435. #define SIO_PDR_UIO_OUT_LO__A 0x7F0016
  436. #define SIO_PDR_OHW_CFG__A 0x7F001F
  437. #define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3
  438. #define SIO_PDR_GPIO_CFG__A 0x7F0021
  439. #define SIO_PDR_MSTRT_CFG__A 0x7F0025
  440. #define SIO_PDR_MERR_CFG__A 0x7F0026
  441. #define SIO_PDR_MCLK_CFG__A 0x7F0028
  442. #define SIO_PDR_MCLK_CFG_DRIVE__B 3
  443. #define SIO_PDR_MVAL_CFG__A 0x7F0029
  444. #define SIO_PDR_MD0_CFG__A 0x7F002A
  445. #define SIO_PDR_MD0_CFG_DRIVE__B 3
  446. #define SIO_PDR_MD1_CFG__A 0x7F002B
  447. #define SIO_PDR_MD2_CFG__A 0x7F002C
  448. #define SIO_PDR_MD3_CFG__A 0x7F002D
  449. #define SIO_PDR_MD4_CFG__A 0x7F002F
  450. #define SIO_PDR_MD5_CFG__A 0x7F0030
  451. #define SIO_PDR_MD6_CFG__A 0x7F0031
  452. #define SIO_PDR_MD7_CFG__A 0x7F0032
  453. #define SIO_PDR_SMA_RX_CFG__A 0x7F0037
  454. #define SIO_PDR_SMA_TX_CFG__A 0x7F0038