mb86a16.c 46 KB

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  1. /*
  2. Fujitsu MB86A16 DVB-S/DSS DC Receiver driver
  3. Copyright (C) Manu Abraham (abraham.manu@gmail.com)
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. */
  16. #include <linux/init.h>
  17. #include <linux/kernel.h>
  18. #include <linux/module.h>
  19. #include <linux/moduleparam.h>
  20. #include <linux/slab.h>
  21. #include "dvb_frontend.h"
  22. #include "mb86a16.h"
  23. #include "mb86a16_priv.h"
  24. static unsigned int verbose = 5;
  25. module_param(verbose, int, 0644);
  26. #define ABS(x) ((x) < 0 ? (-x) : (x))
  27. struct mb86a16_state {
  28. struct i2c_adapter *i2c_adap;
  29. const struct mb86a16_config *config;
  30. struct dvb_frontend frontend;
  31. /* tuning parameters */
  32. int frequency;
  33. int srate;
  34. /* Internal stuff */
  35. int master_clk;
  36. int deci;
  37. int csel;
  38. int rsel;
  39. };
  40. #define MB86A16_ERROR 0
  41. #define MB86A16_NOTICE 1
  42. #define MB86A16_INFO 2
  43. #define MB86A16_DEBUG 3
  44. #define dprintk(x, y, z, format, arg...) do { \
  45. if (z) { \
  46. if ((x > MB86A16_ERROR) && (x > y)) \
  47. printk(KERN_ERR "%s: " format "\n", __func__, ##arg); \
  48. else if ((x > MB86A16_NOTICE) && (x > y)) \
  49. printk(KERN_NOTICE "%s: " format "\n", __func__, ##arg); \
  50. else if ((x > MB86A16_INFO) && (x > y)) \
  51. printk(KERN_INFO "%s: " format "\n", __func__, ##arg); \
  52. else if ((x > MB86A16_DEBUG) && (x > y)) \
  53. printk(KERN_DEBUG "%s: " format "\n", __func__, ##arg); \
  54. } else { \
  55. if (x > y) \
  56. printk(format, ##arg); \
  57. } \
  58. } while (0)
  59. #define TRACE_IN dprintk(verbose, MB86A16_DEBUG, 1, "-->()")
  60. #define TRACE_OUT dprintk(verbose, MB86A16_DEBUG, 1, "()-->")
  61. static int mb86a16_write(struct mb86a16_state *state, u8 reg, u8 val)
  62. {
  63. int ret;
  64. u8 buf[] = { reg, val };
  65. struct i2c_msg msg = {
  66. .addr = state->config->demod_address,
  67. .flags = 0,
  68. .buf = buf,
  69. .len = 2
  70. };
  71. dprintk(verbose, MB86A16_DEBUG, 1,
  72. "writing to [0x%02x],Reg[0x%02x],Data[0x%02x]",
  73. state->config->demod_address, buf[0], buf[1]);
  74. ret = i2c_transfer(state->i2c_adap, &msg, 1);
  75. return (ret != 1) ? -EREMOTEIO : 0;
  76. }
  77. static int mb86a16_read(struct mb86a16_state *state, u8 reg, u8 *val)
  78. {
  79. int ret;
  80. u8 b0[] = { reg };
  81. u8 b1[] = { 0 };
  82. struct i2c_msg msg[] = {
  83. {
  84. .addr = state->config->demod_address,
  85. .flags = 0,
  86. .buf = b0,
  87. .len = 1
  88. }, {
  89. .addr = state->config->demod_address,
  90. .flags = I2C_M_RD,
  91. .buf = b1,
  92. .len = 1
  93. }
  94. };
  95. ret = i2c_transfer(state->i2c_adap, msg, 2);
  96. if (ret != 2) {
  97. dprintk(verbose, MB86A16_ERROR, 1, "read error(reg=0x%02x, ret=%i)",
  98. reg, ret);
  99. if (ret < 0)
  100. return ret;
  101. return -EREMOTEIO;
  102. }
  103. *val = b1[0];
  104. return ret;
  105. }
  106. static int CNTM_set(struct mb86a16_state *state,
  107. unsigned char timint1,
  108. unsigned char timint2,
  109. unsigned char cnext)
  110. {
  111. unsigned char val;
  112. val = (timint1 << 4) | (timint2 << 2) | cnext;
  113. if (mb86a16_write(state, MB86A16_CNTMR, val) < 0)
  114. goto err;
  115. return 0;
  116. err:
  117. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  118. return -EREMOTEIO;
  119. }
  120. static int smrt_set(struct mb86a16_state *state, int rate)
  121. {
  122. int tmp ;
  123. int m ;
  124. unsigned char STOFS0, STOFS1;
  125. m = 1 << state->deci;
  126. tmp = (8192 * state->master_clk - 2 * m * rate * 8192 + state->master_clk / 2) / state->master_clk;
  127. STOFS0 = tmp & 0x0ff;
  128. STOFS1 = (tmp & 0xf00) >> 8;
  129. if (mb86a16_write(state, MB86A16_SRATE1, (state->deci << 2) |
  130. (state->csel << 1) |
  131. state->rsel) < 0)
  132. goto err;
  133. if (mb86a16_write(state, MB86A16_SRATE2, STOFS0) < 0)
  134. goto err;
  135. if (mb86a16_write(state, MB86A16_SRATE3, STOFS1) < 0)
  136. goto err;
  137. return 0;
  138. err:
  139. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  140. return -1;
  141. }
  142. static int srst(struct mb86a16_state *state)
  143. {
  144. if (mb86a16_write(state, MB86A16_RESET, 0x04) < 0)
  145. goto err;
  146. return 0;
  147. err:
  148. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  149. return -EREMOTEIO;
  150. }
  151. static int afcex_data_set(struct mb86a16_state *state,
  152. unsigned char AFCEX_L,
  153. unsigned char AFCEX_H)
  154. {
  155. if (mb86a16_write(state, MB86A16_AFCEXL, AFCEX_L) < 0)
  156. goto err;
  157. if (mb86a16_write(state, MB86A16_AFCEXH, AFCEX_H) < 0)
  158. goto err;
  159. return 0;
  160. err:
  161. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  162. return -1;
  163. }
  164. static int afcofs_data_set(struct mb86a16_state *state,
  165. unsigned char AFCEX_L,
  166. unsigned char AFCEX_H)
  167. {
  168. if (mb86a16_write(state, 0x58, AFCEX_L) < 0)
  169. goto err;
  170. if (mb86a16_write(state, 0x59, AFCEX_H) < 0)
  171. goto err;
  172. return 0;
  173. err:
  174. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  175. return -EREMOTEIO;
  176. }
  177. static int stlp_set(struct mb86a16_state *state,
  178. unsigned char STRAS,
  179. unsigned char STRBS)
  180. {
  181. if (mb86a16_write(state, MB86A16_STRFILTCOEF1, (STRBS << 3) | (STRAS)) < 0)
  182. goto err;
  183. return 0;
  184. err:
  185. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  186. return -EREMOTEIO;
  187. }
  188. static int Vi_set(struct mb86a16_state *state, unsigned char ETH, unsigned char VIA)
  189. {
  190. if (mb86a16_write(state, MB86A16_VISET2, 0x04) < 0)
  191. goto err;
  192. if (mb86a16_write(state, MB86A16_VISET3, 0xf5) < 0)
  193. goto err;
  194. return 0;
  195. err:
  196. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  197. return -EREMOTEIO;
  198. }
  199. static int initial_set(struct mb86a16_state *state)
  200. {
  201. if (stlp_set(state, 5, 7))
  202. goto err;
  203. udelay(100);
  204. if (afcex_data_set(state, 0, 0))
  205. goto err;
  206. udelay(100);
  207. if (afcofs_data_set(state, 0, 0))
  208. goto err;
  209. udelay(100);
  210. if (mb86a16_write(state, MB86A16_CRLFILTCOEF1, 0x16) < 0)
  211. goto err;
  212. if (mb86a16_write(state, 0x2f, 0x21) < 0)
  213. goto err;
  214. if (mb86a16_write(state, MB86A16_VIMAG, 0x38) < 0)
  215. goto err;
  216. if (mb86a16_write(state, MB86A16_FAGCS1, 0x00) < 0)
  217. goto err;
  218. if (mb86a16_write(state, MB86A16_FAGCS2, 0x1c) < 0)
  219. goto err;
  220. if (mb86a16_write(state, MB86A16_FAGCS3, 0x20) < 0)
  221. goto err;
  222. if (mb86a16_write(state, MB86A16_FAGCS4, 0x1e) < 0)
  223. goto err;
  224. if (mb86a16_write(state, MB86A16_FAGCS5, 0x23) < 0)
  225. goto err;
  226. if (mb86a16_write(state, 0x54, 0xff) < 0)
  227. goto err;
  228. if (mb86a16_write(state, MB86A16_TSOUT, 0x00) < 0)
  229. goto err;
  230. return 0;
  231. err:
  232. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  233. return -EREMOTEIO;
  234. }
  235. static int S01T_set(struct mb86a16_state *state,
  236. unsigned char s1t,
  237. unsigned s0t)
  238. {
  239. if (mb86a16_write(state, 0x33, (s1t << 3) | s0t) < 0)
  240. goto err;
  241. return 0;
  242. err:
  243. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  244. return -EREMOTEIO;
  245. }
  246. static int EN_set(struct mb86a16_state *state,
  247. int cren,
  248. int afcen)
  249. {
  250. unsigned char val;
  251. val = 0x7a | (cren << 7) | (afcen << 2);
  252. if (mb86a16_write(state, 0x49, val) < 0)
  253. goto err;
  254. return 0;
  255. err:
  256. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  257. return -EREMOTEIO;
  258. }
  259. static int AFCEXEN_set(struct mb86a16_state *state,
  260. int afcexen,
  261. int smrt)
  262. {
  263. unsigned char AFCA ;
  264. if (smrt > 18875)
  265. AFCA = 4;
  266. else if (smrt > 9375)
  267. AFCA = 3;
  268. else if (smrt > 2250)
  269. AFCA = 2;
  270. else
  271. AFCA = 1;
  272. if (mb86a16_write(state, 0x2a, 0x02 | (afcexen << 5) | (AFCA << 2)) < 0)
  273. goto err;
  274. return 0;
  275. err:
  276. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  277. return -EREMOTEIO;
  278. }
  279. static int DAGC_data_set(struct mb86a16_state *state,
  280. unsigned char DAGCA,
  281. unsigned char DAGCW)
  282. {
  283. if (mb86a16_write(state, 0x2d, (DAGCA << 3) | DAGCW) < 0)
  284. goto err;
  285. return 0;
  286. err:
  287. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  288. return -EREMOTEIO;
  289. }
  290. static void smrt_info_get(struct mb86a16_state *state, int rate)
  291. {
  292. if (rate >= 37501) {
  293. state->deci = 0; state->csel = 0; state->rsel = 0;
  294. } else if (rate >= 30001) {
  295. state->deci = 0; state->csel = 0; state->rsel = 1;
  296. } else if (rate >= 26251) {
  297. state->deci = 0; state->csel = 1; state->rsel = 0;
  298. } else if (rate >= 22501) {
  299. state->deci = 0; state->csel = 1; state->rsel = 1;
  300. } else if (rate >= 18751) {
  301. state->deci = 1; state->csel = 0; state->rsel = 0;
  302. } else if (rate >= 15001) {
  303. state->deci = 1; state->csel = 0; state->rsel = 1;
  304. } else if (rate >= 13126) {
  305. state->deci = 1; state->csel = 1; state->rsel = 0;
  306. } else if (rate >= 11251) {
  307. state->deci = 1; state->csel = 1; state->rsel = 1;
  308. } else if (rate >= 9376) {
  309. state->deci = 2; state->csel = 0; state->rsel = 0;
  310. } else if (rate >= 7501) {
  311. state->deci = 2; state->csel = 0; state->rsel = 1;
  312. } else if (rate >= 6563) {
  313. state->deci = 2; state->csel = 1; state->rsel = 0;
  314. } else if (rate >= 5626) {
  315. state->deci = 2; state->csel = 1; state->rsel = 1;
  316. } else if (rate >= 4688) {
  317. state->deci = 3; state->csel = 0; state->rsel = 0;
  318. } else if (rate >= 3751) {
  319. state->deci = 3; state->csel = 0; state->rsel = 1;
  320. } else if (rate >= 3282) {
  321. state->deci = 3; state->csel = 1; state->rsel = 0;
  322. } else if (rate >= 2814) {
  323. state->deci = 3; state->csel = 1; state->rsel = 1;
  324. } else if (rate >= 2344) {
  325. state->deci = 4; state->csel = 0; state->rsel = 0;
  326. } else if (rate >= 1876) {
  327. state->deci = 4; state->csel = 0; state->rsel = 1;
  328. } else if (rate >= 1641) {
  329. state->deci = 4; state->csel = 1; state->rsel = 0;
  330. } else if (rate >= 1407) {
  331. state->deci = 4; state->csel = 1; state->rsel = 1;
  332. } else if (rate >= 1172) {
  333. state->deci = 5; state->csel = 0; state->rsel = 0;
  334. } else if (rate >= 939) {
  335. state->deci = 5; state->csel = 0; state->rsel = 1;
  336. } else if (rate >= 821) {
  337. state->deci = 5; state->csel = 1; state->rsel = 0;
  338. } else {
  339. state->deci = 5; state->csel = 1; state->rsel = 1;
  340. }
  341. if (state->csel == 0)
  342. state->master_clk = 92000;
  343. else
  344. state->master_clk = 61333;
  345. }
  346. static int signal_det(struct mb86a16_state *state,
  347. int smrt,
  348. unsigned char *SIG)
  349. {
  350. int ret ;
  351. int smrtd ;
  352. int wait_sym ;
  353. u32 wait_t;
  354. unsigned char S[3] ;
  355. int i ;
  356. if (*SIG > 45) {
  357. if (CNTM_set(state, 2, 1, 2) < 0) {
  358. dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
  359. return -1;
  360. }
  361. wait_sym = 40000;
  362. } else {
  363. if (CNTM_set(state, 3, 1, 2) < 0) {
  364. dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
  365. return -1;
  366. }
  367. wait_sym = 80000;
  368. }
  369. for (i = 0; i < 3; i++) {
  370. if (i == 0)
  371. smrtd = smrt * 98 / 100;
  372. else if (i == 1)
  373. smrtd = smrt;
  374. else
  375. smrtd = smrt * 102 / 100;
  376. smrt_info_get(state, smrtd);
  377. smrt_set(state, smrtd);
  378. srst(state);
  379. wait_t = (wait_sym + 99 * smrtd / 100) / smrtd;
  380. if (wait_t == 0)
  381. wait_t = 1;
  382. msleep_interruptible(10);
  383. if (mb86a16_read(state, 0x37, &(S[i])) != 2) {
  384. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  385. return -EREMOTEIO;
  386. }
  387. }
  388. if ((S[1] > S[0] * 112 / 100) &&
  389. (S[1] > S[2] * 112 / 100)) {
  390. ret = 1;
  391. } else {
  392. ret = 0;
  393. }
  394. *SIG = S[1];
  395. if (CNTM_set(state, 0, 1, 2) < 0) {
  396. dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
  397. return -1;
  398. }
  399. return ret;
  400. }
  401. static int rf_val_set(struct mb86a16_state *state,
  402. int f,
  403. int smrt,
  404. unsigned char R)
  405. {
  406. unsigned char C, F, B;
  407. int M;
  408. unsigned char rf_val[5];
  409. int ack = -1;
  410. if (smrt > 37750)
  411. C = 1;
  412. else if (smrt > 18875)
  413. C = 2;
  414. else if (smrt > 5500)
  415. C = 3;
  416. else
  417. C = 4;
  418. if (smrt > 30500)
  419. F = 3;
  420. else if (smrt > 9375)
  421. F = 1;
  422. else if (smrt > 4625)
  423. F = 0;
  424. else
  425. F = 2;
  426. if (f < 1060)
  427. B = 0;
  428. else if (f < 1175)
  429. B = 1;
  430. else if (f < 1305)
  431. B = 2;
  432. else if (f < 1435)
  433. B = 3;
  434. else if (f < 1570)
  435. B = 4;
  436. else if (f < 1715)
  437. B = 5;
  438. else if (f < 1845)
  439. B = 6;
  440. else if (f < 1980)
  441. B = 7;
  442. else if (f < 2080)
  443. B = 8;
  444. else
  445. B = 9;
  446. M = f * (1 << R) / 2;
  447. rf_val[0] = 0x01 | (C << 3) | (F << 1);
  448. rf_val[1] = (R << 5) | ((M & 0x1f000) >> 12);
  449. rf_val[2] = (M & 0x00ff0) >> 4;
  450. rf_val[3] = ((M & 0x0000f) << 4) | B;
  451. /* Frequency Set */
  452. if (mb86a16_write(state, 0x21, rf_val[0]) < 0)
  453. ack = 0;
  454. if (mb86a16_write(state, 0x22, rf_val[1]) < 0)
  455. ack = 0;
  456. if (mb86a16_write(state, 0x23, rf_val[2]) < 0)
  457. ack = 0;
  458. if (mb86a16_write(state, 0x24, rf_val[3]) < 0)
  459. ack = 0;
  460. if (mb86a16_write(state, 0x25, 0x01) < 0)
  461. ack = 0;
  462. if (ack == 0) {
  463. dprintk(verbose, MB86A16_ERROR, 1, "RF Setup - I2C transfer error");
  464. return -EREMOTEIO;
  465. }
  466. return 0;
  467. }
  468. static int afcerr_chk(struct mb86a16_state *state)
  469. {
  470. unsigned char AFCM_L, AFCM_H ;
  471. int AFCM ;
  472. int afcm, afcerr ;
  473. if (mb86a16_read(state, 0x0e, &AFCM_L) != 2)
  474. goto err;
  475. if (mb86a16_read(state, 0x0f, &AFCM_H) != 2)
  476. goto err;
  477. AFCM = (AFCM_H << 8) + AFCM_L;
  478. if (AFCM > 2048)
  479. afcm = AFCM - 4096;
  480. else
  481. afcm = AFCM;
  482. afcerr = afcm * state->master_clk / 8192;
  483. return afcerr;
  484. err:
  485. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  486. return -EREMOTEIO;
  487. }
  488. static int dagcm_val_get(struct mb86a16_state *state)
  489. {
  490. int DAGCM;
  491. unsigned char DAGCM_H, DAGCM_L;
  492. if (mb86a16_read(state, 0x45, &DAGCM_L) != 2)
  493. goto err;
  494. if (mb86a16_read(state, 0x46, &DAGCM_H) != 2)
  495. goto err;
  496. DAGCM = (DAGCM_H << 8) + DAGCM_L;
  497. return DAGCM;
  498. err:
  499. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  500. return -EREMOTEIO;
  501. }
  502. static int mb86a16_read_status(struct dvb_frontend *fe, enum fe_status *status)
  503. {
  504. u8 stat, stat2;
  505. struct mb86a16_state *state = fe->demodulator_priv;
  506. *status = 0;
  507. if (mb86a16_read(state, MB86A16_SIG1, &stat) != 2)
  508. goto err;
  509. if (mb86a16_read(state, MB86A16_SIG2, &stat2) != 2)
  510. goto err;
  511. if ((stat > 25) && (stat2 > 25))
  512. *status |= FE_HAS_SIGNAL;
  513. if ((stat > 45) && (stat2 > 45))
  514. *status |= FE_HAS_CARRIER;
  515. if (mb86a16_read(state, MB86A16_STATUS, &stat) != 2)
  516. goto err;
  517. if (stat & 0x01)
  518. *status |= FE_HAS_SYNC;
  519. if (stat & 0x01)
  520. *status |= FE_HAS_VITERBI;
  521. if (mb86a16_read(state, MB86A16_FRAMESYNC, &stat) != 2)
  522. goto err;
  523. if ((stat & 0x0f) && (*status & FE_HAS_VITERBI))
  524. *status |= FE_HAS_LOCK;
  525. return 0;
  526. err:
  527. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  528. return -EREMOTEIO;
  529. }
  530. static int sync_chk(struct mb86a16_state *state,
  531. unsigned char *VIRM)
  532. {
  533. unsigned char val;
  534. int sync;
  535. if (mb86a16_read(state, 0x0d, &val) != 2)
  536. goto err;
  537. dprintk(verbose, MB86A16_INFO, 1, "Status = %02x,", val);
  538. sync = val & 0x01;
  539. *VIRM = (val & 0x1c) >> 2;
  540. return sync;
  541. err:
  542. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  543. return -EREMOTEIO;
  544. }
  545. static int freqerr_chk(struct mb86a16_state *state,
  546. int fTP,
  547. int smrt,
  548. int unit)
  549. {
  550. unsigned char CRM, AFCML, AFCMH;
  551. unsigned char temp1, temp2, temp3;
  552. int crm, afcm, AFCM;
  553. int crrerr, afcerr; /* kHz */
  554. int frqerr; /* MHz */
  555. int afcen, afcexen = 0;
  556. int R, M, fOSC, fOSC_OFS;
  557. if (mb86a16_read(state, 0x43, &CRM) != 2)
  558. goto err;
  559. if (CRM > 127)
  560. crm = CRM - 256;
  561. else
  562. crm = CRM;
  563. crrerr = smrt * crm / 256;
  564. if (mb86a16_read(state, 0x49, &temp1) != 2)
  565. goto err;
  566. afcen = (temp1 & 0x04) >> 2;
  567. if (afcen == 0) {
  568. if (mb86a16_read(state, 0x2a, &temp1) != 2)
  569. goto err;
  570. afcexen = (temp1 & 0x20) >> 5;
  571. }
  572. if (afcen == 1) {
  573. if (mb86a16_read(state, 0x0e, &AFCML) != 2)
  574. goto err;
  575. if (mb86a16_read(state, 0x0f, &AFCMH) != 2)
  576. goto err;
  577. } else if (afcexen == 1) {
  578. if (mb86a16_read(state, 0x2b, &AFCML) != 2)
  579. goto err;
  580. if (mb86a16_read(state, 0x2c, &AFCMH) != 2)
  581. goto err;
  582. }
  583. if ((afcen == 1) || (afcexen == 1)) {
  584. smrt_info_get(state, smrt);
  585. AFCM = ((AFCMH & 0x01) << 8) + AFCML;
  586. if (AFCM > 255)
  587. afcm = AFCM - 512;
  588. else
  589. afcm = AFCM;
  590. afcerr = afcm * state->master_clk / 8192;
  591. } else
  592. afcerr = 0;
  593. if (mb86a16_read(state, 0x22, &temp1) != 2)
  594. goto err;
  595. if (mb86a16_read(state, 0x23, &temp2) != 2)
  596. goto err;
  597. if (mb86a16_read(state, 0x24, &temp3) != 2)
  598. goto err;
  599. R = (temp1 & 0xe0) >> 5;
  600. M = ((temp1 & 0x1f) << 12) + (temp2 << 4) + (temp3 >> 4);
  601. if (R == 0)
  602. fOSC = 2 * M;
  603. else
  604. fOSC = M;
  605. fOSC_OFS = fOSC - fTP;
  606. if (unit == 0) { /* MHz */
  607. if (crrerr + afcerr + fOSC_OFS * 1000 >= 0)
  608. frqerr = (crrerr + afcerr + fOSC_OFS * 1000 + 500) / 1000;
  609. else
  610. frqerr = (crrerr + afcerr + fOSC_OFS * 1000 - 500) / 1000;
  611. } else { /* kHz */
  612. frqerr = crrerr + afcerr + fOSC_OFS * 1000;
  613. }
  614. return frqerr;
  615. err:
  616. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  617. return -EREMOTEIO;
  618. }
  619. static unsigned char vco_dev_get(struct mb86a16_state *state, int smrt)
  620. {
  621. unsigned char R;
  622. if (smrt > 9375)
  623. R = 0;
  624. else
  625. R = 1;
  626. return R;
  627. }
  628. static void swp_info_get(struct mb86a16_state *state,
  629. int fOSC_start,
  630. int smrt,
  631. int v, int R,
  632. int swp_ofs,
  633. int *fOSC,
  634. int *afcex_freq,
  635. unsigned char *AFCEX_L,
  636. unsigned char *AFCEX_H)
  637. {
  638. int AFCEX ;
  639. int crnt_swp_freq ;
  640. crnt_swp_freq = fOSC_start * 1000 + v * swp_ofs;
  641. if (R == 0)
  642. *fOSC = (crnt_swp_freq + 1000) / 2000 * 2;
  643. else
  644. *fOSC = (crnt_swp_freq + 500) / 1000;
  645. if (*fOSC >= crnt_swp_freq)
  646. *afcex_freq = *fOSC * 1000 - crnt_swp_freq;
  647. else
  648. *afcex_freq = crnt_swp_freq - *fOSC * 1000;
  649. AFCEX = *afcex_freq * 8192 / state->master_clk;
  650. *AFCEX_L = AFCEX & 0x00ff;
  651. *AFCEX_H = (AFCEX & 0x0f00) >> 8;
  652. }
  653. static int swp_freq_calcuation(struct mb86a16_state *state, int i, int v, int *V, int vmax, int vmin,
  654. int SIGMIN, int fOSC, int afcex_freq, int swp_ofs, unsigned char *SIG1)
  655. {
  656. int swp_freq ;
  657. if ((i % 2 == 1) && (v <= vmax)) {
  658. /* positive v (case 1) */
  659. if ((v - 1 == vmin) &&
  660. (*(V + 30 + v) >= 0) &&
  661. (*(V + 30 + v - 1) >= 0) &&
  662. (*(V + 30 + v - 1) > *(V + 30 + v)) &&
  663. (*(V + 30 + v - 1) > SIGMIN)) {
  664. swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
  665. *SIG1 = *(V + 30 + v - 1);
  666. } else if ((v == vmax) &&
  667. (*(V + 30 + v) >= 0) &&
  668. (*(V + 30 + v - 1) >= 0) &&
  669. (*(V + 30 + v) > *(V + 30 + v - 1)) &&
  670. (*(V + 30 + v) > SIGMIN)) {
  671. /* (case 2) */
  672. swp_freq = fOSC * 1000 + afcex_freq;
  673. *SIG1 = *(V + 30 + v);
  674. } else if ((*(V + 30 + v) > 0) &&
  675. (*(V + 30 + v - 1) > 0) &&
  676. (*(V + 30 + v - 2) > 0) &&
  677. (*(V + 30 + v - 3) > 0) &&
  678. (*(V + 30 + v - 1) > *(V + 30 + v)) &&
  679. (*(V + 30 + v - 2) > *(V + 30 + v - 3)) &&
  680. ((*(V + 30 + v - 1) > SIGMIN) ||
  681. (*(V + 30 + v - 2) > SIGMIN))) {
  682. /* (case 3) */
  683. if (*(V + 30 + v - 1) >= *(V + 30 + v - 2)) {
  684. swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
  685. *SIG1 = *(V + 30 + v - 1);
  686. } else {
  687. swp_freq = fOSC * 1000 + afcex_freq - swp_ofs * 2;
  688. *SIG1 = *(V + 30 + v - 2);
  689. }
  690. } else if ((v == vmax) &&
  691. (*(V + 30 + v) >= 0) &&
  692. (*(V + 30 + v - 1) >= 0) &&
  693. (*(V + 30 + v - 2) >= 0) &&
  694. (*(V + 30 + v) > *(V + 30 + v - 2)) &&
  695. (*(V + 30 + v - 1) > *(V + 30 + v - 2)) &&
  696. ((*(V + 30 + v) > SIGMIN) ||
  697. (*(V + 30 + v - 1) > SIGMIN))) {
  698. /* (case 4) */
  699. if (*(V + 30 + v) >= *(V + 30 + v - 1)) {
  700. swp_freq = fOSC * 1000 + afcex_freq;
  701. *SIG1 = *(V + 30 + v);
  702. } else {
  703. swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
  704. *SIG1 = *(V + 30 + v - 1);
  705. }
  706. } else {
  707. swp_freq = -1 ;
  708. }
  709. } else if ((i % 2 == 0) && (v >= vmin)) {
  710. /* Negative v (case 1) */
  711. if ((*(V + 30 + v) > 0) &&
  712. (*(V + 30 + v + 1) > 0) &&
  713. (*(V + 30 + v + 2) > 0) &&
  714. (*(V + 30 + v + 1) > *(V + 30 + v)) &&
  715. (*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
  716. (*(V + 30 + v + 1) > SIGMIN)) {
  717. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
  718. *SIG1 = *(V + 30 + v + 1);
  719. } else if ((v + 1 == vmax) &&
  720. (*(V + 30 + v) >= 0) &&
  721. (*(V + 30 + v + 1) >= 0) &&
  722. (*(V + 30 + v + 1) > *(V + 30 + v)) &&
  723. (*(V + 30 + v + 1) > SIGMIN)) {
  724. /* (case 2) */
  725. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
  726. *SIG1 = *(V + 30 + v);
  727. } else if ((v == vmin) &&
  728. (*(V + 30 + v) > 0) &&
  729. (*(V + 30 + v + 1) > 0) &&
  730. (*(V + 30 + v + 2) > 0) &&
  731. (*(V + 30 + v) > *(V + 30 + v + 1)) &&
  732. (*(V + 30 + v) > *(V + 30 + v + 2)) &&
  733. (*(V + 30 + v) > SIGMIN)) {
  734. /* (case 3) */
  735. swp_freq = fOSC * 1000 + afcex_freq;
  736. *SIG1 = *(V + 30 + v);
  737. } else if ((*(V + 30 + v) >= 0) &&
  738. (*(V + 30 + v + 1) >= 0) &&
  739. (*(V + 30 + v + 2) >= 0) &&
  740. (*(V + 30 + v + 3) >= 0) &&
  741. (*(V + 30 + v + 1) > *(V + 30 + v)) &&
  742. (*(V + 30 + v + 2) > *(V + 30 + v + 3)) &&
  743. ((*(V + 30 + v + 1) > SIGMIN) ||
  744. (*(V + 30 + v + 2) > SIGMIN))) {
  745. /* (case 4) */
  746. if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
  747. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
  748. *SIG1 = *(V + 30 + v + 1);
  749. } else {
  750. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
  751. *SIG1 = *(V + 30 + v + 2);
  752. }
  753. } else if ((*(V + 30 + v) >= 0) &&
  754. (*(V + 30 + v + 1) >= 0) &&
  755. (*(V + 30 + v + 2) >= 0) &&
  756. (*(V + 30 + v + 3) >= 0) &&
  757. (*(V + 30 + v) > *(V + 30 + v + 2)) &&
  758. (*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
  759. (*(V + 30 + v) > *(V + 30 + v + 3)) &&
  760. (*(V + 30 + v + 1) > *(V + 30 + v + 3)) &&
  761. ((*(V + 30 + v) > SIGMIN) ||
  762. (*(V + 30 + v + 1) > SIGMIN))) {
  763. /* (case 5) */
  764. if (*(V + 30 + v) >= *(V + 30 + v + 1)) {
  765. swp_freq = fOSC * 1000 + afcex_freq;
  766. *SIG1 = *(V + 30 + v);
  767. } else {
  768. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
  769. *SIG1 = *(V + 30 + v + 1);
  770. }
  771. } else if ((v + 2 == vmin) &&
  772. (*(V + 30 + v) >= 0) &&
  773. (*(V + 30 + v + 1) >= 0) &&
  774. (*(V + 30 + v + 2) >= 0) &&
  775. (*(V + 30 + v + 1) > *(V + 30 + v)) &&
  776. (*(V + 30 + v + 2) > *(V + 30 + v)) &&
  777. ((*(V + 30 + v + 1) > SIGMIN) ||
  778. (*(V + 30 + v + 2) > SIGMIN))) {
  779. /* (case 6) */
  780. if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
  781. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
  782. *SIG1 = *(V + 30 + v + 1);
  783. } else {
  784. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
  785. *SIG1 = *(V + 30 + v + 2);
  786. }
  787. } else if ((vmax == 0) && (vmin == 0) && (*(V + 30 + v) > SIGMIN)) {
  788. swp_freq = fOSC * 1000;
  789. *SIG1 = *(V + 30 + v);
  790. } else
  791. swp_freq = -1;
  792. } else
  793. swp_freq = -1;
  794. return swp_freq;
  795. }
  796. static void swp_info_get2(struct mb86a16_state *state,
  797. int smrt,
  798. int R,
  799. int swp_freq,
  800. int *afcex_freq,
  801. int *fOSC,
  802. unsigned char *AFCEX_L,
  803. unsigned char *AFCEX_H)
  804. {
  805. int AFCEX ;
  806. if (R == 0)
  807. *fOSC = (swp_freq + 1000) / 2000 * 2;
  808. else
  809. *fOSC = (swp_freq + 500) / 1000;
  810. if (*fOSC >= swp_freq)
  811. *afcex_freq = *fOSC * 1000 - swp_freq;
  812. else
  813. *afcex_freq = swp_freq - *fOSC * 1000;
  814. AFCEX = *afcex_freq * 8192 / state->master_clk;
  815. *AFCEX_L = AFCEX & 0x00ff;
  816. *AFCEX_H = (AFCEX & 0x0f00) >> 8;
  817. }
  818. static void afcex_info_get(struct mb86a16_state *state,
  819. int afcex_freq,
  820. unsigned char *AFCEX_L,
  821. unsigned char *AFCEX_H)
  822. {
  823. int AFCEX ;
  824. AFCEX = afcex_freq * 8192 / state->master_clk;
  825. *AFCEX_L = AFCEX & 0x00ff;
  826. *AFCEX_H = (AFCEX & 0x0f00) >> 8;
  827. }
  828. static int SEQ_set(struct mb86a16_state *state, unsigned char loop)
  829. {
  830. /* SLOCK0 = 0 */
  831. if (mb86a16_write(state, 0x32, 0x02 | (loop << 2)) < 0) {
  832. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  833. return -EREMOTEIO;
  834. }
  835. return 0;
  836. }
  837. static int iq_vt_set(struct mb86a16_state *state, unsigned char IQINV)
  838. {
  839. /* Viterbi Rate, IQ Settings */
  840. if (mb86a16_write(state, 0x06, 0xdf | (IQINV << 5)) < 0) {
  841. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  842. return -EREMOTEIO;
  843. }
  844. return 0;
  845. }
  846. static int FEC_srst(struct mb86a16_state *state)
  847. {
  848. if (mb86a16_write(state, MB86A16_RESET, 0x02) < 0) {
  849. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  850. return -EREMOTEIO;
  851. }
  852. return 0;
  853. }
  854. static int S2T_set(struct mb86a16_state *state, unsigned char S2T)
  855. {
  856. if (mb86a16_write(state, 0x34, 0x70 | S2T) < 0) {
  857. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  858. return -EREMOTEIO;
  859. }
  860. return 0;
  861. }
  862. static int S45T_set(struct mb86a16_state *state, unsigned char S4T, unsigned char S5T)
  863. {
  864. if (mb86a16_write(state, 0x35, 0x00 | (S5T << 4) | S4T) < 0) {
  865. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  866. return -EREMOTEIO;
  867. }
  868. return 0;
  869. }
  870. static int mb86a16_set_fe(struct mb86a16_state *state)
  871. {
  872. u8 agcval, cnmval;
  873. int i, j;
  874. int fOSC = 0;
  875. int fOSC_start = 0;
  876. int wait_t;
  877. int fcp;
  878. int swp_ofs;
  879. int V[60];
  880. u8 SIG1MIN;
  881. unsigned char CREN, AFCEN, AFCEXEN;
  882. unsigned char SIG1;
  883. unsigned char TIMINT1, TIMINT2, TIMEXT;
  884. unsigned char S0T, S1T;
  885. unsigned char S2T;
  886. /* unsigned char S2T, S3T; */
  887. unsigned char S4T, S5T;
  888. unsigned char AFCEX_L, AFCEX_H;
  889. unsigned char R;
  890. unsigned char VIRM;
  891. unsigned char ETH, VIA;
  892. unsigned char junk;
  893. int loop;
  894. int ftemp;
  895. int v, vmax, vmin;
  896. int vmax_his, vmin_his;
  897. int swp_freq, prev_swp_freq[20];
  898. int prev_freq_num;
  899. int signal_dupl;
  900. int afcex_freq;
  901. int signal;
  902. int afcerr;
  903. int temp_freq, delta_freq;
  904. int dagcm[4];
  905. int smrt_d;
  906. /* int freq_err; */
  907. int n;
  908. int ret = -1;
  909. int sync;
  910. dprintk(verbose, MB86A16_INFO, 1, "freq=%d Mhz, symbrt=%d Ksps", state->frequency, state->srate);
  911. fcp = 3000;
  912. swp_ofs = state->srate / 4;
  913. for (i = 0; i < 60; i++)
  914. V[i] = -1;
  915. for (i = 0; i < 20; i++)
  916. prev_swp_freq[i] = 0;
  917. SIG1MIN = 25;
  918. for (n = 0; ((n < 3) && (ret == -1)); n++) {
  919. SEQ_set(state, 0);
  920. iq_vt_set(state, 0);
  921. CREN = 0;
  922. AFCEN = 0;
  923. AFCEXEN = 1;
  924. TIMINT1 = 0;
  925. TIMINT2 = 1;
  926. TIMEXT = 2;
  927. S1T = 0;
  928. S0T = 0;
  929. if (initial_set(state) < 0) {
  930. dprintk(verbose, MB86A16_ERROR, 1, "initial set failed");
  931. return -1;
  932. }
  933. if (DAGC_data_set(state, 3, 2) < 0) {
  934. dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
  935. return -1;
  936. }
  937. if (EN_set(state, CREN, AFCEN) < 0) {
  938. dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
  939. return -1; /* (0, 0) */
  940. }
  941. if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
  942. dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
  943. return -1; /* (1, smrt) = (1, symbolrate) */
  944. }
  945. if (CNTM_set(state, TIMINT1, TIMINT2, TIMEXT) < 0) {
  946. dprintk(verbose, MB86A16_ERROR, 1, "CNTM set error");
  947. return -1; /* (0, 1, 2) */
  948. }
  949. if (S01T_set(state, S1T, S0T) < 0) {
  950. dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
  951. return -1; /* (0, 0) */
  952. }
  953. smrt_info_get(state, state->srate);
  954. if (smrt_set(state, state->srate) < 0) {
  955. dprintk(verbose, MB86A16_ERROR, 1, "smrt info get error");
  956. return -1;
  957. }
  958. R = vco_dev_get(state, state->srate);
  959. if (R == 1)
  960. fOSC_start = state->frequency;
  961. else if (R == 0) {
  962. if (state->frequency % 2 == 0) {
  963. fOSC_start = state->frequency;
  964. } else {
  965. fOSC_start = state->frequency + 1;
  966. if (fOSC_start > 2150)
  967. fOSC_start = state->frequency - 1;
  968. }
  969. }
  970. loop = 1;
  971. ftemp = fOSC_start * 1000;
  972. vmax = 0 ;
  973. while (loop == 1) {
  974. ftemp = ftemp + swp_ofs;
  975. vmax++;
  976. /* Upper bound */
  977. if (ftemp > 2150000) {
  978. loop = 0;
  979. vmax--;
  980. } else {
  981. if ((ftemp == 2150000) ||
  982. (ftemp - state->frequency * 1000 >= fcp + state->srate / 4))
  983. loop = 0;
  984. }
  985. }
  986. loop = 1;
  987. ftemp = fOSC_start * 1000;
  988. vmin = 0 ;
  989. while (loop == 1) {
  990. ftemp = ftemp - swp_ofs;
  991. vmin--;
  992. /* Lower bound */
  993. if (ftemp < 950000) {
  994. loop = 0;
  995. vmin++;
  996. } else {
  997. if ((ftemp == 950000) ||
  998. (state->frequency * 1000 - ftemp >= fcp + state->srate / 4))
  999. loop = 0;
  1000. }
  1001. }
  1002. wait_t = (8000 + state->srate / 2) / state->srate;
  1003. if (wait_t == 0)
  1004. wait_t = 1;
  1005. i = 0;
  1006. j = 0;
  1007. prev_freq_num = 0;
  1008. loop = 1;
  1009. signal = 0;
  1010. vmax_his = 0;
  1011. vmin_his = 0;
  1012. v = 0;
  1013. while (loop == 1) {
  1014. swp_info_get(state, fOSC_start, state->srate,
  1015. v, R, swp_ofs, &fOSC,
  1016. &afcex_freq, &AFCEX_L, &AFCEX_H);
  1017. udelay(100);
  1018. if (rf_val_set(state, fOSC, state->srate, R) < 0) {
  1019. dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
  1020. return -1;
  1021. }
  1022. udelay(100);
  1023. if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1024. dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
  1025. return -1;
  1026. }
  1027. if (srst(state) < 0) {
  1028. dprintk(verbose, MB86A16_ERROR, 1, "srst error");
  1029. return -1;
  1030. }
  1031. msleep_interruptible(wait_t);
  1032. if (mb86a16_read(state, 0x37, &SIG1) != 2) {
  1033. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1034. return -1;
  1035. }
  1036. V[30 + v] = SIG1 ;
  1037. swp_freq = swp_freq_calcuation(state, i, v, V, vmax, vmin,
  1038. SIG1MIN, fOSC, afcex_freq,
  1039. swp_ofs, &SIG1); /* changed */
  1040. signal_dupl = 0;
  1041. for (j = 0; j < prev_freq_num; j++) {
  1042. if ((ABS(prev_swp_freq[j] - swp_freq)) < (swp_ofs * 3 / 2)) {
  1043. signal_dupl = 1;
  1044. dprintk(verbose, MB86A16_INFO, 1, "Probably Duplicate Signal, j = %d", j);
  1045. }
  1046. }
  1047. if ((signal_dupl == 0) && (swp_freq > 0) && (ABS(swp_freq - state->frequency * 1000) < fcp + state->srate / 6)) {
  1048. dprintk(verbose, MB86A16_DEBUG, 1, "------ Signal detect ------ [swp_freq=[%07d, srate=%05d]]", swp_freq, state->srate);
  1049. prev_swp_freq[prev_freq_num] = swp_freq;
  1050. prev_freq_num++;
  1051. swp_info_get2(state, state->srate, R, swp_freq,
  1052. &afcex_freq, &fOSC,
  1053. &AFCEX_L, &AFCEX_H);
  1054. if (rf_val_set(state, fOSC, state->srate, R) < 0) {
  1055. dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
  1056. return -1;
  1057. }
  1058. if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1059. dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
  1060. return -1;
  1061. }
  1062. signal = signal_det(state, state->srate, &SIG1);
  1063. if (signal == 1) {
  1064. dprintk(verbose, MB86A16_ERROR, 1, "***** Signal Found *****");
  1065. loop = 0;
  1066. } else {
  1067. dprintk(verbose, MB86A16_ERROR, 1, "!!!!! No signal !!!!!, try again...");
  1068. smrt_info_get(state, state->srate);
  1069. if (smrt_set(state, state->srate) < 0) {
  1070. dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
  1071. return -1;
  1072. }
  1073. }
  1074. }
  1075. if (v > vmax)
  1076. vmax_his = 1 ;
  1077. if (v < vmin)
  1078. vmin_his = 1 ;
  1079. i++;
  1080. if ((i % 2 == 1) && (vmax_his == 1))
  1081. i++;
  1082. if ((i % 2 == 0) && (vmin_his == 1))
  1083. i++;
  1084. if (i % 2 == 1)
  1085. v = (i + 1) / 2;
  1086. else
  1087. v = -i / 2;
  1088. if ((vmax_his == 1) && (vmin_his == 1))
  1089. loop = 0 ;
  1090. }
  1091. if (signal == 1) {
  1092. dprintk(verbose, MB86A16_INFO, 1, " Start Freq Error Check");
  1093. S1T = 7 ;
  1094. S0T = 1 ;
  1095. CREN = 0 ;
  1096. AFCEN = 1 ;
  1097. AFCEXEN = 0 ;
  1098. if (S01T_set(state, S1T, S0T) < 0) {
  1099. dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
  1100. return -1;
  1101. }
  1102. smrt_info_get(state, state->srate);
  1103. if (smrt_set(state, state->srate) < 0) {
  1104. dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
  1105. return -1;
  1106. }
  1107. if (EN_set(state, CREN, AFCEN) < 0) {
  1108. dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
  1109. return -1;
  1110. }
  1111. if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
  1112. dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
  1113. return -1;
  1114. }
  1115. afcex_info_get(state, afcex_freq, &AFCEX_L, &AFCEX_H);
  1116. if (afcofs_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1117. dprintk(verbose, MB86A16_ERROR, 1, "AFCOFS data set error");
  1118. return -1;
  1119. }
  1120. if (srst(state) < 0) {
  1121. dprintk(verbose, MB86A16_ERROR, 1, "srst error");
  1122. return -1;
  1123. }
  1124. /* delay 4~200 */
  1125. wait_t = 200000 / state->master_clk + 200000 / state->srate;
  1126. msleep(wait_t);
  1127. afcerr = afcerr_chk(state);
  1128. if (afcerr == -1)
  1129. return -1;
  1130. swp_freq = fOSC * 1000 + afcerr ;
  1131. AFCEXEN = 1 ;
  1132. if (state->srate >= 1500)
  1133. smrt_d = state->srate / 3;
  1134. else
  1135. smrt_d = state->srate / 2;
  1136. smrt_info_get(state, smrt_d);
  1137. if (smrt_set(state, smrt_d) < 0) {
  1138. dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
  1139. return -1;
  1140. }
  1141. if (AFCEXEN_set(state, AFCEXEN, smrt_d) < 0) {
  1142. dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
  1143. return -1;
  1144. }
  1145. R = vco_dev_get(state, smrt_d);
  1146. if (DAGC_data_set(state, 2, 0) < 0) {
  1147. dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
  1148. return -1;
  1149. }
  1150. for (i = 0; i < 3; i++) {
  1151. temp_freq = swp_freq + (i - 1) * state->srate / 8;
  1152. swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
  1153. if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
  1154. dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
  1155. return -1;
  1156. }
  1157. if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1158. dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
  1159. return -1;
  1160. }
  1161. wait_t = 200000 / state->master_clk + 40000 / smrt_d;
  1162. msleep(wait_t);
  1163. dagcm[i] = dagcm_val_get(state);
  1164. }
  1165. if ((dagcm[0] > dagcm[1]) &&
  1166. (dagcm[0] > dagcm[2]) &&
  1167. (dagcm[0] - dagcm[1] > 2 * (dagcm[2] - dagcm[1]))) {
  1168. temp_freq = swp_freq - 2 * state->srate / 8;
  1169. swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
  1170. if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
  1171. dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
  1172. return -1;
  1173. }
  1174. if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1175. dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
  1176. return -1;
  1177. }
  1178. wait_t = 200000 / state->master_clk + 40000 / smrt_d;
  1179. msleep(wait_t);
  1180. dagcm[3] = dagcm_val_get(state);
  1181. if (dagcm[3] > dagcm[1])
  1182. delta_freq = (dagcm[2] - dagcm[0] + dagcm[1] - dagcm[3]) * state->srate / 300;
  1183. else
  1184. delta_freq = 0;
  1185. } else if ((dagcm[2] > dagcm[1]) &&
  1186. (dagcm[2] > dagcm[0]) &&
  1187. (dagcm[2] - dagcm[1] > 2 * (dagcm[0] - dagcm[1]))) {
  1188. temp_freq = swp_freq + 2 * state->srate / 8;
  1189. swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
  1190. if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
  1191. dprintk(verbose, MB86A16_ERROR, 1, "rf val set");
  1192. return -1;
  1193. }
  1194. if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1195. dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
  1196. return -1;
  1197. }
  1198. wait_t = 200000 / state->master_clk + 40000 / smrt_d;
  1199. msleep(wait_t);
  1200. dagcm[3] = dagcm_val_get(state);
  1201. if (dagcm[3] > dagcm[1])
  1202. delta_freq = (dagcm[2] - dagcm[0] + dagcm[3] - dagcm[1]) * state->srate / 300;
  1203. else
  1204. delta_freq = 0 ;
  1205. } else {
  1206. delta_freq = 0 ;
  1207. }
  1208. dprintk(verbose, MB86A16_INFO, 1, "SWEEP Frequency = %d", swp_freq);
  1209. swp_freq += delta_freq;
  1210. dprintk(verbose, MB86A16_INFO, 1, "Adjusting .., DELTA Freq = %d, SWEEP Freq=%d", delta_freq, swp_freq);
  1211. if (ABS(state->frequency * 1000 - swp_freq) > 3800) {
  1212. dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL !");
  1213. } else {
  1214. S1T = 0;
  1215. S0T = 3;
  1216. CREN = 1;
  1217. AFCEN = 0;
  1218. AFCEXEN = 1;
  1219. if (S01T_set(state, S1T, S0T) < 0) {
  1220. dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
  1221. return -1;
  1222. }
  1223. if (DAGC_data_set(state, 0, 0) < 0) {
  1224. dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
  1225. return -1;
  1226. }
  1227. R = vco_dev_get(state, state->srate);
  1228. smrt_info_get(state, state->srate);
  1229. if (smrt_set(state, state->srate) < 0) {
  1230. dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
  1231. return -1;
  1232. }
  1233. if (EN_set(state, CREN, AFCEN) < 0) {
  1234. dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
  1235. return -1;
  1236. }
  1237. if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
  1238. dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
  1239. return -1;
  1240. }
  1241. swp_info_get2(state, state->srate, R, swp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
  1242. if (rf_val_set(state, fOSC, state->srate, R) < 0) {
  1243. dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
  1244. return -1;
  1245. }
  1246. if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1247. dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
  1248. return -1;
  1249. }
  1250. if (srst(state) < 0) {
  1251. dprintk(verbose, MB86A16_ERROR, 1, "srst error");
  1252. return -1;
  1253. }
  1254. wait_t = 7 + (10000 + state->srate / 2) / state->srate;
  1255. if (wait_t == 0)
  1256. wait_t = 1;
  1257. msleep_interruptible(wait_t);
  1258. if (mb86a16_read(state, 0x37, &SIG1) != 2) {
  1259. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1260. return -EREMOTEIO;
  1261. }
  1262. if (SIG1 > 110) {
  1263. S2T = 4; S4T = 1; S5T = 6; ETH = 4; VIA = 6;
  1264. wait_t = 7 + (917504 + state->srate / 2) / state->srate;
  1265. } else if (SIG1 > 105) {
  1266. S2T = 4; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
  1267. wait_t = 7 + (1048576 + state->srate / 2) / state->srate;
  1268. } else if (SIG1 > 85) {
  1269. S2T = 5; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
  1270. wait_t = 7 + (1310720 + state->srate / 2) / state->srate;
  1271. } else if (SIG1 > 65) {
  1272. S2T = 6; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
  1273. wait_t = 7 + (1572864 + state->srate / 2) / state->srate;
  1274. } else {
  1275. S2T = 7; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
  1276. wait_t = 7 + (2097152 + state->srate / 2) / state->srate;
  1277. }
  1278. wait_t *= 2; /* FOS */
  1279. S2T_set(state, S2T);
  1280. S45T_set(state, S4T, S5T);
  1281. Vi_set(state, ETH, VIA);
  1282. srst(state);
  1283. msleep_interruptible(wait_t);
  1284. sync = sync_chk(state, &VIRM);
  1285. dprintk(verbose, MB86A16_INFO, 1, "-------- Viterbi=[%d] SYNC=[%d] ---------", VIRM, sync);
  1286. if (VIRM) {
  1287. if (VIRM == 4) {
  1288. /* 5/6 */
  1289. if (SIG1 > 110)
  1290. wait_t = (786432 + state->srate / 2) / state->srate;
  1291. else
  1292. wait_t = (1572864 + state->srate / 2) / state->srate;
  1293. if (state->srate < 5000)
  1294. /* FIXME ! , should be a long wait ! */
  1295. msleep_interruptible(wait_t);
  1296. else
  1297. msleep_interruptible(wait_t);
  1298. if (sync_chk(state, &junk) == 0) {
  1299. iq_vt_set(state, 1);
  1300. FEC_srst(state);
  1301. }
  1302. }
  1303. /* 1/2, 2/3, 3/4, 7/8 */
  1304. if (SIG1 > 110)
  1305. wait_t = (786432 + state->srate / 2) / state->srate;
  1306. else
  1307. wait_t = (1572864 + state->srate / 2) / state->srate;
  1308. msleep_interruptible(wait_t);
  1309. SEQ_set(state, 1);
  1310. } else {
  1311. dprintk(verbose, MB86A16_INFO, 1, "NO -- SYNC");
  1312. SEQ_set(state, 1);
  1313. ret = -1;
  1314. }
  1315. }
  1316. } else {
  1317. dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL");
  1318. ret = -1;
  1319. }
  1320. sync = sync_chk(state, &junk);
  1321. if (sync) {
  1322. dprintk(verbose, MB86A16_INFO, 1, "******* SYNC *******");
  1323. freqerr_chk(state, state->frequency, state->srate, 1);
  1324. ret = 0;
  1325. break;
  1326. }
  1327. }
  1328. mb86a16_read(state, 0x15, &agcval);
  1329. mb86a16_read(state, 0x26, &cnmval);
  1330. dprintk(verbose, MB86A16_INFO, 1, "AGC = %02x CNM = %02x", agcval, cnmval);
  1331. return ret;
  1332. }
  1333. static int mb86a16_send_diseqc_msg(struct dvb_frontend *fe,
  1334. struct dvb_diseqc_master_cmd *cmd)
  1335. {
  1336. struct mb86a16_state *state = fe->demodulator_priv;
  1337. int i;
  1338. u8 regs;
  1339. if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
  1340. goto err;
  1341. if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
  1342. goto err;
  1343. if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
  1344. goto err;
  1345. regs = 0x18;
  1346. if (cmd->msg_len > 5 || cmd->msg_len < 4)
  1347. return -EINVAL;
  1348. for (i = 0; i < cmd->msg_len; i++) {
  1349. if (mb86a16_write(state, regs, cmd->msg[i]) < 0)
  1350. goto err;
  1351. regs++;
  1352. }
  1353. i += 0x90;
  1354. msleep_interruptible(10);
  1355. if (mb86a16_write(state, MB86A16_DCC1, i) < 0)
  1356. goto err;
  1357. if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
  1358. goto err;
  1359. return 0;
  1360. err:
  1361. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1362. return -EREMOTEIO;
  1363. }
  1364. static int mb86a16_send_diseqc_burst(struct dvb_frontend *fe,
  1365. enum fe_sec_mini_cmd burst)
  1366. {
  1367. struct mb86a16_state *state = fe->demodulator_priv;
  1368. switch (burst) {
  1369. case SEC_MINI_A:
  1370. if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
  1371. MB86A16_DCC1_TBEN |
  1372. MB86A16_DCC1_TBO) < 0)
  1373. goto err;
  1374. if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
  1375. goto err;
  1376. break;
  1377. case SEC_MINI_B:
  1378. if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
  1379. MB86A16_DCC1_TBEN) < 0)
  1380. goto err;
  1381. if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
  1382. goto err;
  1383. break;
  1384. }
  1385. return 0;
  1386. err:
  1387. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1388. return -EREMOTEIO;
  1389. }
  1390. static int mb86a16_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
  1391. {
  1392. struct mb86a16_state *state = fe->demodulator_priv;
  1393. switch (tone) {
  1394. case SEC_TONE_ON:
  1395. if (mb86a16_write(state, MB86A16_TONEOUT2, 0x00) < 0)
  1396. goto err;
  1397. if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
  1398. MB86A16_DCC1_CTOE) < 0)
  1399. goto err;
  1400. if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
  1401. goto err;
  1402. break;
  1403. case SEC_TONE_OFF:
  1404. if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
  1405. goto err;
  1406. if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
  1407. goto err;
  1408. if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
  1409. goto err;
  1410. break;
  1411. default:
  1412. return -EINVAL;
  1413. }
  1414. return 0;
  1415. err:
  1416. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1417. return -EREMOTEIO;
  1418. }
  1419. static enum dvbfe_search mb86a16_search(struct dvb_frontend *fe)
  1420. {
  1421. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  1422. struct mb86a16_state *state = fe->demodulator_priv;
  1423. state->frequency = p->frequency / 1000;
  1424. state->srate = p->symbol_rate / 1000;
  1425. if (!mb86a16_set_fe(state)) {
  1426. dprintk(verbose, MB86A16_ERROR, 1, "Successfully acquired LOCK");
  1427. return DVBFE_ALGO_SEARCH_SUCCESS;
  1428. }
  1429. dprintk(verbose, MB86A16_ERROR, 1, "Lock acquisition failed!");
  1430. return DVBFE_ALGO_SEARCH_FAILED;
  1431. }
  1432. static void mb86a16_release(struct dvb_frontend *fe)
  1433. {
  1434. struct mb86a16_state *state = fe->demodulator_priv;
  1435. kfree(state);
  1436. }
  1437. static int mb86a16_init(struct dvb_frontend *fe)
  1438. {
  1439. return 0;
  1440. }
  1441. static int mb86a16_sleep(struct dvb_frontend *fe)
  1442. {
  1443. return 0;
  1444. }
  1445. static int mb86a16_read_ber(struct dvb_frontend *fe, u32 *ber)
  1446. {
  1447. u8 ber_mon, ber_tab, ber_lsb, ber_mid, ber_msb, ber_tim, ber_rst;
  1448. u32 timer;
  1449. struct mb86a16_state *state = fe->demodulator_priv;
  1450. *ber = 0;
  1451. if (mb86a16_read(state, MB86A16_BERMON, &ber_mon) != 2)
  1452. goto err;
  1453. if (mb86a16_read(state, MB86A16_BERTAB, &ber_tab) != 2)
  1454. goto err;
  1455. if (mb86a16_read(state, MB86A16_BERLSB, &ber_lsb) != 2)
  1456. goto err;
  1457. if (mb86a16_read(state, MB86A16_BERMID, &ber_mid) != 2)
  1458. goto err;
  1459. if (mb86a16_read(state, MB86A16_BERMSB, &ber_msb) != 2)
  1460. goto err;
  1461. /* BER monitor invalid when BER_EN = 0 */
  1462. if (ber_mon & 0x04) {
  1463. /* coarse, fast calculation */
  1464. *ber = ber_tab & 0x1f;
  1465. dprintk(verbose, MB86A16_DEBUG, 1, "BER coarse=[0x%02x]", *ber);
  1466. if (ber_mon & 0x01) {
  1467. /*
  1468. * BER_SEL = 1, The monitored BER is the estimated
  1469. * value with a Reed-Solomon decoder error amount at
  1470. * the deinterleaver output.
  1471. * monitored BER is expressed as a 20 bit output in total
  1472. */
  1473. ber_rst = ber_mon >> 3;
  1474. *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb;
  1475. if (ber_rst == 0)
  1476. timer = 12500000;
  1477. if (ber_rst == 1)
  1478. timer = 25000000;
  1479. if (ber_rst == 2)
  1480. timer = 50000000;
  1481. if (ber_rst == 3)
  1482. timer = 100000000;
  1483. *ber /= timer;
  1484. dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber);
  1485. } else {
  1486. /*
  1487. * BER_SEL = 0, The monitored BER is the estimated
  1488. * value with a Viterbi decoder error amount at the
  1489. * QPSK demodulator output.
  1490. * monitored BER is expressed as a 24 bit output in total
  1491. */
  1492. ber_tim = ber_mon >> 1;
  1493. *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb;
  1494. if (ber_tim == 0)
  1495. timer = 16;
  1496. if (ber_tim == 1)
  1497. timer = 24;
  1498. *ber /= 2 ^ timer;
  1499. dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber);
  1500. }
  1501. }
  1502. return 0;
  1503. err:
  1504. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1505. return -EREMOTEIO;
  1506. }
  1507. static int mb86a16_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
  1508. {
  1509. u8 agcm = 0;
  1510. struct mb86a16_state *state = fe->demodulator_priv;
  1511. *strength = 0;
  1512. if (mb86a16_read(state, MB86A16_AGCM, &agcm) != 2) {
  1513. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1514. return -EREMOTEIO;
  1515. }
  1516. *strength = ((0xff - agcm) * 100) / 256;
  1517. dprintk(verbose, MB86A16_DEBUG, 1, "Signal strength=[%d %%]", (u8) *strength);
  1518. *strength = (0xffff - 0xff) + agcm;
  1519. return 0;
  1520. }
  1521. struct cnr {
  1522. u8 cn_reg;
  1523. u8 cn_val;
  1524. };
  1525. static const struct cnr cnr_tab[] = {
  1526. { 35, 2 },
  1527. { 40, 3 },
  1528. { 50, 4 },
  1529. { 60, 5 },
  1530. { 70, 6 },
  1531. { 80, 7 },
  1532. { 92, 8 },
  1533. { 103, 9 },
  1534. { 115, 10 },
  1535. { 138, 12 },
  1536. { 162, 15 },
  1537. { 180, 18 },
  1538. { 185, 19 },
  1539. { 189, 20 },
  1540. { 195, 22 },
  1541. { 199, 24 },
  1542. { 201, 25 },
  1543. { 202, 26 },
  1544. { 203, 27 },
  1545. { 205, 28 },
  1546. { 208, 30 }
  1547. };
  1548. static int mb86a16_read_snr(struct dvb_frontend *fe, u16 *snr)
  1549. {
  1550. struct mb86a16_state *state = fe->demodulator_priv;
  1551. int i = 0;
  1552. int low_tide = 2, high_tide = 30, q_level;
  1553. u8 cn;
  1554. *snr = 0;
  1555. if (mb86a16_read(state, 0x26, &cn) != 2) {
  1556. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1557. return -EREMOTEIO;
  1558. }
  1559. for (i = 0; i < ARRAY_SIZE(cnr_tab); i++) {
  1560. if (cn < cnr_tab[i].cn_reg) {
  1561. *snr = cnr_tab[i].cn_val;
  1562. break;
  1563. }
  1564. }
  1565. q_level = (*snr * 100) / (high_tide - low_tide);
  1566. dprintk(verbose, MB86A16_ERROR, 1, "SNR (Quality) = [%d dB], Level=%d %%", *snr, q_level);
  1567. *snr = (0xffff - 0xff) + *snr;
  1568. return 0;
  1569. }
  1570. static int mb86a16_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
  1571. {
  1572. u8 dist;
  1573. struct mb86a16_state *state = fe->demodulator_priv;
  1574. if (mb86a16_read(state, MB86A16_DISTMON, &dist) != 2) {
  1575. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1576. return -EREMOTEIO;
  1577. }
  1578. *ucblocks = dist;
  1579. return 0;
  1580. }
  1581. static enum dvbfe_algo mb86a16_frontend_algo(struct dvb_frontend *fe)
  1582. {
  1583. return DVBFE_ALGO_CUSTOM;
  1584. }
  1585. static struct dvb_frontend_ops mb86a16_ops = {
  1586. .delsys = { SYS_DVBS },
  1587. .info = {
  1588. .name = "Fujitsu MB86A16 DVB-S",
  1589. .frequency_min = 950000,
  1590. .frequency_max = 2150000,
  1591. .frequency_stepsize = 3000,
  1592. .frequency_tolerance = 0,
  1593. .symbol_rate_min = 1000000,
  1594. .symbol_rate_max = 45000000,
  1595. .symbol_rate_tolerance = 500,
  1596. .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
  1597. FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
  1598. FE_CAN_FEC_7_8 | FE_CAN_QPSK |
  1599. FE_CAN_FEC_AUTO
  1600. },
  1601. .release = mb86a16_release,
  1602. .get_frontend_algo = mb86a16_frontend_algo,
  1603. .search = mb86a16_search,
  1604. .init = mb86a16_init,
  1605. .sleep = mb86a16_sleep,
  1606. .read_status = mb86a16_read_status,
  1607. .read_ber = mb86a16_read_ber,
  1608. .read_signal_strength = mb86a16_read_signal_strength,
  1609. .read_snr = mb86a16_read_snr,
  1610. .read_ucblocks = mb86a16_read_ucblocks,
  1611. .diseqc_send_master_cmd = mb86a16_send_diseqc_msg,
  1612. .diseqc_send_burst = mb86a16_send_diseqc_burst,
  1613. .set_tone = mb86a16_set_tone,
  1614. };
  1615. struct dvb_frontend *mb86a16_attach(const struct mb86a16_config *config,
  1616. struct i2c_adapter *i2c_adap)
  1617. {
  1618. u8 dev_id = 0;
  1619. struct mb86a16_state *state = NULL;
  1620. state = kmalloc(sizeof(struct mb86a16_state), GFP_KERNEL);
  1621. if (state == NULL)
  1622. goto error;
  1623. state->config = config;
  1624. state->i2c_adap = i2c_adap;
  1625. mb86a16_read(state, 0x7f, &dev_id);
  1626. if (dev_id != 0xfe)
  1627. goto error;
  1628. memcpy(&state->frontend.ops, &mb86a16_ops, sizeof(struct dvb_frontend_ops));
  1629. state->frontend.demodulator_priv = state;
  1630. state->frontend.ops.set_voltage = state->config->set_voltage;
  1631. return &state->frontend;
  1632. error:
  1633. kfree(state);
  1634. return NULL;
  1635. }
  1636. EXPORT_SYMBOL(mb86a16_attach);
  1637. MODULE_LICENSE("GPL");
  1638. MODULE_AUTHOR("Manu Abraham");