stv0367_regs.h 96 KB

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  1. /*
  2. * stv0367_regs.h
  3. *
  4. * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
  5. *
  6. * Copyright (C) ST Microelectronics.
  7. * Copyright (C) 2010,2011 NetUP Inc.
  8. * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. *
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24. */
  25. #ifndef STV0367_REGS_H
  26. #define STV0367_REGS_H
  27. /* ID */
  28. #define R367TER_ID 0xf000
  29. #define F367TER_IDENTIFICATIONREG 0xf00000ff
  30. /* I2CRPT */
  31. #define R367TER_I2CRPT 0xf001
  32. #define F367TER_I2CT_ON 0xf0010080
  33. #define F367TER_ENARPT_LEVEL 0xf0010070
  34. #define F367TER_SCLT_DELAY 0xf0010008
  35. #define F367TER_SCLT_NOD 0xf0010004
  36. #define F367TER_STOP_ENABLE 0xf0010002
  37. #define F367TER_SDAT_NOD 0xf0010001
  38. /* TOPCTRL */
  39. #define R367TER_TOPCTRL 0xf002
  40. #define F367TER_STDBY 0xf0020080
  41. #define F367TER_STDBY_FEC 0xf0020040
  42. #define F367TER_STDBY_CORE 0xf0020020
  43. #define F367TER_QAM_COFDM 0xf0020010
  44. #define F367TER_TS_DIS 0xf0020008
  45. #define F367TER_DIR_CLK_216 0xf0020004
  46. #define F367TER_TUNER_BB 0xf0020002
  47. #define F367TER_DVBT_H 0xf0020001
  48. /* IOCFG0 */
  49. #define R367TER_IOCFG0 0xf003
  50. #define F367TER_OP0_SD 0xf0030080
  51. #define F367TER_OP0_VAL 0xf0030040
  52. #define F367TER_OP0_OD 0xf0030020
  53. #define F367TER_OP0_INV 0xf0030010
  54. #define F367TER_OP0_DACVALUE_HI 0xf003000f
  55. /* DAc0R */
  56. #define R367TER_DAC0R 0xf004
  57. #define F367TER_OP0_DACVALUE_LO 0xf00400ff
  58. /* IOCFG1 */
  59. #define R367TER_IOCFG1 0xf005
  60. #define F367TER_IP0 0xf0050040
  61. #define F367TER_OP1_OD 0xf0050020
  62. #define F367TER_OP1_INV 0xf0050010
  63. #define F367TER_OP1_DACVALUE_HI 0xf005000f
  64. /* DAC1R */
  65. #define R367TER_DAC1R 0xf006
  66. #define F367TER_OP1_DACVALUE_LO 0xf00600ff
  67. /* IOCFG2 */
  68. #define R367TER_IOCFG2 0xf007
  69. #define F367TER_OP2_LOCK_CONF 0xf00700e0
  70. #define F367TER_OP2_OD 0xf0070010
  71. #define F367TER_OP2_VAL 0xf0070008
  72. #define F367TER_OP1_LOCK_CONF 0xf0070007
  73. /* SDFR */
  74. #define R367TER_SDFR 0xf008
  75. #define F367TER_OP0_FREQ 0xf00800f0
  76. #define F367TER_OP1_FREQ 0xf008000f
  77. /* STATUS */
  78. #define R367TER_STATUS 0xf009
  79. #define F367TER_TPS_LOCK 0xf0090080
  80. #define F367TER_SYR_LOCK 0xf0090040
  81. #define F367TER_AGC_LOCK 0xf0090020
  82. #define F367TER_PRF 0xf0090010
  83. #define F367TER_LK 0xf0090008
  84. #define F367TER_PR 0xf0090007
  85. /* AUX_CLK */
  86. #define R367TER_AUX_CLK 0xf00a
  87. #define F367TER_AUXFEC_CTL 0xf00a00c0
  88. #define F367TER_DIS_CKX4 0xf00a0020
  89. #define F367TER_CKSEL 0xf00a0018
  90. #define F367TER_CKDIV_PROG 0xf00a0006
  91. #define F367TER_AUXCLK_ENA 0xf00a0001
  92. /* FREESYS1 */
  93. #define R367TER_FREESYS1 0xf00b
  94. #define F367TER_FREE_SYS1 0xf00b00ff
  95. /* FREESYS2 */
  96. #define R367TER_FREESYS2 0xf00c
  97. #define F367TER_FREE_SYS2 0xf00c00ff
  98. /* FREESYS3 */
  99. #define R367TER_FREESYS3 0xf00d
  100. #define F367TER_FREE_SYS3 0xf00d00ff
  101. /* GPIO_CFG */
  102. #define R367TER_GPIO_CFG 0xf00e
  103. #define F367TER_GPIO7_NOD 0xf00e0080
  104. #define F367TER_GPIO7_CFG 0xf00e0040
  105. #define F367TER_GPIO6_NOD 0xf00e0020
  106. #define F367TER_GPIO6_CFG 0xf00e0010
  107. #define F367TER_GPIO5_NOD 0xf00e0008
  108. #define F367TER_GPIO5_CFG 0xf00e0004
  109. #define F367TER_GPIO4_NOD 0xf00e0002
  110. #define F367TER_GPIO4_CFG 0xf00e0001
  111. /* GPIO_CMD */
  112. #define R367TER_GPIO_CMD 0xf00f
  113. #define F367TER_GPIO7_VAL 0xf00f0008
  114. #define F367TER_GPIO6_VAL 0xf00f0004
  115. #define F367TER_GPIO5_VAL 0xf00f0002
  116. #define F367TER_GPIO4_VAL 0xf00f0001
  117. /* AGC2MAX */
  118. #define R367TER_AGC2MAX 0xf010
  119. #define F367TER_AGC2_MAX 0xf01000ff
  120. /* AGC2MIN */
  121. #define R367TER_AGC2MIN 0xf011
  122. #define F367TER_AGC2_MIN 0xf01100ff
  123. /* AGC1MAX */
  124. #define R367TER_AGC1MAX 0xf012
  125. #define F367TER_AGC1_MAX 0xf01200ff
  126. /* AGC1MIN */
  127. #define R367TER_AGC1MIN 0xf013
  128. #define F367TER_AGC1_MIN 0xf01300ff
  129. /* AGCR */
  130. #define R367TER_AGCR 0xf014
  131. #define F367TER_RATIO_A 0xf01400e0
  132. #define F367TER_RATIO_B 0xf0140018
  133. #define F367TER_RATIO_C 0xf0140007
  134. /* AGC2TH */
  135. #define R367TER_AGC2TH 0xf015
  136. #define F367TER_AGC2_THRES 0xf01500ff
  137. /* AGC12c */
  138. #define R367TER_AGC12C 0xf016
  139. #define F367TER_AGC1_IV 0xf0160080
  140. #define F367TER_AGC1_OD 0xf0160040
  141. #define F367TER_AGC1_LOAD 0xf0160020
  142. #define F367TER_AGC2_IV 0xf0160010
  143. #define F367TER_AGC2_OD 0xf0160008
  144. #define F367TER_AGC2_LOAD 0xf0160004
  145. #define F367TER_AGC12_MODE 0xf0160003
  146. /* AGCCTRL1 */
  147. #define R367TER_AGCCTRL1 0xf017
  148. #define F367TER_DAGC_ON 0xf0170080
  149. #define F367TER_INVERT_AGC12 0xf0170040
  150. #define F367TER_AGC1_MODE 0xf0170008
  151. #define F367TER_AGC2_MODE 0xf0170007
  152. /* AGCCTRL2 */
  153. #define R367TER_AGCCTRL2 0xf018
  154. #define F367TER_FRZ2_CTRL 0xf0180060
  155. #define F367TER_FRZ1_CTRL 0xf0180018
  156. #define F367TER_TIME_CST 0xf0180007
  157. /* AGC1VAL1 */
  158. #define R367TER_AGC1VAL1 0xf019
  159. #define F367TER_AGC1_VAL_LO 0xf01900ff
  160. /* AGC1VAL2 */
  161. #define R367TER_AGC1VAL2 0xf01a
  162. #define F367TER_AGC1_VAL_HI 0xf01a000f
  163. /* AGC2VAL1 */
  164. #define R367TER_AGC2VAL1 0xf01b
  165. #define F367TER_AGC2_VAL_LO 0xf01b00ff
  166. /* AGC2VAL2 */
  167. #define R367TER_AGC2VAL2 0xf01c
  168. #define F367TER_AGC2_VAL_HI 0xf01c000f
  169. /* AGC2PGA */
  170. #define R367TER_AGC2PGA 0xf01d
  171. #define F367TER_AGC2_PGA 0xf01d00ff
  172. /* OVF_RATE1 */
  173. #define R367TER_OVF_RATE1 0xf01e
  174. #define F367TER_OVF_RATE_HI 0xf01e000f
  175. /* OVF_RATE2 */
  176. #define R367TER_OVF_RATE2 0xf01f
  177. #define F367TER_OVF_RATE_LO 0xf01f00ff
  178. /* GAIN_SRC1 */
  179. #define R367TER_GAIN_SRC1 0xf020
  180. #define F367TER_INV_SPECTR 0xf0200080
  181. #define F367TER_IQ_INVERT 0xf0200040
  182. #define F367TER_INR_BYPASS 0xf0200020
  183. #define F367TER_STATUS_INV_SPECRUM 0xf0200010
  184. #define F367TER_GAIN_SRC_HI 0xf020000f
  185. /* GAIN_SRC2 */
  186. #define R367TER_GAIN_SRC2 0xf021
  187. #define F367TER_GAIN_SRC_LO 0xf02100ff
  188. /* INC_DEROT1 */
  189. #define R367TER_INC_DEROT1 0xf022
  190. #define F367TER_INC_DEROT_HI 0xf02200ff
  191. /* INC_DEROT2 */
  192. #define R367TER_INC_DEROT2 0xf023
  193. #define F367TER_INC_DEROT_LO 0xf02300ff
  194. /* PPM_CPAMP_DIR */
  195. #define R367TER_PPM_CPAMP_DIR 0xf024
  196. #define F367TER_PPM_CPAMP_DIRECT 0xf02400ff
  197. /* PPM_CPAMP_INV */
  198. #define R367TER_PPM_CPAMP_INV 0xf025
  199. #define F367TER_PPM_CPAMP_INVER 0xf02500ff
  200. /* FREESTFE_1 */
  201. #define R367TER_FREESTFE_1 0xf026
  202. #define F367TER_SYMBOL_NUMBER_INC 0xf02600c0
  203. #define F367TER_SEL_LSB 0xf0260004
  204. #define F367TER_AVERAGE_ON 0xf0260002
  205. #define F367TER_DC_ADJ 0xf0260001
  206. /* FREESTFE_2 */
  207. #define R367TER_FREESTFE_2 0xf027
  208. #define F367TER_SEL_SRCOUT 0xf02700c0
  209. #define F367TER_SEL_SYRTHR 0xf027001f
  210. /* DCOFFSET */
  211. #define R367TER_DCOFFSET 0xf028
  212. #define F367TER_SELECT_I_Q 0xf0280080
  213. #define F367TER_DC_OFFSET 0xf028007f
  214. /* EN_PROCESS */
  215. #define R367TER_EN_PROCESS 0xf029
  216. #define F367TER_FREE 0xf02900f0
  217. #define F367TER_ENAB_MANUAL 0xf0290001
  218. /* SDI_SMOOTHER */
  219. #define R367TER_SDI_SMOOTHER 0xf02a
  220. #define F367TER_DIS_SMOOTH 0xf02a0080
  221. #define F367TER_SDI_INC_SMOOTHER 0xf02a007f
  222. /* FE_LOOP_OPEN */
  223. #define R367TER_FE_LOOP_OPEN 0xf02b
  224. #define F367TER_TRL_LOOP_OP 0xf02b0002
  225. #define F367TER_CRL_LOOP_OP 0xf02b0001
  226. /* FREQOFF1 */
  227. #define R367TER_FREQOFF1 0xf02c
  228. #define F367TER_FREQ_OFFSET_LOOP_OPEN_VHI 0xf02c00ff
  229. /* FREQOFF2 */
  230. #define R367TER_FREQOFF2 0xf02d
  231. #define F367TER_FREQ_OFFSET_LOOP_OPEN_HI 0xf02d00ff
  232. /* FREQOFF3 */
  233. #define R367TER_FREQOFF3 0xf02e
  234. #define F367TER_FREQ_OFFSET_LOOP_OPEN_LO 0xf02e00ff
  235. /* TIMOFF1 */
  236. #define R367TER_TIMOFF1 0xf02f
  237. #define F367TER_TIM_OFFSET_LOOP_OPEN_HI 0xf02f00ff
  238. /* TIMOFF2 */
  239. #define R367TER_TIMOFF2 0xf030
  240. #define F367TER_TIM_OFFSET_LOOP_OPEN_LO 0xf03000ff
  241. /* EPQ */
  242. #define R367TER_EPQ 0xf031
  243. #define F367TER_EPQ1 0xf03100ff
  244. /* EPQAUTO */
  245. #define R367TER_EPQAUTO 0xf032
  246. #define F367TER_EPQ2 0xf03200ff
  247. /* SYR_UPDATE */
  248. #define R367TER_SYR_UPDATE 0xf033
  249. #define F367TER_SYR_PROTV 0xf0330080
  250. #define F367TER_SYR_PROTV_GAIN 0xf0330060
  251. #define F367TER_SYR_FILTER 0xf0330010
  252. #define F367TER_SYR_TRACK_THRES 0xf033000c
  253. /* CHPFREE */
  254. #define R367TER_CHPFREE 0xf034
  255. #define F367TER_CHP_FREE 0xf03400ff
  256. /* PPM_STATE_MAC */
  257. #define R367TER_PPM_STATE_MAC 0xf035
  258. #define F367TER_PPM_STATE_MACHINE_DECODER 0xf035003f
  259. /* INR_THRESHOLD */
  260. #define R367TER_INR_THRESHOLD 0xf036
  261. #define F367TER_INR_THRESH 0xf03600ff
  262. /* EPQ_TPS_ID_CELL */
  263. #define R367TER_EPQ_TPS_ID_CELL 0xf037
  264. #define F367TER_ENABLE_LGTH_TO_CF 0xf0370080
  265. #define F367TER_DIS_TPS_RSVD 0xf0370040
  266. #define F367TER_DIS_BCH 0xf0370020
  267. #define F367TER_DIS_ID_CEL 0xf0370010
  268. #define F367TER_TPS_ADJUST_SYM 0xf037000f
  269. /* EPQ_CFG */
  270. #define R367TER_EPQ_CFG 0xf038
  271. #define F367TER_EPQ_RANGE 0xf0380002
  272. #define F367TER_EPQ_SOFT 0xf0380001
  273. /* EPQ_STATUS */
  274. #define R367TER_EPQ_STATUS 0xf039
  275. #define F367TER_SLOPE_INC 0xf03900fc
  276. #define F367TER_TPS_FIELD 0xf0390003
  277. /* AUTORELOCK */
  278. #define R367TER_AUTORELOCK 0xf03a
  279. #define F367TER_BYPASS_BER_TEMPO 0xf03a0080
  280. #define F367TER_BER_TEMPO 0xf03a0070
  281. #define F367TER_BYPASS_COFDM_TEMPO 0xf03a0008
  282. #define F367TER_COFDM_TEMPO 0xf03a0007
  283. /* BER_THR_VMSB */
  284. #define R367TER_BER_THR_VMSB 0xf03b
  285. #define F367TER_BER_THRESHOLD_HI 0xf03b00ff
  286. /* BER_THR_MSB */
  287. #define R367TER_BER_THR_MSB 0xf03c
  288. #define F367TER_BER_THRESHOLD_MID 0xf03c00ff
  289. /* BER_THR_LSB */
  290. #define R367TER_BER_THR_LSB 0xf03d
  291. #define F367TER_BER_THRESHOLD_LO 0xf03d00ff
  292. /* CCD */
  293. #define R367TER_CCD 0xf03e
  294. #define F367TER_CCD_DETECTED 0xf03e0080
  295. #define F367TER_CCD_RESET 0xf03e0040
  296. #define F367TER_CCD_THRESHOLD 0xf03e000f
  297. /* SPECTR_CFG */
  298. #define R367TER_SPECTR_CFG 0xf03f
  299. #define F367TER_SPECT_CFG 0xf03f0003
  300. /* CONSTMU_MSB */
  301. #define R367TER_CONSTMU_MSB 0xf040
  302. #define F367TER_CONSTMU_FREEZE 0xf0400080
  303. #define F367TER_CONSTNU_FORCE_EN 0xf0400040
  304. #define F367TER_CONST_MU_MSB 0xf040003f
  305. /* CONSTMU_LSB */
  306. #define R367TER_CONSTMU_LSB 0xf041
  307. #define F367TER_CONST_MU_LSB 0xf04100ff
  308. /* CONSTMU_MAX_MSB */
  309. #define R367TER_CONSTMU_MAX_MSB 0xf042
  310. #define F367TER_CONST_MU_MAX_MSB 0xf042003f
  311. /* CONSTMU_MAX_LSB */
  312. #define R367TER_CONSTMU_MAX_LSB 0xf043
  313. #define F367TER_CONST_MU_MAX_LSB 0xf04300ff
  314. /* ALPHANOISE */
  315. #define R367TER_ALPHANOISE 0xf044
  316. #define F367TER_USE_ALLFILTER 0xf0440080
  317. #define F367TER_INTER_ON 0xf0440040
  318. #define F367TER_ALPHA_NOISE 0xf044001f
  319. /* MAXGP_MSB */
  320. #define R367TER_MAXGP_MSB 0xf045
  321. #define F367TER_MUFILTER_LENGTH 0xf04500f0
  322. #define F367TER_MAX_GP_MSB 0xf045000f
  323. /* MAXGP_LSB */
  324. #define R367TER_MAXGP_LSB 0xf046
  325. #define F367TER_MAX_GP_LSB 0xf04600ff
  326. /* ALPHAMSB */
  327. #define R367TER_ALPHAMSB 0xf047
  328. #define F367TER_CHC_DATARATE 0xf04700c0
  329. #define F367TER_ALPHA_MSB 0xf047003f
  330. /* ALPHALSB */
  331. #define R367TER_ALPHALSB 0xf048
  332. #define F367TER_ALPHA_LSB 0xf04800ff
  333. /* PILOT_ACCU */
  334. #define R367TER_PILOT_ACCU 0xf049
  335. #define F367TER_USE_SCAT4ADDAPT 0xf0490080
  336. #define F367TER_PILOT_ACC 0xf049001f
  337. /* PILOTMU_ACCU */
  338. #define R367TER_PILOTMU_ACCU 0xf04a
  339. #define F367TER_DISCARD_BAD_SP 0xf04a0080
  340. #define F367TER_DISCARD_BAD_CP 0xf04a0040
  341. #define F367TER_PILOT_MU_ACCU 0xf04a001f
  342. /* FILT_CHANNEL_EST */
  343. #define R367TER_FILT_CHANNEL_EST 0xf04b
  344. #define F367TER_USE_FILT_PILOT 0xf04b0080
  345. #define F367TER_FILT_CHANNEL 0xf04b007f
  346. /* ALPHA_NOPISE_FREQ */
  347. #define R367TER_ALPHA_NOPISE_FREQ 0xf04c
  348. #define F367TER_NOISE_FREQ_FILT 0xf04c0040
  349. #define F367TER_ALPHA_NOISE_FREQ 0xf04c003f
  350. /* RATIO_PILOT */
  351. #define R367TER_RATIO_PILOT 0xf04d
  352. #define F367TER_RATIO_MEAN_SP 0xf04d00f0
  353. #define F367TER_RATIO_MEAN_CP 0xf04d000f
  354. /* CHC_CTL */
  355. #define R367TER_CHC_CTL 0xf04e
  356. #define F367TER_TRACK_EN 0xf04e0080
  357. #define F367TER_NOISE_NORM_EN 0xf04e0040
  358. #define F367TER_FORCE_CHC_RESET 0xf04e0020
  359. #define F367TER_SHORT_TIME 0xf04e0010
  360. #define F367TER_FORCE_STATE_EN 0xf04e0008
  361. #define F367TER_FORCE_STATE 0xf04e0007
  362. /* EPQ_ADJUST */
  363. #define R367TER_EPQ_ADJUST 0xf04f
  364. #define F367TER_ADJUST_SCAT_IND 0xf04f00c0
  365. #define F367TER_ONE_SYMBOL 0xf04f0010
  366. #define F367TER_EPQ_DECAY 0xf04f000e
  367. #define F367TER_HOLD_SLOPE 0xf04f0001
  368. /* EPQ_THRES */
  369. #define R367TER_EPQ_THRES 0xf050
  370. #define F367TER_EPQ_THR 0xf05000ff
  371. /* OMEGA_CTL */
  372. #define R367TER_OMEGA_CTL 0xf051
  373. #define F367TER_OMEGA_RST 0xf0510080
  374. #define F367TER_FREEZE_OMEGA 0xf0510040
  375. #define F367TER_OMEGA_SEL 0xf051003f
  376. /* GP_CTL */
  377. #define R367TER_GP_CTL 0xf052
  378. #define F367TER_CHC_STATE 0xf05200e0
  379. #define F367TER_FREEZE_GP 0xf0520010
  380. #define F367TER_GP_SEL 0xf052000f
  381. /* MUMSB */
  382. #define R367TER_MUMSB 0xf053
  383. #define F367TER_MU_MSB 0xf053007f
  384. /* MULSB */
  385. #define R367TER_MULSB 0xf054
  386. #define F367TER_MU_LSB 0xf05400ff
  387. /* GPMSB */
  388. #define R367TER_GPMSB 0xf055
  389. #define F367TER_CSI_THRESHOLD 0xf05500e0
  390. #define F367TER_GP_MSB 0xf055000f
  391. /* GPLSB */
  392. #define R367TER_GPLSB 0xf056
  393. #define F367TER_GP_LSB 0xf05600ff
  394. /* OMEGAMSB */
  395. #define R367TER_OMEGAMSB 0xf057
  396. #define F367TER_OMEGA_MSB 0xf057007f
  397. /* OMEGALSB */
  398. #define R367TER_OMEGALSB 0xf058
  399. #define F367TER_OMEGA_LSB 0xf05800ff
  400. /* SCAT_NB */
  401. #define R367TER_SCAT_NB 0xf059
  402. #define F367TER_CHC_TEST 0xf05900f8
  403. #define F367TER_SCAT_NUMB 0xf0590003
  404. /* CHC_DUMMY */
  405. #define R367TER_CHC_DUMMY 0xf05a
  406. #define F367TER_CHC_DUM 0xf05a00ff
  407. /* INC_CTL */
  408. #define R367TER_INC_CTL 0xf05b
  409. #define F367TER_INC_BYPASS 0xf05b0080
  410. #define F367TER_INC_NDEPTH 0xf05b000c
  411. #define F367TER_INC_MADEPTH 0xf05b0003
  412. /* INCTHRES_COR1 */
  413. #define R367TER_INCTHRES_COR1 0xf05c
  414. #define F367TER_INC_THRES_COR1 0xf05c00ff
  415. /* INCTHRES_COR2 */
  416. #define R367TER_INCTHRES_COR2 0xf05d
  417. #define F367TER_INC_THRES_COR2 0xf05d00ff
  418. /* INCTHRES_DET1 */
  419. #define R367TER_INCTHRES_DET1 0xf05e
  420. #define F367TER_INC_THRES_DET1 0xf05e003f
  421. /* INCTHRES_DET2 */
  422. #define R367TER_INCTHRES_DET2 0xf05f
  423. #define F367TER_INC_THRES_DET2 0xf05f003f
  424. /* IIR_CELLNB */
  425. #define R367TER_IIR_CELLNB 0xf060
  426. #define F367TER_NRST_IIR 0xf0600080
  427. #define F367TER_IIR_CELL_NB 0xf0600007
  428. /* IIRCX_COEFF1_MSB */
  429. #define R367TER_IIRCX_COEFF1_MSB 0xf061
  430. #define F367TER_IIR_CX_COEFF1_MSB 0xf06100ff
  431. /* IIRCX_COEFF1_LSB */
  432. #define R367TER_IIRCX_COEFF1_LSB 0xf062
  433. #define F367TER_IIR_CX_COEFF1_LSB 0xf06200ff
  434. /* IIRCX_COEFF2_MSB */
  435. #define R367TER_IIRCX_COEFF2_MSB 0xf063
  436. #define F367TER_IIR_CX_COEFF2_MSB 0xf06300ff
  437. /* IIRCX_COEFF2_LSB */
  438. #define R367TER_IIRCX_COEFF2_LSB 0xf064
  439. #define F367TER_IIR_CX_COEFF2_LSB 0xf06400ff
  440. /* IIRCX_COEFF3_MSB */
  441. #define R367TER_IIRCX_COEFF3_MSB 0xf065
  442. #define F367TER_IIR_CX_COEFF3_MSB 0xf06500ff
  443. /* IIRCX_COEFF3_LSB */
  444. #define R367TER_IIRCX_COEFF3_LSB 0xf066
  445. #define F367TER_IIR_CX_COEFF3_LSB 0xf06600ff
  446. /* IIRCX_COEFF4_MSB */
  447. #define R367TER_IIRCX_COEFF4_MSB 0xf067
  448. #define F367TER_IIR_CX_COEFF4_MSB 0xf06700ff
  449. /* IIRCX_COEFF4_LSB */
  450. #define R367TER_IIRCX_COEFF4_LSB 0xf068
  451. #define F367TER_IIR_CX_COEFF4_LSB 0xf06800ff
  452. /* IIRCX_COEFF5_MSB */
  453. #define R367TER_IIRCX_COEFF5_MSB 0xf069
  454. #define F367TER_IIR_CX_COEFF5_MSB 0xf06900ff
  455. /* IIRCX_COEFF5_LSB */
  456. #define R367TER_IIRCX_COEFF5_LSB 0xf06a
  457. #define F367TER_IIR_CX_COEFF5_LSB 0xf06a00ff
  458. /* FEPATH_CFG */
  459. #define R367TER_FEPATH_CFG 0xf06b
  460. #define F367TER_DEMUX_SWAP 0xf06b0004
  461. #define F367TER_DIGAGC_SWAP 0xf06b0002
  462. #define F367TER_LONGPATH_IF 0xf06b0001
  463. /* PMC1_FUNC */
  464. #define R367TER_PMC1_FUNC 0xf06c
  465. #define F367TER_SOFT_RSTN 0xf06c0080
  466. #define F367TER_PMC1_AVERAGE_TIME 0xf06c0078
  467. #define F367TER_PMC1_WAIT_TIME 0xf06c0006
  468. #define F367TER_PMC1_2N_SEL 0xf06c0001
  469. /* PMC1_FOR */
  470. #define R367TER_PMC1_FOR 0xf06d
  471. #define F367TER_PMC1_FORCE 0xf06d0080
  472. #define F367TER_PMC1_FORCE_VALUE 0xf06d007c
  473. /* PMC2_FUNC */
  474. #define R367TER_PMC2_FUNC 0xf06e
  475. #define F367TER_PMC2_SOFT_STN 0xf06e0080
  476. #define F367TER_PMC2_ACCU_TIME 0xf06e0070
  477. #define F367TER_PMC2_CMDP_MN 0xf06e0008
  478. #define F367TER_PMC2_SWAP 0xf06e0004
  479. /* STATUS_ERR_DA */
  480. #define R367TER_STATUS_ERR_DA 0xf06f
  481. #define F367TER_COM_USEGAINTRK 0xf06f0080
  482. #define F367TER_COM_AGCLOCK 0xf06f0040
  483. #define F367TER_AUT_AGCLOCK 0xf06f0020
  484. #define F367TER_MIN_ERR_X_LSB 0xf06f000f
  485. /* DIG_AGC_R */
  486. #define R367TER_DIG_AGC_R 0xf070
  487. #define F367TER_COM_SOFT_RSTN 0xf0700080
  488. #define F367TER_COM_AGC_ON 0xf0700040
  489. #define F367TER_COM_EARLY 0xf0700020
  490. #define F367TER_AUT_SOFT_RESETN 0xf0700010
  491. #define F367TER_AUT_AGC_ON 0xf0700008
  492. #define F367TER_AUT_EARLY 0xf0700004
  493. #define F367TER_AUT_ROT_EN 0xf0700002
  494. #define F367TER_LOCK_SOFT_RESETN 0xf0700001
  495. /* COMAGC_TARMSB */
  496. #define R367TER_COMAGC_TARMSB 0xf071
  497. #define F367TER_COM_AGC_TARGET_MSB 0xf07100ff
  498. /* COM_AGC_TAR_ENMODE */
  499. #define R367TER_COM_AGC_TAR_ENMODE 0xf072
  500. #define F367TER_COM_AGC_TARGET_LSB 0xf07200f0
  501. #define F367TER_COM_ENMODE 0xf072000f
  502. /* COM_AGC_CFG */
  503. #define R367TER_COM_AGC_CFG 0xf073
  504. #define F367TER_COM_N 0xf07300f8
  505. #define F367TER_COM_STABMODE 0xf0730006
  506. #define F367TER_ERR_SEL 0xf0730001
  507. /* COM_AGC_GAIN1 */
  508. #define R367TER_COM_AGC_GAIN1 0xf074
  509. #define F367TER_COM_GAIN1aCK 0xf07400f0
  510. #define F367TER_COM_GAIN1TRK 0xf074000f
  511. /* AUT_AGC_TARGETMSB */
  512. #define R367TER_AUT_AGC_TARGETMSB 0xf075
  513. #define F367TER_AUT_AGC_TARGET_MSB 0xf07500ff
  514. /* LOCK_DET_MSB */
  515. #define R367TER_LOCK_DET_MSB 0xf076
  516. #define F367TER_LOCK_DETECT_MSB 0xf07600ff
  517. /* AGCTAR_LOCK_LSBS */
  518. #define R367TER_AGCTAR_LOCK_LSBS 0xf077
  519. #define F367TER_AUT_AGC_TARGET_LSB 0xf07700f0
  520. #define F367TER_LOCK_DETECT_LSB 0xf077000f
  521. /* AUT_GAIN_EN */
  522. #define R367TER_AUT_GAIN_EN 0xf078
  523. #define F367TER_AUT_ENMODE 0xf07800f0
  524. #define F367TER_AUT_GAIN2 0xf078000f
  525. /* AUT_CFG */
  526. #define R367TER_AUT_CFG 0xf079
  527. #define F367TER_AUT_N 0xf07900f8
  528. #define F367TER_INT_CHOICE 0xf0790006
  529. #define F367TER_INT_LOAD 0xf0790001
  530. /* LOCKN */
  531. #define R367TER_LOCKN 0xf07a
  532. #define F367TER_LOCK_N 0xf07a00f8
  533. #define F367TER_SEL_IQNTAR 0xf07a0004
  534. #define F367TER_LOCK_DETECT_CHOICE 0xf07a0003
  535. /* INT_X_3 */
  536. #define R367TER_INT_X_3 0xf07b
  537. #define F367TER_INT_X3 0xf07b00ff
  538. /* INT_X_2 */
  539. #define R367TER_INT_X_2 0xf07c
  540. #define F367TER_INT_X2 0xf07c00ff
  541. /* INT_X_1 */
  542. #define R367TER_INT_X_1 0xf07d
  543. #define F367TER_INT_X1 0xf07d00ff
  544. /* INT_X_0 */
  545. #define R367TER_INT_X_0 0xf07e
  546. #define F367TER_INT_X0 0xf07e00ff
  547. /* MIN_ERRX_MSB */
  548. #define R367TER_MIN_ERRX_MSB 0xf07f
  549. #define F367TER_MIN_ERR_X_MSB 0xf07f00ff
  550. /* COR_CTL */
  551. #define R367TER_COR_CTL 0xf080
  552. #define F367TER_CORE_ACTIVE 0xf0800020
  553. #define F367TER_HOLD 0xf0800010
  554. #define F367TER_CORE_STATE_CTL 0xf080000f
  555. /* COR_STAT */
  556. #define R367TER_COR_STAT 0xf081
  557. #define F367TER_SCATT_LOCKED 0xf0810080
  558. #define F367TER_TPS_LOCKED 0xf0810040
  559. #define F367TER_SYR_LOCKED_COR 0xf0810020
  560. #define F367TER_AGC_LOCKED_STAT 0xf0810010
  561. #define F367TER_CORE_STATE_STAT 0xf081000f
  562. /* COR_INTEN */
  563. #define R367TER_COR_INTEN 0xf082
  564. #define F367TER_INTEN 0xf0820080
  565. #define F367TER_INTEN_SYR 0xf0820020
  566. #define F367TER_INTEN_FFT 0xf0820010
  567. #define F367TER_INTEN_AGC 0xf0820008
  568. #define F367TER_INTEN_TPS1 0xf0820004
  569. #define F367TER_INTEN_TPS2 0xf0820002
  570. #define F367TER_INTEN_TPS3 0xf0820001
  571. /* COR_INTSTAT */
  572. #define R367TER_COR_INTSTAT 0xf083
  573. #define F367TER_INTSTAT_SYR 0xf0830020
  574. #define F367TER_INTSTAT_FFT 0xf0830010
  575. #define F367TER_INTSAT_AGC 0xf0830008
  576. #define F367TER_INTSTAT_TPS1 0xf0830004
  577. #define F367TER_INTSTAT_TPS2 0xf0830002
  578. #define F367TER_INTSTAT_TPS3 0xf0830001
  579. /* COR_MODEGUARD */
  580. #define R367TER_COR_MODEGUARD 0xf084
  581. #define F367TER_FORCE 0xf0840010
  582. #define F367TER_MODE 0xf084000c
  583. #define F367TER_GUARD 0xf0840003
  584. /* AGC_CTL */
  585. #define R367TER_AGC_CTL 0xf085
  586. #define F367TER_AGC_TIMING_FACTOR 0xf08500e0
  587. #define F367TER_AGC_LAST 0xf0850010
  588. #define F367TER_AGC_GAIN 0xf085000c
  589. #define F367TER_AGC_NEG 0xf0850002
  590. #define F367TER_AGC_SET 0xf0850001
  591. /* AGC_MANUAL1 */
  592. #define R367TER_AGC_MANUAL1 0xf086
  593. #define F367TER_AGC_VAL_LO 0xf08600ff
  594. /* AGC_MANUAL2 */
  595. #define R367TER_AGC_MANUAL2 0xf087
  596. #define F367TER_AGC_VAL_HI 0xf087000f
  597. /* AGC_TARG */
  598. #define R367TER_AGC_TARG 0xf088
  599. #define F367TER_AGC_TARGET 0xf08800ff
  600. /* AGC_GAIN1 */
  601. #define R367TER_AGC_GAIN1 0xf089
  602. #define F367TER_AGC_GAIN_LO 0xf08900ff
  603. /* AGC_GAIN2 */
  604. #define R367TER_AGC_GAIN2 0xf08a
  605. #define F367TER_AGC_LOCKED_GAIN2 0xf08a0010
  606. #define F367TER_AGC_GAIN_HI 0xf08a000f
  607. /* RESERVED_1 */
  608. #define R367TER_RESERVED_1 0xf08b
  609. #define F367TER_RESERVED1 0xf08b00ff
  610. /* RESERVED_2 */
  611. #define R367TER_RESERVED_2 0xf08c
  612. #define F367TER_RESERVED2 0xf08c00ff
  613. /* RESERVED_3 */
  614. #define R367TER_RESERVED_3 0xf08d
  615. #define F367TER_RESERVED3 0xf08d00ff
  616. /* CAS_CTL */
  617. #define R367TER_CAS_CTL 0xf08e
  618. #define F367TER_CCS_ENABLE 0xf08e0080
  619. #define F367TER_ACS_DISABLE 0xf08e0040
  620. #define F367TER_DAGC_DIS 0xf08e0020
  621. #define F367TER_DAGC_GAIN 0xf08e0018
  622. #define F367TER_CCSMU 0xf08e0007
  623. /* CAS_FREQ */
  624. #define R367TER_CAS_FREQ 0xf08f
  625. #define F367TER_CCS_FREQ 0xf08f00ff
  626. /* CAS_DAGCGAIN */
  627. #define R367TER_CAS_DAGCGAIN 0xf090
  628. #define F367TER_CAS_DAGC_GAIN 0xf09000ff
  629. /* SYR_CTL */
  630. #define R367TER_SYR_CTL 0xf091
  631. #define F367TER_SICTH_ENABLE 0xf0910080
  632. #define F367TER_LONG_ECHO 0xf0910078
  633. #define F367TER_AUTO_LE_EN 0xf0910004
  634. #define F367TER_SYR_BYPASS 0xf0910002
  635. #define F367TER_SYR_TR_DIS 0xf0910001
  636. /* SYR_STAT */
  637. #define R367TER_SYR_STAT 0xf092
  638. #define F367TER_SYR_LOCKED_STAT 0xf0920010
  639. #define F367TER_SYR_MODE 0xf092000c
  640. #define F367TER_SYR_GUARD 0xf0920003
  641. /* SYR_NCO1 */
  642. #define R367TER_SYR_NCO1 0xf093
  643. #define F367TER_SYR_NCO_LO 0xf09300ff
  644. /* SYR_NCO2 */
  645. #define R367TER_SYR_NCO2 0xf094
  646. #define F367TER_SYR_NCO_HI 0xf094003f
  647. /* SYR_OFFSET1 */
  648. #define R367TER_SYR_OFFSET1 0xf095
  649. #define F367TER_SYR_OFFSET_LO 0xf09500ff
  650. /* SYR_OFFSET2 */
  651. #define R367TER_SYR_OFFSET2 0xf096
  652. #define F367TER_SYR_OFFSET_HI 0xf096003f
  653. /* FFT_CTL */
  654. #define R367TER_FFT_CTL 0xf097
  655. #define F367TER_SHIFT_FFT_TRIG 0xf0970018
  656. #define F367TER_FFT_TRIGGER 0xf0970004
  657. #define F367TER_FFT_MANUAL 0xf0970002
  658. #define F367TER_IFFT_MODE 0xf0970001
  659. /* SCR_CTL */
  660. #define R367TER_SCR_CTL 0xf098
  661. #define F367TER_SYRADJDECAY 0xf0980070
  662. #define F367TER_SCR_CPEDIS 0xf0980002
  663. #define F367TER_SCR_DIS 0xf0980001
  664. /* PPM_CTL1 */
  665. #define R367TER_PPM_CTL1 0xf099
  666. #define F367TER_PPM_MAXFREQ 0xf0990030
  667. #define F367TER_PPM_MAXTIM 0xf0990008
  668. #define F367TER_PPM_INVSEL 0xf0990004
  669. #define F367TER_PPM_SCATDIS 0xf0990002
  670. #define F367TER_PPM_BYP 0xf0990001
  671. /* TRL_CTL */
  672. #define R367TER_TRL_CTL 0xf09a
  673. #define F367TER_TRL_NOMRATE_LSB 0xf09a0080
  674. #define F367TER_TRL_GAIN_FACTOR 0xf09a0078
  675. #define F367TER_TRL_LOOPGAIN 0xf09a0007
  676. /* TRL_NOMRATE1 */
  677. #define R367TER_TRL_NOMRATE1 0xf09b
  678. #define F367TER_TRL_NOMRATE_LO 0xf09b00ff
  679. /* TRL_NOMRATE2 */
  680. #define R367TER_TRL_NOMRATE2 0xf09c
  681. #define F367TER_TRL_NOMRATE_HI 0xf09c00ff
  682. /* TRL_TIME1 */
  683. #define R367TER_TRL_TIME1 0xf09d
  684. #define F367TER_TRL_TOFFSET_LO 0xf09d00ff
  685. /* TRL_TIME2 */
  686. #define R367TER_TRL_TIME2 0xf09e
  687. #define F367TER_TRL_TOFFSET_HI 0xf09e00ff
  688. /* CRL_CTL */
  689. #define R367TER_CRL_CTL 0xf09f
  690. #define F367TER_CRL_DIS 0xf09f0080
  691. #define F367TER_CRL_GAIN_FACTOR 0xf09f0078
  692. #define F367TER_CRL_LOOPGAIN 0xf09f0007
  693. /* CRL_FREQ1 */
  694. #define R367TER_CRL_FREQ1 0xf0a0
  695. #define F367TER_CRL_FOFFSET_LO 0xf0a000ff
  696. /* CRL_FREQ2 */
  697. #define R367TER_CRL_FREQ2 0xf0a1
  698. #define F367TER_CRL_FOFFSET_HI 0xf0a100ff
  699. /* CRL_FREQ3 */
  700. #define R367TER_CRL_FREQ3 0xf0a2
  701. #define F367TER_CRL_FOFFSET_VHI 0xf0a200ff
  702. /* TPS_SFRAME_CTL */
  703. #define R367TER_TPS_SFRAME_CTL 0xf0a3
  704. #define F367TER_TPS_SFRAME_SYNC 0xf0a30001
  705. /* CHC_SNR */
  706. #define R367TER_CHC_SNR 0xf0a4
  707. #define F367TER_CHCSNR 0xf0a400ff
  708. /* BDI_CTL */
  709. #define R367TER_BDI_CTL 0xf0a5
  710. #define F367TER_BDI_LPSEL 0xf0a50002
  711. #define F367TER_BDI_SERIAL 0xf0a50001
  712. /* DMP_CTL */
  713. #define R367TER_DMP_CTL 0xf0a6
  714. #define F367TER_DMP_SCALING_FACTOR 0xf0a6001e
  715. #define F367TER_DMP_SDDIS 0xf0a60001
  716. /* TPS_RCVD1 */
  717. #define R367TER_TPS_RCVD1 0xf0a7
  718. #define F367TER_TPS_CHANGE 0xf0a70040
  719. #define F367TER_BCH_OK 0xf0a70020
  720. #define F367TER_TPS_SYNC 0xf0a70010
  721. #define F367TER_TPS_FRAME 0xf0a70003
  722. /* TPS_RCVD2 */
  723. #define R367TER_TPS_RCVD2 0xf0a8
  724. #define F367TER_TPS_HIERMODE 0xf0a80070
  725. #define F367TER_TPS_CONST 0xf0a80003
  726. /* TPS_RCVD3 */
  727. #define R367TER_TPS_RCVD3 0xf0a9
  728. #define F367TER_TPS_LPCODE 0xf0a90070
  729. #define F367TER_TPS_HPCODE 0xf0a90007
  730. /* TPS_RCVD4 */
  731. #define R367TER_TPS_RCVD4 0xf0aa
  732. #define F367TER_TPS_GUARD 0xf0aa0030
  733. #define F367TER_TPS_MODE 0xf0aa0003
  734. /* TPS_ID_CELL1 */
  735. #define R367TER_TPS_ID_CELL1 0xf0ab
  736. #define F367TER_TPS_ID_CELL_LO 0xf0ab00ff
  737. /* TPS_ID_CELL2 */
  738. #define R367TER_TPS_ID_CELL2 0xf0ac
  739. #define F367TER_TPS_ID_CELL_HI 0xf0ac00ff
  740. /* TPS_RCVD5_SET1 */
  741. #define R367TER_TPS_RCVD5_SET1 0xf0ad
  742. #define F367TER_TPS_NA 0xf0ad00fC
  743. #define F367TER_TPS_SETFRAME 0xf0ad0003
  744. /* TPS_SET2 */
  745. #define R367TER_TPS_SET2 0xf0ae
  746. #define F367TER_TPS_SETHIERMODE 0xf0ae0070
  747. #define F367TER_TPS_SETCONST 0xf0ae0003
  748. /* TPS_SET3 */
  749. #define R367TER_TPS_SET3 0xf0af
  750. #define F367TER_TPS_SETLPCODE 0xf0af0070
  751. #define F367TER_TPS_SETHPCODE 0xf0af0007
  752. /* TPS_CTL */
  753. #define R367TER_TPS_CTL 0xf0b0
  754. #define F367TER_TPS_IMM 0xf0b00004
  755. #define F367TER_TPS_BCHDIS 0xf0b00002
  756. #define F367TER_TPS_UPDDIS 0xf0b00001
  757. /* CTL_FFTOSNUM */
  758. #define R367TER_CTL_FFTOSNUM 0xf0b1
  759. #define F367TER_SYMBOL_NUMBER 0xf0b1007f
  760. /* TESTSELECT */
  761. #define R367TER_TESTSELECT 0xf0b2
  762. #define F367TER_TEST_SELECT 0xf0b2001f
  763. /* MSC_REV */
  764. #define R367TER_MSC_REV 0xf0b3
  765. #define F367TER_REV_NUMBER 0xf0b300ff
  766. /* PIR_CTL */
  767. #define R367TER_PIR_CTL 0xf0b4
  768. #define F367TER_FREEZE 0xf0b40001
  769. /* SNR_CARRIER1 */
  770. #define R367TER_SNR_CARRIER1 0xf0b5
  771. #define F367TER_SNR_CARRIER_LO 0xf0b500ff
  772. /* SNR_CARRIER2 */
  773. #define R367TER_SNR_CARRIER2 0xf0b6
  774. #define F367TER_MEAN 0xf0b600c0
  775. #define F367TER_SNR_CARRIER_HI 0xf0b6001f
  776. /* PPM_CPAMP */
  777. #define R367TER_PPM_CPAMP 0xf0b7
  778. #define F367TER_PPM_CPC 0xf0b700ff
  779. /* TSM_AP0 */
  780. #define R367TER_TSM_AP0 0xf0b8
  781. #define F367TER_ADDRESS_BYTE_0 0xf0b800ff
  782. /* TSM_AP1 */
  783. #define R367TER_TSM_AP1 0xf0b9
  784. #define F367TER_ADDRESS_BYTE_1 0xf0b900ff
  785. /* TSM_AP2 */
  786. #define R367TER_TSM_AP2 0xf0bA
  787. #define F367TER_DATA_BYTE_0 0xf0ba00ff
  788. /* TSM_AP3 */
  789. #define R367TER_TSM_AP3 0xf0bB
  790. #define F367TER_DATA_BYTE_1 0xf0bb00ff
  791. /* TSM_AP4 */
  792. #define R367TER_TSM_AP4 0xf0bC
  793. #define F367TER_DATA_BYTE_2 0xf0bc00ff
  794. /* TSM_AP5 */
  795. #define R367TER_TSM_AP5 0xf0bD
  796. #define F367TER_DATA_BYTE_3 0xf0bd00ff
  797. /* TSM_AP6 */
  798. #define R367TER_TSM_AP6 0xf0bE
  799. #define F367TER_TSM_AP_6 0xf0be00ff
  800. /* TSM_AP7 */
  801. #define R367TER_TSM_AP7 0xf0bF
  802. #define F367TER_MEM_SELECT_BYTE 0xf0bf00ff
  803. /* TSTRES */
  804. #define R367TER_TSTRES 0xf0c0
  805. #define F367TER_FRES_DISPLAY 0xf0c00080
  806. #define F367TER_FRES_FIFO_AD 0xf0c00020
  807. #define F367TER_FRESRS 0xf0c00010
  808. #define F367TER_FRESACS 0xf0c00008
  809. #define F367TER_FRESFEC 0xf0c00004
  810. #define F367TER_FRES_PRIF 0xf0c00002
  811. #define F367TER_FRESCORE 0xf0c00001
  812. /* ANACTRL */
  813. #define R367TER_ANACTRL 0xf0c1
  814. #define F367TER_BYPASS_XTAL 0xf0c10040
  815. #define F367TER_BYPASS_PLLXN 0xf0c1000c
  816. #define F367TER_DIS_PAD_OSC 0xf0c10002
  817. #define F367TER_STDBY_PLLXN 0xf0c10001
  818. /* TSTBUS */
  819. #define R367TER_TSTBUS 0xf0c2
  820. #define F367TER_TS_BYTE_CLK_INV 0xf0c20080
  821. #define F367TER_CFG_IP 0xf0c20070
  822. #define F367TER_CFG_TST 0xf0c2000f
  823. /* TSTRATE */
  824. #define R367TER_TSTRATE 0xf0c6
  825. #define F367TER_FORCEPHA 0xf0c60080
  826. #define F367TER_FNEWPHA 0xf0c60010
  827. #define F367TER_FROT90 0xf0c60008
  828. #define F367TER_FR 0xf0c60007
  829. /* CONSTMODE */
  830. #define R367TER_CONSTMODE 0xf0cb
  831. #define F367TER_TST_PRIF 0xf0cb00e0
  832. #define F367TER_CAR_TYPE 0xf0cb0018
  833. #define F367TER_CONST_MODE 0xf0cb0003
  834. /* CONSTCARR1 */
  835. #define R367TER_CONSTCARR1 0xf0cc
  836. #define F367TER_CONST_CARR_LO 0xf0cc00ff
  837. /* CONSTCARR2 */
  838. #define R367TER_CONSTCARR2 0xf0cd
  839. #define F367TER_CONST_CARR_HI 0xf0cd001f
  840. /* ICONSTEL */
  841. #define R367TER_ICONSTEL 0xf0ce
  842. #define F367TER_PICONSTEL 0xf0ce00ff
  843. /* QCONSTEL */
  844. #define R367TER_QCONSTEL 0xf0cf
  845. #define F367TER_PQCONSTEL 0xf0cf00ff
  846. /* TSTBISTRES0 */
  847. #define R367TER_TSTBISTRES0 0xf0d0
  848. #define F367TER_BEND_PPM 0xf0d00080
  849. #define F367TER_BBAD_PPM 0xf0d00040
  850. #define F367TER_BEND_FFTW 0xf0d00020
  851. #define F367TER_BBAD_FFTW 0xf0d00010
  852. #define F367TER_BEND_FFT_BUF 0xf0d00008
  853. #define F367TER_BBAD_FFT_BUF 0xf0d00004
  854. #define F367TER_BEND_SYR 0xf0d00002
  855. #define F367TER_BBAD_SYR 0xf0d00001
  856. /* TSTBISTRES1 */
  857. #define R367TER_TSTBISTRES1 0xf0d1
  858. #define F367TER_BEND_CHC_CP 0xf0d10080
  859. #define F367TER_BBAD_CHC_CP 0xf0d10040
  860. #define F367TER_BEND_CHCI 0xf0d10020
  861. #define F367TER_BBAD_CHCI 0xf0d10010
  862. #define F367TER_BEND_BDI 0xf0d10008
  863. #define F367TER_BBAD_BDI 0xf0d10004
  864. #define F367TER_BEND_SDI 0xf0d10002
  865. #define F367TER_BBAD_SDI 0xf0d10001
  866. /* TSTBISTRES2 */
  867. #define R367TER_TSTBISTRES2 0xf0d2
  868. #define F367TER_BEND_CHC_INC 0xf0d20080
  869. #define F367TER_BBAD_CHC_INC 0xf0d20040
  870. #define F367TER_BEND_CHC_SPP 0xf0d20020
  871. #define F367TER_BBAD_CHC_SPP 0xf0d20010
  872. #define F367TER_BEND_CHC_CPP 0xf0d20008
  873. #define F367TER_BBAD_CHC_CPP 0xf0d20004
  874. #define F367TER_BEND_CHC_SP 0xf0d20002
  875. #define F367TER_BBAD_CHC_SP 0xf0d20001
  876. /* TSTBISTRES3 */
  877. #define R367TER_TSTBISTRES3 0xf0d3
  878. #define F367TER_BEND_QAM 0xf0d30080
  879. #define F367TER_BBAD_QAM 0xf0d30040
  880. #define F367TER_BEND_SFEC_VIT 0xf0d30020
  881. #define F367TER_BBAD_SFEC_VIT 0xf0d30010
  882. #define F367TER_BEND_SFEC_DLINE 0xf0d30008
  883. #define F367TER_BBAD_SFEC_DLINE 0xf0d30004
  884. #define F367TER_BEND_SFEC_HW 0xf0d30002
  885. #define F367TER_BBAD_SFEC_HW 0xf0d30001
  886. /* RF_AGC1 */
  887. #define R367TER_RF_AGC1 0xf0d4
  888. #define F367TER_RF_AGC1_LEVEL_HI 0xf0d400ff
  889. /* RF_AGC2 */
  890. #define R367TER_RF_AGC2 0xf0d5
  891. #define F367TER_REF_ADGP 0xf0d50080
  892. #define F367TER_STDBY_ADCGP 0xf0d50020
  893. #define F367TER_CHANNEL_SEL 0xf0d5001c
  894. #define F367TER_RF_AGC1_LEVEL_LO 0xf0d50003
  895. /* ANADIGCTRL */
  896. #define R367TER_ANADIGCTRL 0xf0d7
  897. #define F367TER_SEL_CLKDEM 0xf0d70020
  898. #define F367TER_EN_BUFFER_Q 0xf0d70010
  899. #define F367TER_EN_BUFFER_I 0xf0d70008
  900. #define F367TER_ADC_RIS_EGDE 0xf0d70004
  901. #define F367TER_SGN_ADC 0xf0d70002
  902. #define F367TER_SEL_AD12_SYNC 0xf0d70001
  903. /* PLLMDIV */
  904. #define R367TER_PLLMDIV 0xf0d8
  905. #define F367TER_PLL_MDIV 0xf0d800ff
  906. /* PLLNDIV */
  907. #define R367TER_PLLNDIV 0xf0d9
  908. #define F367TER_PLL_NDIV 0xf0d900ff
  909. /* PLLSETUP */
  910. #define R367TER_PLLSETUP 0xf0dA
  911. #define F367TER_PLL_PDIV 0xf0da0070
  912. #define F367TER_PLL_KDIV 0xf0da000f
  913. /* DUAL_AD12 */
  914. #define R367TER_DUAL_AD12 0xf0dB
  915. #define F367TER_FS20M 0xf0db0020
  916. #define F367TER_FS50M 0xf0db0010
  917. #define F367TER_INMODe0 0xf0db0008
  918. #define F367TER_POFFQ 0xf0db0004
  919. #define F367TER_POFFI 0xf0db0002
  920. #define F367TER_INMODE1 0xf0db0001
  921. /* TSTBIST */
  922. #define R367TER_TSTBIST 0xf0dC
  923. #define F367TER_TST_BYP_CLK 0xf0dc0080
  924. #define F367TER_TST_GCLKENA_STD 0xf0dc0040
  925. #define F367TER_TST_GCLKENA 0xf0dc0020
  926. #define F367TER_TST_MEMBIST 0xf0dc001f
  927. /* PAD_COMP_CTRL */
  928. #define R367TER_PAD_COMP_CTRL 0xf0dD
  929. #define F367TER_COMPTQ 0xf0dd0010
  930. #define F367TER_COMPEN 0xf0dd0008
  931. #define F367TER_FREEZE2 0xf0dd0004
  932. #define F367TER_SLEEP_INHBT 0xf0dd0002
  933. #define F367TER_CHIP_SLEEP 0xf0dd0001
  934. /* PAD_COMP_WR */
  935. #define R367TER_PAD_COMP_WR 0xf0de
  936. #define F367TER_WR_ASRC 0xf0de007f
  937. /* PAD_COMP_RD */
  938. #define R367TER_PAD_COMP_RD 0xf0df
  939. #define F367TER_COMPOK 0xf0df0080
  940. #define F367TER_RD_ASRC 0xf0df007f
  941. /* SYR_TARGET_FFTADJT_MSB */
  942. #define R367TER_SYR_TARGET_FFTADJT_MSB 0xf100
  943. #define F367TER_SYR_START 0xf1000080
  944. #define F367TER_SYR_TARGET_FFTADJ_HI 0xf100000f
  945. /* SYR_TARGET_FFTADJT_LSB */
  946. #define R367TER_SYR_TARGET_FFTADJT_LSB 0xf101
  947. #define F367TER_SYR_TARGET_FFTADJ_LO 0xf10100ff
  948. /* SYR_TARGET_CHCADJT_MSB */
  949. #define R367TER_SYR_TARGET_CHCADJT_MSB 0xf102
  950. #define F367TER_SYR_TARGET_CHCADJ_HI 0xf102000f
  951. /* SYR_TARGET_CHCADJT_LSB */
  952. #define R367TER_SYR_TARGET_CHCADJT_LSB 0xf103
  953. #define F367TER_SYR_TARGET_CHCADJ_LO 0xf10300ff
  954. /* SYR_FLAG */
  955. #define R367TER_SYR_FLAG 0xf104
  956. #define F367TER_TRIG_FLG1 0xf1040080
  957. #define F367TER_TRIG_FLG0 0xf1040040
  958. #define F367TER_FFT_FLG1 0xf1040008
  959. #define F367TER_FFT_FLG0 0xf1040004
  960. #define F367TER_CHC_FLG1 0xf1040002
  961. #define F367TER_CHC_FLG0 0xf1040001
  962. /* CRL_TARGET1 */
  963. #define R367TER_CRL_TARGET1 0xf105
  964. #define F367TER_CRL_START 0xf1050080
  965. #define F367TER_CRL_TARGET_VHI 0xf105000f
  966. /* CRL_TARGET2 */
  967. #define R367TER_CRL_TARGET2 0xf106
  968. #define F367TER_CRL_TARGET_HI 0xf10600ff
  969. /* CRL_TARGET3 */
  970. #define R367TER_CRL_TARGET3 0xf107
  971. #define F367TER_CRL_TARGET_LO 0xf10700ff
  972. /* CRL_TARGET4 */
  973. #define R367TER_CRL_TARGET4 0xf108
  974. #define F367TER_CRL_TARGET_VLO 0xf10800ff
  975. /* CRL_FLAG */
  976. #define R367TER_CRL_FLAG 0xf109
  977. #define F367TER_CRL_FLAG1 0xf1090002
  978. #define F367TER_CRL_FLAG0 0xf1090001
  979. /* TRL_TARGET1 */
  980. #define R367TER_TRL_TARGET1 0xf10a
  981. #define F367TER_TRL_TARGET_HI 0xf10a00ff
  982. /* TRL_TARGET2 */
  983. #define R367TER_TRL_TARGET2 0xf10b
  984. #define F367TER_TRL_TARGET_LO 0xf10b00ff
  985. /* TRL_CHC */
  986. #define R367TER_TRL_CHC 0xf10c
  987. #define F367TER_TRL_START 0xf10c0080
  988. #define F367TER_CHC_START 0xf10c0040
  989. #define F367TER_TRL_FLAG1 0xf10c0002
  990. #define F367TER_TRL_FLAG0 0xf10c0001
  991. /* CHC_SNR_TARG */
  992. #define R367TER_CHC_SNR_TARG 0xf10d
  993. #define F367TER_CHC_SNR_TARGET 0xf10d00ff
  994. /* TOP_TRACK */
  995. #define R367TER_TOP_TRACK 0xf10e
  996. #define F367TER_TOP_START 0xf10e0080
  997. #define F367TER_FIRST_FLAG 0xf10e0070
  998. #define F367TER_TOP_FLAG1 0xf10e0008
  999. #define F367TER_TOP_FLAG0 0xf10e0004
  1000. #define F367TER_CHC_FLAG1 0xf10e0002
  1001. #define F367TER_CHC_FLAG0 0xf10e0001
  1002. /* TRACKER_FREE1 */
  1003. #define R367TER_TRACKER_FREE1 0xf10f
  1004. #define F367TER_TRACKER_FREE_1 0xf10f00ff
  1005. /* ERROR_CRL1 */
  1006. #define R367TER_ERROR_CRL1 0xf110
  1007. #define F367TER_ERROR_CRL_VHI 0xf11000ff
  1008. /* ERROR_CRL2 */
  1009. #define R367TER_ERROR_CRL2 0xf111
  1010. #define F367TER_ERROR_CRL_HI 0xf11100ff
  1011. /* ERROR_CRL3 */
  1012. #define R367TER_ERROR_CRL3 0xf112
  1013. #define F367TER_ERROR_CRL_LOI 0xf11200ff
  1014. /* ERROR_CRL4 */
  1015. #define R367TER_ERROR_CRL4 0xf113
  1016. #define F367TER_ERROR_CRL_VLO 0xf11300ff
  1017. /* DEC_NCO1 */
  1018. #define R367TER_DEC_NCO1 0xf114
  1019. #define F367TER_DEC_NCO_VHI 0xf11400ff
  1020. /* DEC_NCO2 */
  1021. #define R367TER_DEC_NCO2 0xf115
  1022. #define F367TER_DEC_NCO_HI 0xf11500ff
  1023. /* DEC_NCO3 */
  1024. #define R367TER_DEC_NCO3 0xf116
  1025. #define F367TER_DEC_NCO_LO 0xf11600ff
  1026. /* SNR */
  1027. #define R367TER_SNR 0xf117
  1028. #define F367TER_SNRATIO 0xf11700ff
  1029. /* SYR_FFTADJ1 */
  1030. #define R367TER_SYR_FFTADJ1 0xf118
  1031. #define F367TER_SYR_FFTADJ_HI 0xf11800ff
  1032. /* SYR_FFTADJ2 */
  1033. #define R367TER_SYR_FFTADJ2 0xf119
  1034. #define F367TER_SYR_FFTADJ_LO 0xf11900ff
  1035. /* SYR_CHCADJ1 */
  1036. #define R367TER_SYR_CHCADJ1 0xf11a
  1037. #define F367TER_SYR_CHCADJ_HI 0xf11a00ff
  1038. /* SYR_CHCADJ2 */
  1039. #define R367TER_SYR_CHCADJ2 0xf11b
  1040. #define F367TER_SYR_CHCADJ_LO 0xf11b00ff
  1041. /* SYR_OFF */
  1042. #define R367TER_SYR_OFF 0xf11c
  1043. #define F367TER_SYR_OFFSET 0xf11c00ff
  1044. /* PPM_OFFSET1 */
  1045. #define R367TER_PPM_OFFSET1 0xf11d
  1046. #define F367TER_PPM_OFFSET_HI 0xf11d00ff
  1047. /* PPM_OFFSET2 */
  1048. #define R367TER_PPM_OFFSET2 0xf11e
  1049. #define F367TER_PPM_OFFSET_LO 0xf11e00ff
  1050. /* TRACKER_FREE2 */
  1051. #define R367TER_TRACKER_FREE2 0xf11f
  1052. #define F367TER_TRACKER_FREE_2 0xf11f00ff
  1053. /* DEBG_LT10 */
  1054. #define R367TER_DEBG_LT10 0xf120
  1055. #define F367TER_DEBUG_LT10 0xf12000ff
  1056. /* DEBG_LT11 */
  1057. #define R367TER_DEBG_LT11 0xf121
  1058. #define F367TER_DEBUG_LT11 0xf12100ff
  1059. /* DEBG_LT12 */
  1060. #define R367TER_DEBG_LT12 0xf122
  1061. #define F367TER_DEBUG_LT12 0xf12200ff
  1062. /* DEBG_LT13 */
  1063. #define R367TER_DEBG_LT13 0xf123
  1064. #define F367TER_DEBUG_LT13 0xf12300ff
  1065. /* DEBG_LT14 */
  1066. #define R367TER_DEBG_LT14 0xf124
  1067. #define F367TER_DEBUG_LT14 0xf12400ff
  1068. /* DEBG_LT15 */
  1069. #define R367TER_DEBG_LT15 0xf125
  1070. #define F367TER_DEBUG_LT15 0xf12500ff
  1071. /* DEBG_LT16 */
  1072. #define R367TER_DEBG_LT16 0xf126
  1073. #define F367TER_DEBUG_LT16 0xf12600ff
  1074. /* DEBG_LT17 */
  1075. #define R367TER_DEBG_LT17 0xf127
  1076. #define F367TER_DEBUG_LT17 0xf12700ff
  1077. /* DEBG_LT18 */
  1078. #define R367TER_DEBG_LT18 0xf128
  1079. #define F367TER_DEBUG_LT18 0xf12800ff
  1080. /* DEBG_LT19 */
  1081. #define R367TER_DEBG_LT19 0xf129
  1082. #define F367TER_DEBUG_LT19 0xf12900ff
  1083. /* DEBG_LT1a */
  1084. #define R367TER_DEBG_LT1A 0xf12a
  1085. #define F367TER_DEBUG_LT1A 0xf12a00ff
  1086. /* DEBG_LT1b */
  1087. #define R367TER_DEBG_LT1B 0xf12b
  1088. #define F367TER_DEBUG_LT1B 0xf12b00ff
  1089. /* DEBG_LT1c */
  1090. #define R367TER_DEBG_LT1C 0xf12c
  1091. #define F367TER_DEBUG_LT1C 0xf12c00ff
  1092. /* DEBG_LT1D */
  1093. #define R367TER_DEBG_LT1D 0xf12d
  1094. #define F367TER_DEBUG_LT1D 0xf12d00ff
  1095. /* DEBG_LT1E */
  1096. #define R367TER_DEBG_LT1E 0xf12e
  1097. #define F367TER_DEBUG_LT1E 0xf12e00ff
  1098. /* DEBG_LT1F */
  1099. #define R367TER_DEBG_LT1F 0xf12f
  1100. #define F367TER_DEBUG_LT1F 0xf12f00ff
  1101. /* RCCFGH */
  1102. #define R367TER_RCCFGH 0xf200
  1103. #define F367TER_TSRCFIFO_DVBCI 0xf2000080
  1104. #define F367TER_TSRCFIFO_SERIAL 0xf2000040
  1105. #define F367TER_TSRCFIFO_DISABLE 0xf2000020
  1106. #define F367TER_TSFIFO_2TORC 0xf2000010
  1107. #define F367TER_TSRCFIFO_HSGNLOUT 0xf2000008
  1108. #define F367TER_TSRCFIFO_ERRMODE 0xf2000006
  1109. #define F367TER_RCCFGH_0 0xf2000001
  1110. /* RCCFGM */
  1111. #define R367TER_RCCFGM 0xf201
  1112. #define F367TER_TSRCFIFO_MANSPEED 0xf20100c0
  1113. #define F367TER_TSRCFIFO_PERMDATA 0xf2010020
  1114. #define F367TER_TSRCFIFO_NONEWSGNL 0xf2010010
  1115. #define F367TER_RCBYTE_OVERSAMPLING 0xf201000e
  1116. #define F367TER_TSRCFIFO_INVDATA 0xf2010001
  1117. /* RCCFGL */
  1118. #define R367TER_RCCFGL 0xf202
  1119. #define F367TER_TSRCFIFO_BCLKDEL1cK 0xf20200c0
  1120. #define F367TER_RCCFGL_5 0xf2020020
  1121. #define F367TER_TSRCFIFO_DUTY50 0xf2020010
  1122. #define F367TER_TSRCFIFO_NSGNL2dATA 0xf2020008
  1123. #define F367TER_TSRCFIFO_DISSERMUX 0xf2020004
  1124. #define F367TER_RCCFGL_1 0xf2020002
  1125. #define F367TER_TSRCFIFO_STOPCKDIS 0xf2020001
  1126. /* RCINSDELH */
  1127. #define R367TER_RCINSDELH 0xf203
  1128. #define F367TER_TSRCDEL_SYNCBYTE 0xf2030080
  1129. #define F367TER_TSRCDEL_XXHEADER 0xf2030040
  1130. #define F367TER_TSRCDEL_BBHEADER 0xf2030020
  1131. #define F367TER_TSRCDEL_DATAFIELD 0xf2030010
  1132. #define F367TER_TSRCINSDEL_ISCR 0xf2030008
  1133. #define F367TER_TSRCINSDEL_NPD 0xf2030004
  1134. #define F367TER_TSRCINSDEL_RSPARITY 0xf2030002
  1135. #define F367TER_TSRCINSDEL_CRC8 0xf2030001
  1136. /* RCINSDELM */
  1137. #define R367TER_RCINSDELM 0xf204
  1138. #define F367TER_TSRCINS_BBPADDING 0xf2040080
  1139. #define F367TER_TSRCINS_BCHFEC 0xf2040040
  1140. #define F367TER_TSRCINS_LDPCFEC 0xf2040020
  1141. #define F367TER_TSRCINS_EMODCOD 0xf2040010
  1142. #define F367TER_TSRCINS_TOKEN 0xf2040008
  1143. #define F367TER_TSRCINS_XXXERR 0xf2040004
  1144. #define F367TER_TSRCINS_MATYPE 0xf2040002
  1145. #define F367TER_TSRCINS_UPL 0xf2040001
  1146. /* RCINSDELL */
  1147. #define R367TER_RCINSDELL 0xf205
  1148. #define F367TER_TSRCINS_DFL 0xf2050080
  1149. #define F367TER_TSRCINS_SYNCD 0xf2050040
  1150. #define F367TER_TSRCINS_BLOCLEN 0xf2050020
  1151. #define F367TER_TSRCINS_SIGPCOUNT 0xf2050010
  1152. #define F367TER_TSRCINS_FIFO 0xf2050008
  1153. #define F367TER_TSRCINS_REALPACK 0xf2050004
  1154. #define F367TER_TSRCINS_TSCONFIG 0xf2050002
  1155. #define F367TER_TSRCINS_LATENCY 0xf2050001
  1156. /* RCSTATUS */
  1157. #define R367TER_RCSTATUS 0xf206
  1158. #define F367TER_TSRCFIFO_LINEOK 0xf2060080
  1159. #define F367TER_TSRCFIFO_ERROR 0xf2060040
  1160. #define F367TER_TSRCFIFO_DATA7 0xf2060020
  1161. #define F367TER_RCSTATUS_4 0xf2060010
  1162. #define F367TER_TSRCFIFO_DEMODSEL 0xf2060008
  1163. #define F367TER_TSRC1FIFOSPEED_STORE 0xf2060004
  1164. #define F367TER_RCSTATUS_1 0xf2060002
  1165. #define F367TER_TSRCSERIAL_IMPOSSIBLE 0xf2060001
  1166. /* RCSPEED */
  1167. #define R367TER_RCSPEED 0xf207
  1168. #define F367TER_TSRCFIFO_OUTSPEED 0xf20700ff
  1169. /* RCDEBUGM */
  1170. #define R367TER_RCDEBUGM 0xf208
  1171. #define F367TER_SD_UNSYNC 0xf2080080
  1172. #define F367TER_ULFLOCK_DETECTM 0xf2080040
  1173. #define F367TER_SUL_SELECTOS 0xf2080020
  1174. #define F367TER_DILUL_NOSCRBLE 0xf2080010
  1175. #define F367TER_NUL_SCRB 0xf2080008
  1176. #define F367TER_UL_SCRB 0xf2080004
  1177. #define F367TER_SCRAULBAD 0xf2080002
  1178. #define F367TER_SCRAUL_UNSYNC 0xf2080001
  1179. /* RCDEBUGL */
  1180. #define R367TER_RCDEBUGL 0xf209
  1181. #define F367TER_RS_ERR 0xf2090080
  1182. #define F367TER_LLFLOCK_DETECTM 0xf2090040
  1183. #define F367TER_NOT_SUL_SELECTOS 0xf2090020
  1184. #define F367TER_DILLL_NOSCRBLE 0xf2090010
  1185. #define F367TER_NLL_SCRB 0xf2090008
  1186. #define F367TER_LL_SCRB 0xf2090004
  1187. #define F367TER_SCRALLBAD 0xf2090002
  1188. #define F367TER_SCRALL_UNSYNC 0xf2090001
  1189. /* RCOBSCFG */
  1190. #define R367TER_RCOBSCFG 0xf20a
  1191. #define F367TER_TSRCFIFO_OBSCFG 0xf20a00ff
  1192. /* RCOBSM */
  1193. #define R367TER_RCOBSM 0xf20b
  1194. #define F367TER_TSRCFIFO_OBSDATA_HI 0xf20b00ff
  1195. /* RCOBSL */
  1196. #define R367TER_RCOBSL 0xf20c
  1197. #define F367TER_TSRCFIFO_OBSDATA_LO 0xf20c00ff
  1198. /* RCFECSPY */
  1199. #define R367TER_RCFECSPY 0xf210
  1200. #define F367TER_SPYRC_ENABLE 0xf2100080
  1201. #define F367TER_RCNO_SYNCBYTE 0xf2100040
  1202. #define F367TER_RCSERIAL_MODE 0xf2100020
  1203. #define F367TER_RCUNUSUAL_PACKET 0xf2100010
  1204. #define F367TER_BERRCMETER_DATAMODE 0xf210000c
  1205. #define F367TER_BERRCMETER_LMODE 0xf2100002
  1206. #define F367TER_BERRCMETER_RESET 0xf2100001
  1207. /* RCFSPYCFG */
  1208. #define R367TER_RCFSPYCFG 0xf211
  1209. #define F367TER_FECSPYRC_INPUT 0xf21100c0
  1210. #define F367TER_RCRST_ON_ERROR 0xf2110020
  1211. #define F367TER_RCONE_SHOT 0xf2110010
  1212. #define F367TER_RCI2C_MODE 0xf211000c
  1213. #define F367TER_SPYRC_HSTERESIS 0xf2110003
  1214. /* RCFSPYDATA */
  1215. #define R367TER_RCFSPYDATA 0xf212
  1216. #define F367TER_SPYRC_STUFFING 0xf2120080
  1217. #define F367TER_RCNOERR_PKTJITTER 0xf2120040
  1218. #define F367TER_SPYRC_CNULLPKT 0xf2120020
  1219. #define F367TER_SPYRC_OUTDATA_MODE 0xf212001f
  1220. /* RCFSPYOUT */
  1221. #define R367TER_RCFSPYOUT 0xf213
  1222. #define F367TER_FSPYRC_DIRECT 0xf2130080
  1223. #define F367TER_RCFSPYOUT_6 0xf2130040
  1224. #define F367TER_SPYRC_OUTDATA_BUS 0xf2130038
  1225. #define F367TER_RCSTUFF_MODE 0xf2130007
  1226. /* RCFSTATUS */
  1227. #define R367TER_RCFSTATUS 0xf214
  1228. #define F367TER_SPYRC_ENDSIM 0xf2140080
  1229. #define F367TER_RCVALID_SIM 0xf2140040
  1230. #define F367TER_RCFOUND_SIGNAL 0xf2140020
  1231. #define F367TER_RCDSS_SYNCBYTE 0xf2140010
  1232. #define F367TER_RCRESULT_STATE 0xf214000f
  1233. /* RCFGOODPACK */
  1234. #define R367TER_RCFGOODPACK 0xf215
  1235. #define F367TER_RCGOOD_PACKET 0xf21500ff
  1236. /* RCFPACKCNT */
  1237. #define R367TER_RCFPACKCNT 0xf216
  1238. #define F367TER_RCPACKET_COUNTER 0xf21600ff
  1239. /* RCFSPYMISC */
  1240. #define R367TER_RCFSPYMISC 0xf217
  1241. #define F367TER_RCLABEL_COUNTER 0xf21700ff
  1242. /* RCFBERCPT4 */
  1243. #define R367TER_RCFBERCPT4 0xf218
  1244. #define F367TER_FBERRCMETER_CPT_MMMMSB 0xf21800ff
  1245. /* RCFBERCPT3 */
  1246. #define R367TER_RCFBERCPT3 0xf219
  1247. #define F367TER_FBERRCMETER_CPT_MMMSB 0xf21900ff
  1248. /* RCFBERCPT2 */
  1249. #define R367TER_RCFBERCPT2 0xf21a
  1250. #define F367TER_FBERRCMETER_CPT_MMSB 0xf21a00ff
  1251. /* RCFBERCPT1 */
  1252. #define R367TER_RCFBERCPT1 0xf21b
  1253. #define F367TER_FBERRCMETER_CPT_MSB 0xf21b00ff
  1254. /* RCFBERCPT0 */
  1255. #define R367TER_RCFBERCPT0 0xf21c
  1256. #define F367TER_FBERRCMETER_CPT_LSB 0xf21c00ff
  1257. /* RCFBERERR2 */
  1258. #define R367TER_RCFBERERR2 0xf21d
  1259. #define F367TER_FBERRCMETER_ERR_HI 0xf21d00ff
  1260. /* RCFBERERR1 */
  1261. #define R367TER_RCFBERERR1 0xf21e
  1262. #define F367TER_FBERRCMETER_ERR 0xf21e00ff
  1263. /* RCFBERERR0 */
  1264. #define R367TER_RCFBERERR0 0xf21f
  1265. #define F367TER_FBERRCMETER_ERR_LO 0xf21f00ff
  1266. /* RCFSTATESM */
  1267. #define R367TER_RCFSTATESM 0xf220
  1268. #define F367TER_RCRSTATE_F 0xf2200080
  1269. #define F367TER_RCRSTATE_E 0xf2200040
  1270. #define F367TER_RCRSTATE_D 0xf2200020
  1271. #define F367TER_RCRSTATE_C 0xf2200010
  1272. #define F367TER_RCRSTATE_B 0xf2200008
  1273. #define F367TER_RCRSTATE_A 0xf2200004
  1274. #define F367TER_RCRSTATE_9 0xf2200002
  1275. #define F367TER_RCRSTATE_8 0xf2200001
  1276. /* RCFSTATESL */
  1277. #define R367TER_RCFSTATESL 0xf221
  1278. #define F367TER_RCRSTATE_7 0xf2210080
  1279. #define F367TER_RCRSTATE_6 0xf2210040
  1280. #define F367TER_RCRSTATE_5 0xf2210020
  1281. #define F367TER_RCRSTATE_4 0xf2210010
  1282. #define F367TER_RCRSTATE_3 0xf2210008
  1283. #define F367TER_RCRSTATE_2 0xf2210004
  1284. #define F367TER_RCRSTATE_1 0xf2210002
  1285. #define F367TER_RCRSTATE_0 0xf2210001
  1286. /* RCFSPYBER */
  1287. #define R367TER_RCFSPYBER 0xf222
  1288. #define F367TER_RCFSPYBER_7 0xf2220080
  1289. #define F367TER_SPYRCOBS_XORREAD 0xf2220040
  1290. #define F367TER_FSPYRCBER_OBSMODE 0xf2220020
  1291. #define F367TER_FSPYRCBER_SYNCBYT 0xf2220010
  1292. #define F367TER_FSPYRCBER_UNSYNC 0xf2220008
  1293. #define F367TER_FSPYRCBER_CTIME 0xf2220007
  1294. /* RCFSPYDISTM */
  1295. #define R367TER_RCFSPYDISTM 0xf223
  1296. #define F367TER_RCPKTTIME_DISTANCE_HI 0xf22300ff
  1297. /* RCFSPYDISTL */
  1298. #define R367TER_RCFSPYDISTL 0xf224
  1299. #define F367TER_RCPKTTIME_DISTANCE_LO 0xf22400ff
  1300. /* RCFSPYOBS7 */
  1301. #define R367TER_RCFSPYOBS7 0xf228
  1302. #define F367TER_RCSPYOBS_SPYFAIL 0xf2280080
  1303. #define F367TER_RCSPYOBS_SPYFAIL1 0xf2280040
  1304. #define F367TER_RCSPYOBS_ERROR 0xf2280020
  1305. #define F367TER_RCSPYOBS_STROUT 0xf2280010
  1306. #define F367TER_RCSPYOBS_RESULTSTATE1 0xf228000f
  1307. /* RCFSPYOBS6 */
  1308. #define R367TER_RCFSPYOBS6 0xf229
  1309. #define F367TER_RCSPYOBS_RESULTSTATe0 0xf22900f0
  1310. #define F367TER_RCSPYOBS_RESULTSTATEM1 0xf229000f
  1311. /* RCFSPYOBS5 */
  1312. #define R367TER_RCFSPYOBS5 0xf22a
  1313. #define F367TER_RCSPYOBS_BYTEOFPACKET1 0xf22a00ff
  1314. /* RCFSPYOBS4 */
  1315. #define R367TER_RCFSPYOBS4 0xf22b
  1316. #define F367TER_RCSPYOBS_BYTEVALUE1 0xf22b00ff
  1317. /* RCFSPYOBS3 */
  1318. #define R367TER_RCFSPYOBS3 0xf22c
  1319. #define F367TER_RCSPYOBS_DATA1 0xf22c00ff
  1320. /* RCFSPYOBS2 */
  1321. #define R367TER_RCFSPYOBS2 0xf22d
  1322. #define F367TER_RCSPYOBS_DATa0 0xf22d00ff
  1323. /* RCFSPYOBS1 */
  1324. #define R367TER_RCFSPYOBS1 0xf22e
  1325. #define F367TER_RCSPYOBS_DATAM1 0xf22e00ff
  1326. /* RCFSPYOBS0 */
  1327. #define R367TER_RCFSPYOBS0 0xf22f
  1328. #define F367TER_RCSPYOBS_DATAM2 0xf22f00ff
  1329. /* TSGENERAL */
  1330. #define R367TER_TSGENERAL 0xf230
  1331. #define F367TER_TSGENERAL_7 0xf2300080
  1332. #define F367TER_TSGENERAL_6 0xf2300040
  1333. #define F367TER_TSFIFO_BCLK1aLL 0xf2300020
  1334. #define F367TER_TSGENERAL_4 0xf2300010
  1335. #define F367TER_MUXSTREAM_OUTMODE 0xf2300008
  1336. #define F367TER_TSFIFO_PERMPARAL 0xf2300006
  1337. #define F367TER_RST_REEDSOLO 0xf2300001
  1338. /* RC1SPEED */
  1339. #define R367TER_RC1SPEED 0xf231
  1340. #define F367TER_TSRCFIFO1_OUTSPEED 0xf23100ff
  1341. /* TSGSTATUS */
  1342. #define R367TER_TSGSTATUS 0xf232
  1343. #define F367TER_TSGSTATUS_7 0xf2320080
  1344. #define F367TER_TSGSTATUS_6 0xf2320040
  1345. #define F367TER_RSMEM_FULL 0xf2320020
  1346. #define F367TER_RS_MULTCALC 0xf2320010
  1347. #define F367TER_RSIN_OVERTIME 0xf2320008
  1348. #define F367TER_TSFIFO3_DEMODSEL 0xf2320004
  1349. #define F367TER_TSFIFO2_DEMODSEL 0xf2320002
  1350. #define F367TER_TSFIFO1_DEMODSEL 0xf2320001
  1351. /* FECM */
  1352. #define R367TER_FECM 0xf233
  1353. #define F367TER_DSS_DVB 0xf2330080
  1354. #define F367TER_DEMOD_BYPASS 0xf2330040
  1355. #define F367TER_CMP_SLOWMODE 0xf2330020
  1356. #define F367TER_DSS_SRCH 0xf2330010
  1357. #define F367TER_FECM_3 0xf2330008
  1358. #define F367TER_DIFF_MODEVIT 0xf2330004
  1359. #define F367TER_SYNCVIT 0xf2330002
  1360. #define F367TER_I2CSYM 0xf2330001
  1361. /* VTH12 */
  1362. #define R367TER_VTH12 0xf234
  1363. #define F367TER_VTH_12 0xf23400ff
  1364. /* VTH23 */
  1365. #define R367TER_VTH23 0xf235
  1366. #define F367TER_VTH_23 0xf23500ff
  1367. /* VTH34 */
  1368. #define R367TER_VTH34 0xf236
  1369. #define F367TER_VTH_34 0xf23600ff
  1370. /* VTH56 */
  1371. #define R367TER_VTH56 0xf237
  1372. #define F367TER_VTH_56 0xf23700ff
  1373. /* VTH67 */
  1374. #define R367TER_VTH67 0xf238
  1375. #define F367TER_VTH_67 0xf23800ff
  1376. /* VTH78 */
  1377. #define R367TER_VTH78 0xf239
  1378. #define F367TER_VTH_78 0xf23900ff
  1379. /* VITCURPUN */
  1380. #define R367TER_VITCURPUN 0xf23a
  1381. #define F367TER_VIT_MAPPING 0xf23a00e0
  1382. #define F367TER_VIT_CURPUN 0xf23a001f
  1383. /* VERROR */
  1384. #define R367TER_VERROR 0xf23b
  1385. #define F367TER_REGERR_VIT 0xf23b00ff
  1386. /* PRVIT */
  1387. #define R367TER_PRVIT 0xf23c
  1388. #define F367TER_PRVIT_7 0xf23c0080
  1389. #define F367TER_DIS_VTHLOCK 0xf23c0040
  1390. #define F367TER_E7_8VIT 0xf23c0020
  1391. #define F367TER_E6_7VIT 0xf23c0010
  1392. #define F367TER_E5_6VIT 0xf23c0008
  1393. #define F367TER_E3_4VIT 0xf23c0004
  1394. #define F367TER_E2_3VIT 0xf23c0002
  1395. #define F367TER_E1_2VIT 0xf23c0001
  1396. /* VAVSRVIT */
  1397. #define R367TER_VAVSRVIT 0xf23d
  1398. #define F367TER_AMVIT 0xf23d0080
  1399. #define F367TER_FROZENVIT 0xf23d0040
  1400. #define F367TER_SNVIT 0xf23d0030
  1401. #define F367TER_TOVVIT 0xf23d000c
  1402. #define F367TER_HYPVIT 0xf23d0003
  1403. /* VSTATUSVIT */
  1404. #define R367TER_VSTATUSVIT 0xf23e
  1405. #define F367TER_VITERBI_ON 0xf23e0080
  1406. #define F367TER_END_LOOPVIT 0xf23e0040
  1407. #define F367TER_VITERBI_DEPRF 0xf23e0020
  1408. #define F367TER_PRFVIT 0xf23e0010
  1409. #define F367TER_LOCKEDVIT 0xf23e0008
  1410. #define F367TER_VITERBI_DELOCK 0xf23e0004
  1411. #define F367TER_VIT_DEMODSEL 0xf23e0002
  1412. #define F367TER_VITERBI_COMPOUT 0xf23e0001
  1413. /* VTHINUSE */
  1414. #define R367TER_VTHINUSE 0xf23f
  1415. #define F367TER_VIT_INUSE 0xf23f00ff
  1416. /* KDIV12 */
  1417. #define R367TER_KDIV12 0xf240
  1418. #define F367TER_KDIV12_MANUAL 0xf2400080
  1419. #define F367TER_K_DIVIDER_12 0xf240007f
  1420. /* KDIV23 */
  1421. #define R367TER_KDIV23 0xf241
  1422. #define F367TER_KDIV23_MANUAL 0xf2410080
  1423. #define F367TER_K_DIVIDER_23 0xf241007f
  1424. /* KDIV34 */
  1425. #define R367TER_KDIV34 0xf242
  1426. #define F367TER_KDIV34_MANUAL 0xf2420080
  1427. #define F367TER_K_DIVIDER_34 0xf242007f
  1428. /* KDIV56 */
  1429. #define R367TER_KDIV56 0xf243
  1430. #define F367TER_KDIV56_MANUAL 0xf2430080
  1431. #define F367TER_K_DIVIDER_56 0xf243007f
  1432. /* KDIV67 */
  1433. #define R367TER_KDIV67 0xf244
  1434. #define F367TER_KDIV67_MANUAL 0xf2440080
  1435. #define F367TER_K_DIVIDER_67 0xf244007f
  1436. /* KDIV78 */
  1437. #define R367TER_KDIV78 0xf245
  1438. #define F367TER_KDIV78_MANUAL 0xf2450080
  1439. #define F367TER_K_DIVIDER_78 0xf245007f
  1440. /* SIGPOWER */
  1441. #define R367TER_SIGPOWER 0xf246
  1442. #define F367TER_SIGPOWER_MANUAL 0xf2460080
  1443. #define F367TER_SIG_POWER 0xf246007f
  1444. /* DEMAPVIT */
  1445. #define R367TER_DEMAPVIT 0xf247
  1446. #define F367TER_DEMAPVIT_7 0xf2470080
  1447. #define F367TER_K_DIVIDER_VIT 0xf247007f
  1448. /* VITSCALE */
  1449. #define R367TER_VITSCALE 0xf248
  1450. #define F367TER_NVTH_NOSRANGE 0xf2480080
  1451. #define F367TER_VERROR_MAXMODE 0xf2480040
  1452. #define F367TER_KDIV_MODE 0xf2480030
  1453. #define F367TER_NSLOWSN_LOCKED 0xf2480008
  1454. #define F367TER_DELOCK_PRFLOSS 0xf2480004
  1455. #define F367TER_DIS_RSFLOCK 0xf2480002
  1456. #define F367TER_VITSCALE_0 0xf2480001
  1457. /* FFEC1PRG */
  1458. #define R367TER_FFEC1PRG 0xf249
  1459. #define F367TER_FDSS_DVB 0xf2490080
  1460. #define F367TER_FDSS_SRCH 0xf2490040
  1461. #define F367TER_FFECPROG_5 0xf2490020
  1462. #define F367TER_FFECPROG_4 0xf2490010
  1463. #define F367TER_FFECPROG_3 0xf2490008
  1464. #define F367TER_FFECPROG_2 0xf2490004
  1465. #define F367TER_FTS1_DISABLE 0xf2490002
  1466. #define F367TER_FTS2_DISABLE 0xf2490001
  1467. /* FVITCURPUN */
  1468. #define R367TER_FVITCURPUN 0xf24a
  1469. #define F367TER_FVIT_MAPPING 0xf24a00e0
  1470. #define F367TER_FVIT_CURPUN 0xf24a001f
  1471. /* FVERROR */
  1472. #define R367TER_FVERROR 0xf24b
  1473. #define F367TER_FREGERR_VIT 0xf24b00ff
  1474. /* FVSTATUSVIT */
  1475. #define R367TER_FVSTATUSVIT 0xf24c
  1476. #define F367TER_FVITERBI_ON 0xf24c0080
  1477. #define F367TER_F1END_LOOPVIT 0xf24c0040
  1478. #define F367TER_FVITERBI_DEPRF 0xf24c0020
  1479. #define F367TER_FPRFVIT 0xf24c0010
  1480. #define F367TER_FLOCKEDVIT 0xf24c0008
  1481. #define F367TER_FVITERBI_DELOCK 0xf24c0004
  1482. #define F367TER_FVIT_DEMODSEL 0xf24c0002
  1483. #define F367TER_FVITERBI_COMPOUT 0xf24c0001
  1484. /* DEBUG_LT1 */
  1485. #define R367TER_DEBUG_LT1 0xf24d
  1486. #define F367TER_DBG_LT1 0xf24d00ff
  1487. /* DEBUG_LT2 */
  1488. #define R367TER_DEBUG_LT2 0xf24e
  1489. #define F367TER_DBG_LT2 0xf24e00ff
  1490. /* DEBUG_LT3 */
  1491. #define R367TER_DEBUG_LT3 0xf24f
  1492. #define F367TER_DBG_LT3 0xf24f00ff
  1493. /* TSTSFMET */
  1494. #define R367TER_TSTSFMET 0xf250
  1495. #define F367TER_TSTSFEC_METRIQUES 0xf25000ff
  1496. /* SELOUT */
  1497. #define R367TER_SELOUT 0xf252
  1498. #define F367TER_EN_SYNC 0xf2520080
  1499. #define F367TER_EN_TBUSDEMAP 0xf2520040
  1500. #define F367TER_SELOUT_5 0xf2520020
  1501. #define F367TER_SELOUT_4 0xf2520010
  1502. #define F367TER_TSTSYNCHRO_MODE 0xf2520002
  1503. /* TSYNC */
  1504. #define R367TER_TSYNC 0xf253
  1505. #define F367TER_CURPUN_INCMODE 0xf2530080
  1506. #define F367TER_CERR_TSTMODE 0xf2530040
  1507. #define F367TER_SHIFTSOF_MODE 0xf2530030
  1508. #define F367TER_SLOWPHA_MODE 0xf2530008
  1509. #define F367TER_PXX_BYPALL 0xf2530004
  1510. #define F367TER_FROTA45_FIRST 0xf2530002
  1511. #define F367TER_TST_BCHERROR 0xf2530001
  1512. /* TSTERR */
  1513. #define R367TER_TSTERR 0xf254
  1514. #define F367TER_TST_LONGPKT 0xf2540080
  1515. #define F367TER_TST_ISSYION 0xf2540040
  1516. #define F367TER_TST_NPDON 0xf2540020
  1517. #define F367TER_TSTERR_4 0xf2540010
  1518. #define F367TER_TRACEBACK_MODE 0xf2540008
  1519. #define F367TER_TST_RSPARITY 0xf2540004
  1520. #define F367TER_METRIQUE_MODE 0xf2540003
  1521. /* TSFSYNC */
  1522. #define R367TER_TSFSYNC 0xf255
  1523. #define F367TER_EN_SFECSYNC 0xf2550080
  1524. #define F367TER_EN_SFECDEMAP 0xf2550040
  1525. #define F367TER_SFCERR_TSTMODE 0xf2550020
  1526. #define F367TER_SFECPXX_BYPALL 0xf2550010
  1527. #define F367TER_SFECTSTSYNCHRO_MODE 0xf255000f
  1528. /* TSTSFERR */
  1529. #define R367TER_TSTSFERR 0xf256
  1530. #define F367TER_TSTSTERR_7 0xf2560080
  1531. #define F367TER_TSTSTERR_6 0xf2560040
  1532. #define F367TER_TSTSTERR_5 0xf2560020
  1533. #define F367TER_TSTSTERR_4 0xf2560010
  1534. #define F367TER_SFECTRACEBACK_MODE 0xf2560008
  1535. #define F367TER_SFEC_NCONVPROG 0xf2560004
  1536. #define F367TER_SFECMETRIQUE_MODE 0xf2560003
  1537. /* TSTTSSF1 */
  1538. #define R367TER_TSTTSSF1 0xf258
  1539. #define F367TER_TSTERSSF 0xf2580080
  1540. #define F367TER_TSTTSSFEN 0xf2580040
  1541. #define F367TER_SFEC_OUTMODE 0xf2580030
  1542. #define F367TER_XLSF_NOFTHRESHOLD 0xf2580008
  1543. #define F367TER_TSTTSSF_STACKSEL 0xf2580007
  1544. /* TSTTSSF2 */
  1545. #define R367TER_TSTTSSF2 0xf259
  1546. #define F367TER_DILSF_DBBHEADER 0xf2590080
  1547. #define F367TER_TSTTSSF_DISBUG 0xf2590040
  1548. #define F367TER_TSTTSSF_NOBADSTART 0xf2590020
  1549. #define F367TER_TSTTSSF_SELECT 0xf259001f
  1550. /* TSTTSSF3 */
  1551. #define R367TER_TSTTSSF3 0xf25a
  1552. #define F367TER_TSTTSSF3_7 0xf25a0080
  1553. #define F367TER_TSTTSSF3_6 0xf25a0040
  1554. #define F367TER_TSTTSSF3_5 0xf25a0020
  1555. #define F367TER_TSTTSSF3_4 0xf25a0010
  1556. #define F367TER_TSTTSSF3_3 0xf25a0008
  1557. #define F367TER_TSTTSSF3_2 0xf25a0004
  1558. #define F367TER_TSTTSSF3_1 0xf25a0002
  1559. #define F367TER_DISSF_CLKENABLE 0xf25a0001
  1560. /* TSTTS1 */
  1561. #define R367TER_TSTTS1 0xf25c
  1562. #define F367TER_TSTERS 0xf25c0080
  1563. #define F367TER_TSFIFO_DSSSYNCB 0xf25c0040
  1564. #define F367TER_TSTTS_FSPYBEFRS 0xf25c0020
  1565. #define F367TER_NFORCE_SYNCBYTE 0xf25c0010
  1566. #define F367TER_XL_NOFTHRESHOLD 0xf25c0008
  1567. #define F367TER_TSTTS_FRFORCEPKT 0xf25c0004
  1568. #define F367TER_DESCR_NOTAUTO 0xf25c0002
  1569. #define F367TER_TSTTSEN 0xf25c0001
  1570. /* TSTTS2 */
  1571. #define R367TER_TSTTS2 0xf25d
  1572. #define F367TER_DIL_DBBHEADER 0xf25d0080
  1573. #define F367TER_TSTTS_NOBADXXX 0xf25d0040
  1574. #define F367TER_TSFIFO_DELSPEEDUP 0xf25d0020
  1575. #define F367TER_TSTTS_SELECT 0xf25d001f
  1576. /* TSTTS3 */
  1577. #define R367TER_TSTTS3 0xf25e
  1578. #define F367TER_TSTTS_NOPKTGAIN 0xf25e0080
  1579. #define F367TER_TSTTS_NOPKTENE 0xf25e0040
  1580. #define F367TER_TSTTS_ISOLATION 0xf25e0020
  1581. #define F367TER_TSTTS_DISBUG 0xf25e0010
  1582. #define F367TER_TSTTS_NOBADSTART 0xf25e0008
  1583. #define F367TER_TSTTS_STACKSEL 0xf25e0007
  1584. /* TSTTS4 */
  1585. #define R367TER_TSTTS4 0xf25f
  1586. #define F367TER_TSTTS4_7 0xf25f0080
  1587. #define F367TER_TSTTS4_6 0xf25f0040
  1588. #define F367TER_TSTTS4_5 0xf25f0020
  1589. #define F367TER_TSTTS_DISDSTATE 0xf25f0010
  1590. #define F367TER_TSTTS_FASTNOSYNC 0xf25f0008
  1591. #define F367TER_EXT_FECSPYIN 0xf25f0004
  1592. #define F367TER_TSTTS_NODPZERO 0xf25f0002
  1593. #define F367TER_TSTTS_NODIV3 0xf25f0001
  1594. /* TSTTSRC */
  1595. #define R367TER_TSTTSRC 0xf26c
  1596. #define F367TER_TSTTSRC_7 0xf26c0080
  1597. #define F367TER_TSRCFIFO_DSSSYNCB 0xf26c0040
  1598. #define F367TER_TSRCFIFO_DPUNACTIVE 0xf26c0020
  1599. #define F367TER_TSRCFIFO_DELSPEEDUP 0xf26c0010
  1600. #define F367TER_TSTTSRC_NODIV3 0xf26c0008
  1601. #define F367TER_TSTTSRC_FRFORCEPKT 0xf26c0004
  1602. #define F367TER_SAT25_SDDORIGINE 0xf26c0002
  1603. #define F367TER_TSTTSRC_INACTIVE 0xf26c0001
  1604. /* TSTTSRS */
  1605. #define R367TER_TSTTSRS 0xf26d
  1606. #define F367TER_TSTTSRS_7 0xf26d0080
  1607. #define F367TER_TSTTSRS_6 0xf26d0040
  1608. #define F367TER_TSTTSRS_5 0xf26d0020
  1609. #define F367TER_TSTTSRS_4 0xf26d0010
  1610. #define F367TER_TSTTSRS_3 0xf26d0008
  1611. #define F367TER_TSTTSRS_2 0xf26d0004
  1612. #define F367TER_TSTRS_DISRS2 0xf26d0002
  1613. #define F367TER_TSTRS_DISRS1 0xf26d0001
  1614. /* TSSTATEM */
  1615. #define R367TER_TSSTATEM 0xf270
  1616. #define F367TER_TSDIL_ON 0xf2700080
  1617. #define F367TER_TSSKIPRS_ON 0xf2700040
  1618. #define F367TER_TSRS_ON 0xf2700020
  1619. #define F367TER_TSDESCRAMB_ON 0xf2700010
  1620. #define F367TER_TSFRAME_MODE 0xf2700008
  1621. #define F367TER_TS_DISABLE 0xf2700004
  1622. #define F367TER_TSACM_MODE 0xf2700002
  1623. #define F367TER_TSOUT_NOSYNC 0xf2700001
  1624. /* TSSTATEL */
  1625. #define R367TER_TSSTATEL 0xf271
  1626. #define F367TER_TSNOSYNCBYTE 0xf2710080
  1627. #define F367TER_TSPARITY_ON 0xf2710040
  1628. #define F367TER_TSSYNCOUTRS_ON 0xf2710020
  1629. #define F367TER_TSDVBS2_MODE 0xf2710010
  1630. #define F367TER_TSISSYI_ON 0xf2710008
  1631. #define F367TER_TSNPD_ON 0xf2710004
  1632. #define F367TER_TSCRC8_ON 0xf2710002
  1633. #define F367TER_TSDSS_PACKET 0xf2710001
  1634. /* TSCFGH */
  1635. #define R367TER_TSCFGH 0xf272
  1636. #define F367TER_TSFIFO_DVBCI 0xf2720080
  1637. #define F367TER_TSFIFO_SERIAL 0xf2720040
  1638. #define F367TER_TSFIFO_TEIUPDATE 0xf2720020
  1639. #define F367TER_TSFIFO_DUTY50 0xf2720010
  1640. #define F367TER_TSFIFO_HSGNLOUT 0xf2720008
  1641. #define F367TER_TSFIFO_ERRMODE 0xf2720006
  1642. #define F367TER_RST_HWARE 0xf2720001
  1643. /* TSCFGM */
  1644. #define R367TER_TSCFGM 0xf273
  1645. #define F367TER_TSFIFO_MANSPEED 0xf27300c0
  1646. #define F367TER_TSFIFO_PERMDATA 0xf2730020
  1647. #define F367TER_TSFIFO_NONEWSGNL 0xf2730010
  1648. #define F367TER_TSFIFO_BITSPEED 0xf2730008
  1649. #define F367TER_NPD_SPECDVBS2 0xf2730004
  1650. #define F367TER_TSFIFO_STOPCKDIS 0xf2730002
  1651. #define F367TER_TSFIFO_INVDATA 0xf2730001
  1652. /* TSCFGL */
  1653. #define R367TER_TSCFGL 0xf274
  1654. #define F367TER_TSFIFO_BCLKDEL1cK 0xf27400c0
  1655. #define F367TER_BCHERROR_MODE 0xf2740030
  1656. #define F367TER_TSFIFO_NSGNL2dATA 0xf2740008
  1657. #define F367TER_TSFIFO_EMBINDVB 0xf2740004
  1658. #define F367TER_TSFIFO_DPUNACT 0xf2740002
  1659. #define F367TER_TSFIFO_NPDOFF 0xf2740001
  1660. /* TSSYNC */
  1661. #define R367TER_TSSYNC 0xf275
  1662. #define F367TER_TSFIFO_PERMUTE 0xf2750080
  1663. #define F367TER_TSFIFO_FISCR3B 0xf2750060
  1664. #define F367TER_TSFIFO_SYNCMODE 0xf2750018
  1665. #define F367TER_TSFIFO_SYNCSEL 0xf2750007
  1666. /* TSINSDELH */
  1667. #define R367TER_TSINSDELH 0xf276
  1668. #define F367TER_TSDEL_SYNCBYTE 0xf2760080
  1669. #define F367TER_TSDEL_XXHEADER 0xf2760040
  1670. #define F367TER_TSDEL_BBHEADER 0xf2760020
  1671. #define F367TER_TSDEL_DATAFIELD 0xf2760010
  1672. #define F367TER_TSINSDEL_ISCR 0xf2760008
  1673. #define F367TER_TSINSDEL_NPD 0xf2760004
  1674. #define F367TER_TSINSDEL_RSPARITY 0xf2760002
  1675. #define F367TER_TSINSDEL_CRC8 0xf2760001
  1676. /* TSINSDELM */
  1677. #define R367TER_TSINSDELM 0xf277
  1678. #define F367TER_TSINS_BBPADDING 0xf2770080
  1679. #define F367TER_TSINS_BCHFEC 0xf2770040
  1680. #define F367TER_TSINS_LDPCFEC 0xf2770020
  1681. #define F367TER_TSINS_EMODCOD 0xf2770010
  1682. #define F367TER_TSINS_TOKEN 0xf2770008
  1683. #define F367TER_TSINS_XXXERR 0xf2770004
  1684. #define F367TER_TSINS_MATYPE 0xf2770002
  1685. #define F367TER_TSINS_UPL 0xf2770001
  1686. /* TSINSDELL */
  1687. #define R367TER_TSINSDELL 0xf278
  1688. #define F367TER_TSINS_DFL 0xf2780080
  1689. #define F367TER_TSINS_SYNCD 0xf2780040
  1690. #define F367TER_TSINS_BLOCLEN 0xf2780020
  1691. #define F367TER_TSINS_SIGPCOUNT 0xf2780010
  1692. #define F367TER_TSINS_FIFO 0xf2780008
  1693. #define F367TER_TSINS_REALPACK 0xf2780004
  1694. #define F367TER_TSINS_TSCONFIG 0xf2780002
  1695. #define F367TER_TSINS_LATENCY 0xf2780001
  1696. /* TSDIVN */
  1697. #define R367TER_TSDIVN 0xf279
  1698. #define F367TER_TSFIFO_LOWSPEED 0xf2790080
  1699. #define F367TER_BYTE_OVERSAMPLING 0xf2790070
  1700. #define F367TER_TSMANUAL_PACKETNBR 0xf279000f
  1701. /* TSDIVPM */
  1702. #define R367TER_TSDIVPM 0xf27a
  1703. #define F367TER_TSMANUAL_P_HI 0xf27a00ff
  1704. /* TSDIVPL */
  1705. #define R367TER_TSDIVPL 0xf27b
  1706. #define F367TER_TSMANUAL_P_LO 0xf27b00ff
  1707. /* TSDIVQM */
  1708. #define R367TER_TSDIVQM 0xf27c
  1709. #define F367TER_TSMANUAL_Q_HI 0xf27c00ff
  1710. /* TSDIVQL */
  1711. #define R367TER_TSDIVQL 0xf27d
  1712. #define F367TER_TSMANUAL_Q_LO 0xf27d00ff
  1713. /* TSDILSTKM */
  1714. #define R367TER_TSDILSTKM 0xf27e
  1715. #define F367TER_TSFIFO_DILSTK_HI 0xf27e00ff
  1716. /* TSDILSTKL */
  1717. #define R367TER_TSDILSTKL 0xf27f
  1718. #define F367TER_TSFIFO_DILSTK_LO 0xf27f00ff
  1719. /* TSSPEED */
  1720. #define R367TER_TSSPEED 0xf280
  1721. #define F367TER_TSFIFO_OUTSPEED 0xf28000ff
  1722. /* TSSTATUS */
  1723. #define R367TER_TSSTATUS 0xf281
  1724. #define F367TER_TSFIFO_LINEOK 0xf2810080
  1725. #define F367TER_TSFIFO_ERROR 0xf2810040
  1726. #define F367TER_TSFIFO_DATA7 0xf2810020
  1727. #define F367TER_TSFIFO_NOSYNC 0xf2810010
  1728. #define F367TER_ISCR_INITIALIZED 0xf2810008
  1729. #define F367TER_ISCR_UPDATED 0xf2810004
  1730. #define F367TER_SOFFIFO_UNREGUL 0xf2810002
  1731. #define F367TER_DIL_READY 0xf2810001
  1732. /* TSSTATUS2 */
  1733. #define R367TER_TSSTATUS2 0xf282
  1734. #define F367TER_TSFIFO_DEMODSEL 0xf2820080
  1735. #define F367TER_TSFIFOSPEED_STORE 0xf2820040
  1736. #define F367TER_DILXX_RESET 0xf2820020
  1737. #define F367TER_TSSERIAL_IMPOSSIBLE 0xf2820010
  1738. #define F367TER_TSFIFO_UNDERSPEED 0xf2820008
  1739. #define F367TER_BITSPEED_EVENT 0xf2820004
  1740. #define F367TER_UL_SCRAMBDETECT 0xf2820002
  1741. #define F367TER_ULDTV67_FALSELOCK 0xf2820001
  1742. /* TSBITRATEM */
  1743. #define R367TER_TSBITRATEM 0xf283
  1744. #define F367TER_TSFIFO_BITRATE_HI 0xf28300ff
  1745. /* TSBITRATEL */
  1746. #define R367TER_TSBITRATEL 0xf284
  1747. #define F367TER_TSFIFO_BITRATE_LO 0xf28400ff
  1748. /* TSPACKLENM */
  1749. #define R367TER_TSPACKLENM 0xf285
  1750. #define F367TER_TSFIFO_PACKCPT 0xf28500e0
  1751. #define F367TER_DIL_RPLEN_HI 0xf285001f
  1752. /* TSPACKLENL */
  1753. #define R367TER_TSPACKLENL 0xf286
  1754. #define F367TER_DIL_RPLEN_LO 0xf28600ff
  1755. /* TSBLOCLENM */
  1756. #define R367TER_TSBLOCLENM 0xf287
  1757. #define F367TER_TSFIFO_PFLEN_HI 0xf28700ff
  1758. /* TSBLOCLENL */
  1759. #define R367TER_TSBLOCLENL 0xf288
  1760. #define F367TER_TSFIFO_PFLEN_LO 0xf28800ff
  1761. /* TSDLYH */
  1762. #define R367TER_TSDLYH 0xf289
  1763. #define F367TER_SOFFIFO_TSTIMEVALID 0xf2890080
  1764. #define F367TER_SOFFIFO_SPEEDUP 0xf2890040
  1765. #define F367TER_SOFFIFO_STOP 0xf2890020
  1766. #define F367TER_SOFFIFO_REGULATED 0xf2890010
  1767. #define F367TER_SOFFIFO_REALSBOFF_HI 0xf289000f
  1768. /* TSDLYM */
  1769. #define R367TER_TSDLYM 0xf28a
  1770. #define F367TER_SOFFIFO_REALSBOFF_MED 0xf28a00ff
  1771. /* TSDLYL */
  1772. #define R367TER_TSDLYL 0xf28b
  1773. #define F367TER_SOFFIFO_REALSBOFF_LO 0xf28b00ff
  1774. /* TSNPDAV */
  1775. #define R367TER_TSNPDAV 0xf28c
  1776. #define F367TER_TSNPD_AVERAGE 0xf28c00ff
  1777. /* TSBUFSTATH */
  1778. #define R367TER_TSBUFSTATH 0xf28d
  1779. #define F367TER_TSISCR_3BYTES 0xf28d0080
  1780. #define F367TER_TSISCR_NEWDATA 0xf28d0040
  1781. #define F367TER_TSISCR_BUFSTAT_HI 0xf28d003f
  1782. /* TSBUFSTATM */
  1783. #define R367TER_TSBUFSTATM 0xf28e
  1784. #define F367TER_TSISCR_BUFSTAT_MED 0xf28e00ff
  1785. /* TSBUFSTATL */
  1786. #define R367TER_TSBUFSTATL 0xf28f
  1787. #define F367TER_TSISCR_BUFSTAT_LO 0xf28f00ff
  1788. /* TSDEBUGM */
  1789. #define R367TER_TSDEBUGM 0xf290
  1790. #define F367TER_TSFIFO_ILLPACKET 0xf2900080
  1791. #define F367TER_DIL_NOSYNC 0xf2900040
  1792. #define F367TER_DIL_ISCR 0xf2900020
  1793. #define F367TER_DILOUT_BSYNCB 0xf2900010
  1794. #define F367TER_TSFIFO_EMPTYPKT 0xf2900008
  1795. #define F367TER_TSFIFO_EMPTYRD 0xf2900004
  1796. #define F367TER_SOFFIFO_STOPM 0xf2900002
  1797. #define F367TER_SOFFIFO_SPEEDUPM 0xf2900001
  1798. /* TSDEBUGL */
  1799. #define R367TER_TSDEBUGL 0xf291
  1800. #define F367TER_TSFIFO_PACKLENFAIL 0xf2910080
  1801. #define F367TER_TSFIFO_SYNCBFAIL 0xf2910040
  1802. #define F367TER_TSFIFO_VITLIBRE 0xf2910020
  1803. #define F367TER_TSFIFO_BOOSTSPEEDM 0xf2910010
  1804. #define F367TER_TSFIFO_UNDERSPEEDM 0xf2910008
  1805. #define F367TER_TSFIFO_ERROR_EVNT 0xf2910004
  1806. #define F367TER_TSFIFO_FULL 0xf2910002
  1807. #define F367TER_TSFIFO_OVERFLOWM 0xf2910001
  1808. /* TSDLYSETH */
  1809. #define R367TER_TSDLYSETH 0xf292
  1810. #define F367TER_SOFFIFO_OFFSET 0xf29200e0
  1811. #define F367TER_SOFFIFO_SYMBOFFSET_HI 0xf292001f
  1812. /* TSDLYSETM */
  1813. #define R367TER_TSDLYSETM 0xf293
  1814. #define F367TER_SOFFIFO_SYMBOFFSET_MED 0xf29300ff
  1815. /* TSDLYSETL */
  1816. #define R367TER_TSDLYSETL 0xf294
  1817. #define F367TER_SOFFIFO_SYMBOFFSET_LO 0xf29400ff
  1818. /* TSOBSCFG */
  1819. #define R367TER_TSOBSCFG 0xf295
  1820. #define F367TER_TSFIFO_OBSCFG 0xf29500ff
  1821. /* TSOBSM */
  1822. #define R367TER_TSOBSM 0xf296
  1823. #define F367TER_TSFIFO_OBSDATA_HI 0xf29600ff
  1824. /* TSOBSL */
  1825. #define R367TER_TSOBSL 0xf297
  1826. #define F367TER_TSFIFO_OBSDATA_LO 0xf29700ff
  1827. /* ERRCTRL1 */
  1828. #define R367TER_ERRCTRL1 0xf298
  1829. #define F367TER_ERR_SRC1 0xf29800f0
  1830. #define F367TER_ERRCTRL1_3 0xf2980008
  1831. #define F367TER_NUM_EVT1 0xf2980007
  1832. /* ERRCNT1H */
  1833. #define R367TER_ERRCNT1H 0xf299
  1834. #define F367TER_ERRCNT1_OLDVALUE 0xf2990080
  1835. #define F367TER_ERR_CNT1 0xf299007f
  1836. /* ERRCNT1M */
  1837. #define R367TER_ERRCNT1M 0xf29a
  1838. #define F367TER_ERR_CNT1_HI 0xf29a00ff
  1839. /* ERRCNT1L */
  1840. #define R367TER_ERRCNT1L 0xf29b
  1841. #define F367TER_ERR_CNT1_LO 0xf29b00ff
  1842. /* ERRCTRL2 */
  1843. #define R367TER_ERRCTRL2 0xf29c
  1844. #define F367TER_ERR_SRC2 0xf29c00f0
  1845. #define F367TER_ERRCTRL2_3 0xf29c0008
  1846. #define F367TER_NUM_EVT2 0xf29c0007
  1847. /* ERRCNT2H */
  1848. #define R367TER_ERRCNT2H 0xf29d
  1849. #define F367TER_ERRCNT2_OLDVALUE 0xf29d0080
  1850. #define F367TER_ERR_CNT2_HI 0xf29d007f
  1851. /* ERRCNT2M */
  1852. #define R367TER_ERRCNT2M 0xf29e
  1853. #define F367TER_ERR_CNT2_MED 0xf29e00ff
  1854. /* ERRCNT2L */
  1855. #define R367TER_ERRCNT2L 0xf29f
  1856. #define F367TER_ERR_CNT2_LO 0xf29f00ff
  1857. /* FECSPY */
  1858. #define R367TER_FECSPY 0xf2a0
  1859. #define F367TER_SPY_ENABLE 0xf2a00080
  1860. #define F367TER_NO_SYNCBYTE 0xf2a00040
  1861. #define F367TER_SERIAL_MODE 0xf2a00020
  1862. #define F367TER_UNUSUAL_PACKET 0xf2a00010
  1863. #define F367TER_BERMETER_DATAMODE 0xf2a0000c
  1864. #define F367TER_BERMETER_LMODE 0xf2a00002
  1865. #define F367TER_BERMETER_RESET 0xf2a00001
  1866. /* FSPYCFG */
  1867. #define R367TER_FSPYCFG 0xf2a1
  1868. #define F367TER_FECSPY_INPUT 0xf2a100c0
  1869. #define F367TER_RST_ON_ERROR 0xf2a10020
  1870. #define F367TER_ONE_SHOT 0xf2a10010
  1871. #define F367TER_I2C_MOD 0xf2a1000c
  1872. #define F367TER_SPY_HYSTERESIS 0xf2a10003
  1873. /* FSPYDATA */
  1874. #define R367TER_FSPYDATA 0xf2a2
  1875. #define F367TER_SPY_STUFFING 0xf2a20080
  1876. #define F367TER_NOERROR_PKTJITTER 0xf2a20040
  1877. #define F367TER_SPY_CNULLPKT 0xf2a20020
  1878. #define F367TER_SPY_OUTDATA_MODE 0xf2a2001f
  1879. /* FSPYOUT */
  1880. #define R367TER_FSPYOUT 0xf2a3
  1881. #define F367TER_FSPY_DIRECT 0xf2a30080
  1882. #define F367TER_FSPYOUT_6 0xf2a30040
  1883. #define F367TER_SPY_OUTDATA_BUS 0xf2a30038
  1884. #define F367TER_STUFF_MODE 0xf2a30007
  1885. /* FSTATUS */
  1886. #define R367TER_FSTATUS 0xf2a4
  1887. #define F367TER_SPY_ENDSIM 0xf2a40080
  1888. #define F367TER_VALID_SIM 0xf2a40040
  1889. #define F367TER_FOUND_SIGNAL 0xf2a40020
  1890. #define F367TER_DSS_SYNCBYTE 0xf2a40010
  1891. #define F367TER_RESULT_STATE 0xf2a4000f
  1892. /* FGOODPACK */
  1893. #define R367TER_FGOODPACK 0xf2a5
  1894. #define F367TER_FGOOD_PACKET 0xf2a500ff
  1895. /* FPACKCNT */
  1896. #define R367TER_FPACKCNT 0xf2a6
  1897. #define F367TER_FPACKET_COUNTER 0xf2a600ff
  1898. /* FSPYMISC */
  1899. #define R367TER_FSPYMISC 0xf2a7
  1900. #define F367TER_FLABEL_COUNTER 0xf2a700ff
  1901. /* FBERCPT4 */
  1902. #define R367TER_FBERCPT4 0xf2a8
  1903. #define F367TER_FBERMETER_CPT5 0xf2a800ff
  1904. /* FBERCPT3 */
  1905. #define R367TER_FBERCPT3 0xf2a9
  1906. #define F367TER_FBERMETER_CPT4 0xf2a900ff
  1907. /* FBERCPT2 */
  1908. #define R367TER_FBERCPT2 0xf2aa
  1909. #define F367TER_FBERMETER_CPT3 0xf2aa00ff
  1910. /* FBERCPT1 */
  1911. #define R367TER_FBERCPT1 0xf2ab
  1912. #define F367TER_FBERMETER_CPT2 0xf2ab00ff
  1913. /* FBERCPT0 */
  1914. #define R367TER_FBERCPT0 0xf2ac
  1915. #define F367TER_FBERMETER_CPT1 0xf2ac00ff
  1916. /* FBERERR2 */
  1917. #define R367TER_FBERERR2 0xf2ad
  1918. #define F367TER_FBERMETER_ERR_HI 0xf2ad00ff
  1919. /* FBERERR1 */
  1920. #define R367TER_FBERERR1 0xf2ae
  1921. #define F367TER_FBERMETER_ERR_MED 0xf2ae00ff
  1922. /* FBERERR0 */
  1923. #define R367TER_FBERERR0 0xf2af
  1924. #define F367TER_FBERMETER_ERR_LO 0xf2af00ff
  1925. /* FSTATESM */
  1926. #define R367TER_FSTATESM 0xf2b0
  1927. #define F367TER_RSTATE_F 0xf2b00080
  1928. #define F367TER_RSTATE_E 0xf2b00040
  1929. #define F367TER_RSTATE_D 0xf2b00020
  1930. #define F367TER_RSTATE_C 0xf2b00010
  1931. #define F367TER_RSTATE_B 0xf2b00008
  1932. #define F367TER_RSTATE_A 0xf2b00004
  1933. #define F367TER_RSTATE_9 0xf2b00002
  1934. #define F367TER_RSTATE_8 0xf2b00001
  1935. /* FSTATESL */
  1936. #define R367TER_FSTATESL 0xf2b1
  1937. #define F367TER_RSTATE_7 0xf2b10080
  1938. #define F367TER_RSTATE_6 0xf2b10040
  1939. #define F367TER_RSTATE_5 0xf2b10020
  1940. #define F367TER_RSTATE_4 0xf2b10010
  1941. #define F367TER_RSTATE_3 0xf2b10008
  1942. #define F367TER_RSTATE_2 0xf2b10004
  1943. #define F367TER_RSTATE_1 0xf2b10002
  1944. #define F367TER_RSTATE_0 0xf2b10001
  1945. /* FSPYBER */
  1946. #define R367TER_FSPYBER 0xf2b2
  1947. #define F367TER_FSPYBER_7 0xf2b20080
  1948. #define F367TER_FSPYOBS_XORREAD 0xf2b20040
  1949. #define F367TER_FSPYBER_OBSMODE 0xf2b20020
  1950. #define F367TER_FSPYBER_SYNCBYTE 0xf2b20010
  1951. #define F367TER_FSPYBER_UNSYNC 0xf2b20008
  1952. #define F367TER_FSPYBER_CTIME 0xf2b20007
  1953. /* FSPYDISTM */
  1954. #define R367TER_FSPYDISTM 0xf2b3
  1955. #define F367TER_PKTTIME_DISTANCE_HI 0xf2b300ff
  1956. /* FSPYDISTL */
  1957. #define R367TER_FSPYDISTL 0xf2b4
  1958. #define F367TER_PKTTIME_DISTANCE_LO 0xf2b400ff
  1959. /* FSPYOBS7 */
  1960. #define R367TER_FSPYOBS7 0xf2b8
  1961. #define F367TER_FSPYOBS_SPYFAIL 0xf2b80080
  1962. #define F367TER_FSPYOBS_SPYFAIL1 0xf2b80040
  1963. #define F367TER_FSPYOBS_ERROR 0xf2b80020
  1964. #define F367TER_FSPYOBS_STROUT 0xf2b80010
  1965. #define F367TER_FSPYOBS_RESULTSTATE1 0xf2b8000f
  1966. /* FSPYOBS6 */
  1967. #define R367TER_FSPYOBS6 0xf2b9
  1968. #define F367TER_FSPYOBS_RESULTSTATe0 0xf2b900f0
  1969. #define F367TER_FSPYOBS_RESULTSTATEM1 0xf2b9000f
  1970. /* FSPYOBS5 */
  1971. #define R367TER_FSPYOBS5 0xf2ba
  1972. #define F367TER_FSPYOBS_BYTEOFPACKET1 0xf2ba00ff
  1973. /* FSPYOBS4 */
  1974. #define R367TER_FSPYOBS4 0xf2bb
  1975. #define F367TER_FSPYOBS_BYTEVALUE1 0xf2bb00ff
  1976. /* FSPYOBS3 */
  1977. #define R367TER_FSPYOBS3 0xf2bc
  1978. #define F367TER_FSPYOBS_DATA1 0xf2bc00ff
  1979. /* FSPYOBS2 */
  1980. #define R367TER_FSPYOBS2 0xf2bd
  1981. #define F367TER_FSPYOBS_DATa0 0xf2bd00ff
  1982. /* FSPYOBS1 */
  1983. #define R367TER_FSPYOBS1 0xf2be
  1984. #define F367TER_FSPYOBS_DATAM1 0xf2be00ff
  1985. /* FSPYOBS0 */
  1986. #define R367TER_FSPYOBS0 0xf2bf
  1987. #define F367TER_FSPYOBS_DATAM2 0xf2bf00ff
  1988. /* SFDEMAP */
  1989. #define R367TER_SFDEMAP 0xf2c0
  1990. #define F367TER_SFDEMAP_7 0xf2c00080
  1991. #define F367TER_SFEC_K_DIVIDER_VIT 0xf2c0007f
  1992. /* SFERROR */
  1993. #define R367TER_SFERROR 0xf2c1
  1994. #define F367TER_SFEC_REGERR_VIT 0xf2c100ff
  1995. /* SFAVSR */
  1996. #define R367TER_SFAVSR 0xf2c2
  1997. #define F367TER_SFEC_SUMERRORS 0xf2c20080
  1998. #define F367TER_SERROR_MAXMODE 0xf2c20040
  1999. #define F367TER_SN_SFEC 0xf2c20030
  2000. #define F367TER_KDIV_MODE_SFEC 0xf2c2000c
  2001. #define F367TER_SFAVSR_1 0xf2c20002
  2002. #define F367TER_SFAVSR_0 0xf2c20001
  2003. /* SFECSTATUS */
  2004. #define R367TER_SFECSTATUS 0xf2c3
  2005. #define F367TER_SFEC_ON 0xf2c30080
  2006. #define F367TER_SFSTATUS_6 0xf2c30040
  2007. #define F367TER_SFSTATUS_5 0xf2c30020
  2008. #define F367TER_SFSTATUS_4 0xf2c30010
  2009. #define F367TER_LOCKEDSFEC 0xf2c30008
  2010. #define F367TER_SFEC_DELOCK 0xf2c30004
  2011. #define F367TER_SFEC_DEMODSEL1 0xf2c30002
  2012. #define F367TER_SFEC_OVFON 0xf2c30001
  2013. /* SFKDIV12 */
  2014. #define R367TER_SFKDIV12 0xf2c4
  2015. #define F367TER_SFECKDIV12_MAN 0xf2c40080
  2016. #define F367TER_SFEC_K_DIVIDER_12 0xf2c4007f
  2017. /* SFKDIV23 */
  2018. #define R367TER_SFKDIV23 0xf2c5
  2019. #define F367TER_SFECKDIV23_MAN 0xf2c50080
  2020. #define F367TER_SFEC_K_DIVIDER_23 0xf2c5007f
  2021. /* SFKDIV34 */
  2022. #define R367TER_SFKDIV34 0xf2c6
  2023. #define F367TER_SFECKDIV34_MAN 0xf2c60080
  2024. #define F367TER_SFEC_K_DIVIDER_34 0xf2c6007f
  2025. /* SFKDIV56 */
  2026. #define R367TER_SFKDIV56 0xf2c7
  2027. #define F367TER_SFECKDIV56_MAN 0xf2c70080
  2028. #define F367TER_SFEC_K_DIVIDER_56 0xf2c7007f
  2029. /* SFKDIV67 */
  2030. #define R367TER_SFKDIV67 0xf2c8
  2031. #define F367TER_SFECKDIV67_MAN 0xf2c80080
  2032. #define F367TER_SFEC_K_DIVIDER_67 0xf2c8007f
  2033. /* SFKDIV78 */
  2034. #define R367TER_SFKDIV78 0xf2c9
  2035. #define F367TER_SFECKDIV78_MAN 0xf2c90080
  2036. #define F367TER_SFEC_K_DIVIDER_78 0xf2c9007f
  2037. /* SFDILSTKM */
  2038. #define R367TER_SFDILSTKM 0xf2ca
  2039. #define F367TER_SFEC_PACKCPT 0xf2ca00e0
  2040. #define F367TER_SFEC_DILSTK_HI 0xf2ca001f
  2041. /* SFDILSTKL */
  2042. #define R367TER_SFDILSTKL 0xf2cb
  2043. #define F367TER_SFEC_DILSTK_LO 0xf2cb00ff
  2044. /* SFSTATUS */
  2045. #define R367TER_SFSTATUS 0xf2cc
  2046. #define F367TER_SFEC_LINEOK 0xf2cc0080
  2047. #define F367TER_SFEC_ERROR 0xf2cc0040
  2048. #define F367TER_SFEC_DATA7 0xf2cc0020
  2049. #define F367TER_SFEC_OVERFLOW 0xf2cc0010
  2050. #define F367TER_SFEC_DEMODSEL2 0xf2cc0008
  2051. #define F367TER_SFEC_NOSYNC 0xf2cc0004
  2052. #define F367TER_SFEC_UNREGULA 0xf2cc0002
  2053. #define F367TER_SFEC_READY 0xf2cc0001
  2054. /* SFDLYH */
  2055. #define R367TER_SFDLYH 0xf2cd
  2056. #define F367TER_SFEC_TSTIMEVALID 0xf2cd0080
  2057. #define F367TER_SFEC_SPEEDUP 0xf2cd0040
  2058. #define F367TER_SFEC_STOP 0xf2cd0020
  2059. #define F367TER_SFEC_REGULATED 0xf2cd0010
  2060. #define F367TER_SFEC_REALSYMBOFFSET 0xf2cd000f
  2061. /* SFDLYM */
  2062. #define R367TER_SFDLYM 0xf2ce
  2063. #define F367TER_SFEC_REALSYMBOFFSET_HI 0xf2ce00ff
  2064. /* SFDLYL */
  2065. #define R367TER_SFDLYL 0xf2cf
  2066. #define F367TER_SFEC_REALSYMBOFFSET_LO 0xf2cf00ff
  2067. /* SFDLYSETH */
  2068. #define R367TER_SFDLYSETH 0xf2d0
  2069. #define F367TER_SFEC_OFFSET 0xf2d000e0
  2070. #define F367TER_SFECDLYSETH_4 0xf2d00010
  2071. #define F367TER_RST_SFEC 0xf2d00008
  2072. #define F367TER_SFECDLYSETH_2 0xf2d00004
  2073. #define F367TER_SFEC_DISABLE 0xf2d00002
  2074. #define F367TER_SFEC_UNREGUL 0xf2d00001
  2075. /* SFDLYSETM */
  2076. #define R367TER_SFDLYSETM 0xf2d1
  2077. #define F367TER_SFECDLYSETM_7 0xf2d10080
  2078. #define F367TER_SFEC_SYMBOFFSET_HI 0xf2d1007f
  2079. /* SFDLYSETL */
  2080. #define R367TER_SFDLYSETL 0xf2d2
  2081. #define F367TER_SFEC_SYMBOFFSET_LO 0xf2d200ff
  2082. /* SFOBSCFG */
  2083. #define R367TER_SFOBSCFG 0xf2d3
  2084. #define F367TER_SFEC_OBSCFG 0xf2d300ff
  2085. /* SFOBSM */
  2086. #define R367TER_SFOBSM 0xf2d4
  2087. #define F367TER_SFEC_OBSDATA_HI 0xf2d400ff
  2088. /* SFOBSL */
  2089. #define R367TER_SFOBSL 0xf2d5
  2090. #define F367TER_SFEC_OBSDATA_LO 0xf2d500ff
  2091. /* SFECINFO */
  2092. #define R367TER_SFECINFO 0xf2d6
  2093. #define F367TER_SFECINFO_7 0xf2d60080
  2094. #define F367TER_SFEC_SYNCDLSB 0xf2d60070
  2095. #define F367TER_SFCE_S1cPHASE 0xf2d6000f
  2096. /* SFERRCTRL */
  2097. #define R367TER_SFERRCTRL 0xf2d8
  2098. #define F367TER_SFEC_ERR_SOURCE 0xf2d800f0
  2099. #define F367TER_SFERRCTRL_3 0xf2d80008
  2100. #define F367TER_SFEC_NUM_EVENT 0xf2d80007
  2101. /* SFERRCNTH */
  2102. #define R367TER_SFERRCNTH 0xf2d9
  2103. #define F367TER_SFERRC_OLDVALUE 0xf2d90080
  2104. #define F367TER_SFEC_ERR_CNT 0xf2d9007f
  2105. /* SFERRCNTM */
  2106. #define R367TER_SFERRCNTM 0xf2da
  2107. #define F367TER_SFEC_ERR_CNT_HI 0xf2da00ff
  2108. /* SFERRCNTL */
  2109. #define R367TER_SFERRCNTL 0xf2db
  2110. #define F367TER_SFEC_ERR_CNT_LO 0xf2db00ff
  2111. /* SYMBRATEM */
  2112. #define R367TER_SYMBRATEM 0xf2e0
  2113. #define F367TER_DEFGEN_SYMBRATE_HI 0xf2e000ff
  2114. /* SYMBRATEL */
  2115. #define R367TER_SYMBRATEL 0xf2e1
  2116. #define F367TER_DEFGEN_SYMBRATE_LO 0xf2e100ff
  2117. /* SYMBSTATUS */
  2118. #define R367TER_SYMBSTATUS 0xf2e2
  2119. #define F367TER_SYMBDLINE2_OFF 0xf2e20080
  2120. #define F367TER_SDDL_REINIT1 0xf2e20040
  2121. #define F367TER_SDD_REINIT1 0xf2e20020
  2122. #define F367TER_TOKENID_ERROR 0xf2e20010
  2123. #define F367TER_SYMBRATE_OVERFLOW 0xf2e20008
  2124. #define F367TER_SYMBRATE_UNDERFLOW 0xf2e20004
  2125. #define F367TER_TOKENID_RSTEVENT 0xf2e20002
  2126. #define F367TER_TOKENID_RESET1 0xf2e20001
  2127. /* SYMBCFG */
  2128. #define R367TER_SYMBCFG 0xf2e3
  2129. #define F367TER_SYMBCFG_7 0xf2e30080
  2130. #define F367TER_SYMBCFG_6 0xf2e30040
  2131. #define F367TER_SYMBCFG_5 0xf2e30020
  2132. #define F367TER_SYMBCFG_4 0xf2e30010
  2133. #define F367TER_SYMRATE_FSPEED 0xf2e3000c
  2134. #define F367TER_SYMRATE_SSPEED 0xf2e30003
  2135. /* SYMBFIFOM */
  2136. #define R367TER_SYMBFIFOM 0xf2e4
  2137. #define F367TER_SYMBFIFOM_7 0xf2e40080
  2138. #define F367TER_SYMBFIFOM_6 0xf2e40040
  2139. #define F367TER_DEFGEN_SYMFIFO_HI 0xf2e4003f
  2140. /* SYMBFIFOL */
  2141. #define R367TER_SYMBFIFOL 0xf2e5
  2142. #define F367TER_DEFGEN_SYMFIFO_LO 0xf2e500ff
  2143. /* SYMBOFFSM */
  2144. #define R367TER_SYMBOFFSM 0xf2e6
  2145. #define F367TER_TOKENID_RESET2 0xf2e60080
  2146. #define F367TER_SDDL_REINIT2 0xf2e60040
  2147. #define F367TER_SDD_REINIT2 0xf2e60020
  2148. #define F367TER_SYMBOFFSM_4 0xf2e60010
  2149. #define F367TER_SYMBOFFSM_3 0xf2e60008
  2150. #define F367TER_DEFGEN_SYMBOFFSET_HI 0xf2e60007
  2151. /* SYMBOFFSL */
  2152. #define R367TER_SYMBOFFSL 0xf2e7
  2153. #define F367TER_DEFGEN_SYMBOFFSET_LO 0xf2e700ff
  2154. /* DEBUG_LT4 */
  2155. #define R367TER_DEBUG_LT4 0xf400
  2156. #define F367TER_F_DEBUG_LT4 0xf40000ff
  2157. /* DEBUG_LT5 */
  2158. #define R367TER_DEBUG_LT5 0xf401
  2159. #define F367TER_F_DEBUG_LT5 0xf40100ff
  2160. /* DEBUG_LT6 */
  2161. #define R367TER_DEBUG_LT6 0xf402
  2162. #define F367TER_F_DEBUG_LT6 0xf40200ff
  2163. /* DEBUG_LT7 */
  2164. #define R367TER_DEBUG_LT7 0xf403
  2165. #define F367TER_F_DEBUG_LT7 0xf40300ff
  2166. /* DEBUG_LT8 */
  2167. #define R367TER_DEBUG_LT8 0xf404
  2168. #define F367TER_F_DEBUG_LT8 0xf40400ff
  2169. /* DEBUG_LT9 */
  2170. #define R367TER_DEBUG_LT9 0xf405
  2171. #define F367TER_F_DEBUG_LT9 0xf40500ff
  2172. #define STV0367TER_NBREGS 445
  2173. /* ID */
  2174. #define R367CAB_ID 0xf000
  2175. #define F367CAB_IDENTIFICATIONREGISTER 0xf00000ff
  2176. /* I2CRPT */
  2177. #define R367CAB_I2CRPT 0xf001
  2178. #define F367CAB_I2CT_ON 0xf0010080
  2179. #define F367CAB_ENARPT_LEVEL 0xf0010070
  2180. #define F367CAB_SCLT_DELAY 0xf0010008
  2181. #define F367CAB_SCLT_NOD 0xf0010004
  2182. #define F367CAB_STOP_ENABLE 0xf0010002
  2183. #define F367CAB_SDAT_NOD 0xf0010001
  2184. /* TOPCTRL */
  2185. #define R367CAB_TOPCTRL 0xf002
  2186. #define F367CAB_STDBY 0xf0020080
  2187. #define F367CAB_STDBY_CORE 0xf0020020
  2188. #define F367CAB_QAM_COFDM 0xf0020010
  2189. #define F367CAB_TS_DIS 0xf0020008
  2190. #define F367CAB_DIR_CLK_216 0xf0020004
  2191. /* IOCFG0 */
  2192. #define R367CAB_IOCFG0 0xf003
  2193. #define F367CAB_OP0_SD 0xf0030080
  2194. #define F367CAB_OP0_VAL 0xf0030040
  2195. #define F367CAB_OP0_OD 0xf0030020
  2196. #define F367CAB_OP0_INV 0xf0030010
  2197. #define F367CAB_OP0_DACVALUE_HI 0xf003000f
  2198. /* DAc0R */
  2199. #define R367CAB_DAC0R 0xf004
  2200. #define F367CAB_OP0_DACVALUE_LO 0xf00400ff
  2201. /* IOCFG1 */
  2202. #define R367CAB_IOCFG1 0xf005
  2203. #define F367CAB_IP0 0xf0050040
  2204. #define F367CAB_OP1_OD 0xf0050020
  2205. #define F367CAB_OP1_INV 0xf0050010
  2206. #define F367CAB_OP1_DACVALUE_HI 0xf005000f
  2207. /* DAC1R */
  2208. #define R367CAB_DAC1R 0xf006
  2209. #define F367CAB_OP1_DACVALUE_LO 0xf00600ff
  2210. /* IOCFG2 */
  2211. #define R367CAB_IOCFG2 0xf007
  2212. #define F367CAB_OP2_LOCK_CONF 0xf00700e0
  2213. #define F367CAB_OP2_OD 0xf0070010
  2214. #define F367CAB_OP2_VAL 0xf0070008
  2215. #define F367CAB_OP1_LOCK_CONF 0xf0070007
  2216. /* SDFR */
  2217. #define R367CAB_SDFR 0xf008
  2218. #define F367CAB_OP0_FREQ 0xf00800f0
  2219. #define F367CAB_OP1_FREQ 0xf008000f
  2220. /* AUX_CLK */
  2221. #define R367CAB_AUX_CLK 0xf00a
  2222. #define F367CAB_AUXFEC_CTL 0xf00a00c0
  2223. #define F367CAB_DIS_CKX4 0xf00a0020
  2224. #define F367CAB_CKSEL 0xf00a0018
  2225. #define F367CAB_CKDIV_PROG 0xf00a0006
  2226. #define F367CAB_AUXCLK_ENA 0xf00a0001
  2227. /* FREESYS1 */
  2228. #define R367CAB_FREESYS1 0xf00b
  2229. #define F367CAB_FREESYS_1 0xf00b00ff
  2230. /* FREESYS2 */
  2231. #define R367CAB_FREESYS2 0xf00c
  2232. #define F367CAB_FREESYS_2 0xf00c00ff
  2233. /* FREESYS3 */
  2234. #define R367CAB_FREESYS3 0xf00d
  2235. #define F367CAB_FREESYS_3 0xf00d00ff
  2236. /* GPIO_CFG */
  2237. #define R367CAB_GPIO_CFG 0xf00e
  2238. #define F367CAB_GPIO7_OD 0xf00e0080
  2239. #define F367CAB_GPIO7_CFG 0xf00e0040
  2240. #define F367CAB_GPIO6_OD 0xf00e0020
  2241. #define F367CAB_GPIO6_CFG 0xf00e0010
  2242. #define F367CAB_GPIO5_OD 0xf00e0008
  2243. #define F367CAB_GPIO5_CFG 0xf00e0004
  2244. #define F367CAB_GPIO4_OD 0xf00e0002
  2245. #define F367CAB_GPIO4_CFG 0xf00e0001
  2246. /* GPIO_CMD */
  2247. #define R367CAB_GPIO_CMD 0xf00f
  2248. #define F367CAB_GPIO7_VAL 0xf00f0008
  2249. #define F367CAB_GPIO6_VAL 0xf00f0004
  2250. #define F367CAB_GPIO5_VAL 0xf00f0002
  2251. #define F367CAB_GPIO4_VAL 0xf00f0001
  2252. /* TSTRES */
  2253. #define R367CAB_TSTRES 0xf0c0
  2254. #define F367CAB_FRES_DISPLAY 0xf0c00080
  2255. #define F367CAB_FRES_FIFO_AD 0xf0c00020
  2256. #define F367CAB_FRESRS 0xf0c00010
  2257. #define F367CAB_FRESACS 0xf0c00008
  2258. #define F367CAB_FRESFEC 0xf0c00004
  2259. #define F367CAB_FRES_PRIF 0xf0c00002
  2260. #define F367CAB_FRESCORE 0xf0c00001
  2261. /* ANACTRL */
  2262. #define R367CAB_ANACTRL 0xf0c1
  2263. #define F367CAB_BYPASS_XTAL 0xf0c10040
  2264. #define F367CAB_BYPASS_PLLXN 0xf0c1000c
  2265. #define F367CAB_DIS_PAD_OSC 0xf0c10002
  2266. #define F367CAB_STDBY_PLLXN 0xf0c10001
  2267. /* TSTBUS */
  2268. #define R367CAB_TSTBUS 0xf0c2
  2269. #define F367CAB_TS_BYTE_CLK_INV 0xf0c20080
  2270. #define F367CAB_CFG_IP 0xf0c20070
  2271. #define F367CAB_CFG_TST 0xf0c2000f
  2272. /* RF_AGC1 */
  2273. #define R367CAB_RF_AGC1 0xf0d4
  2274. #define F367CAB_RF_AGC1_LEVEL_HI 0xf0d400ff
  2275. /* RF_AGC2 */
  2276. #define R367CAB_RF_AGC2 0xf0d5
  2277. #define F367CAB_REF_ADGP 0xf0d50080
  2278. #define F367CAB_STDBY_ADCGP 0xf0d50020
  2279. #define F367CAB_RF_AGC1_LEVEL_LO 0xf0d50003
  2280. /* ANADIGCTRL */
  2281. #define R367CAB_ANADIGCTRL 0xf0d7
  2282. #define F367CAB_SEL_CLKDEM 0xf0d70020
  2283. #define F367CAB_EN_BUFFER_Q 0xf0d70010
  2284. #define F367CAB_EN_BUFFER_I 0xf0d70008
  2285. #define F367CAB_ADC_RIS_EGDE 0xf0d70004
  2286. #define F367CAB_SGN_ADC 0xf0d70002
  2287. #define F367CAB_SEL_AD12_SYNC 0xf0d70001
  2288. /* PLLMDIV */
  2289. #define R367CAB_PLLMDIV 0xf0d8
  2290. #define F367CAB_PLL_MDIV 0xf0d800ff
  2291. /* PLLNDIV */
  2292. #define R367CAB_PLLNDIV 0xf0d9
  2293. #define F367CAB_PLL_NDIV 0xf0d900ff
  2294. /* PLLSETUP */
  2295. #define R367CAB_PLLSETUP 0xf0da
  2296. #define F367CAB_PLL_PDIV 0xf0da0070
  2297. #define F367CAB_PLL_KDIV 0xf0da000f
  2298. /* DUAL_AD12 */
  2299. #define R367CAB_DUAL_AD12 0xf0db
  2300. #define F367CAB_FS20M 0xf0db0020
  2301. #define F367CAB_FS50M 0xf0db0010
  2302. #define F367CAB_INMODe0 0xf0db0008
  2303. #define F367CAB_POFFQ 0xf0db0004
  2304. #define F367CAB_POFFI 0xf0db0002
  2305. #define F367CAB_INMODE1 0xf0db0001
  2306. /* TSTBIST */
  2307. #define R367CAB_TSTBIST 0xf0dc
  2308. #define F367CAB_TST_BYP_CLK 0xf0dc0080
  2309. #define F367CAB_TST_GCLKENA_STD 0xf0dc0040
  2310. #define F367CAB_TST_GCLKENA 0xf0dc0020
  2311. #define F367CAB_TST_MEMBIST 0xf0dc001f
  2312. /* CTRL_1 */
  2313. #define R367CAB_CTRL_1 0xf402
  2314. #define F367CAB_SOFT_RST 0xf4020080
  2315. #define F367CAB_EQU_RST 0xf4020008
  2316. #define F367CAB_CRL_RST 0xf4020004
  2317. #define F367CAB_TRL_RST 0xf4020002
  2318. #define F367CAB_AGC_RST 0xf4020001
  2319. /* CTRL_2 */
  2320. #define R367CAB_CTRL_2 0xf403
  2321. #define F367CAB_DEINT_RST 0xf4030008
  2322. #define F367CAB_RS_RST 0xf4030004
  2323. /* IT_STATUS1 */
  2324. #define R367CAB_IT_STATUS1 0xf408
  2325. #define F367CAB_SWEEP_OUT 0xf4080080
  2326. #define F367CAB_FSM_CRL 0xf4080040
  2327. #define F367CAB_CRL_LOCK 0xf4080020
  2328. #define F367CAB_MFSM 0xf4080010
  2329. #define F367CAB_TRL_LOCK 0xf4080008
  2330. #define F367CAB_TRL_AGC_LIMIT 0xf4080004
  2331. #define F367CAB_ADJ_AGC_LOCK 0xf4080002
  2332. #define F367CAB_AGC_QAM_LOCK 0xf4080001
  2333. /* IT_STATUS2 */
  2334. #define R367CAB_IT_STATUS2 0xf409
  2335. #define F367CAB_TSMF_CNT 0xf4090080
  2336. #define F367CAB_TSMF_EOF 0xf4090040
  2337. #define F367CAB_TSMF_RDY 0xf4090020
  2338. #define F367CAB_FEC_NOCORR 0xf4090010
  2339. #define F367CAB_SYNCSTATE 0xf4090008
  2340. #define F367CAB_DEINT_LOCK 0xf4090004
  2341. #define F367CAB_FADDING_FRZ 0xf4090002
  2342. #define F367CAB_TAPMON_ALARM 0xf4090001
  2343. /* IT_EN1 */
  2344. #define R367CAB_IT_EN1 0xf40a
  2345. #define F367CAB_SWEEP_OUTE 0xf40a0080
  2346. #define F367CAB_FSM_CRLE 0xf40a0040
  2347. #define F367CAB_CRL_LOCKE 0xf40a0020
  2348. #define F367CAB_MFSME 0xf40a0010
  2349. #define F367CAB_TRL_LOCKE 0xf40a0008
  2350. #define F367CAB_TRL_AGC_LIMITE 0xf40a0004
  2351. #define F367CAB_ADJ_AGC_LOCKE 0xf40a0002
  2352. #define F367CAB_AGC_LOCKE 0xf40a0001
  2353. /* IT_EN2 */
  2354. #define R367CAB_IT_EN2 0xf40b
  2355. #define F367CAB_TSMF_CNTE 0xf40b0080
  2356. #define F367CAB_TSMF_EOFE 0xf40b0040
  2357. #define F367CAB_TSMF_RDYE 0xf40b0020
  2358. #define F367CAB_FEC_NOCORRE 0xf40b0010
  2359. #define F367CAB_SYNCSTATEE 0xf40b0008
  2360. #define F367CAB_DEINT_LOCKE 0xf40b0004
  2361. #define F367CAB_FADDING_FRZE 0xf40b0002
  2362. #define F367CAB_TAPMON_ALARME 0xf40b0001
  2363. /* CTRL_STATUS */
  2364. #define R367CAB_CTRL_STATUS 0xf40c
  2365. #define F367CAB_QAMFEC_LOCK 0xf40c0004
  2366. #define F367CAB_TSMF_LOCK 0xf40c0002
  2367. #define F367CAB_TSMF_ERROR 0xf40c0001
  2368. /* TEST_CTL */
  2369. #define R367CAB_TEST_CTL 0xf40f
  2370. #define F367CAB_TST_BLK_SEL 0xf40f0060
  2371. #define F367CAB_TST_BUS_SEL 0xf40f001f
  2372. /* AGC_CTL */
  2373. #define R367CAB_AGC_CTL 0xf410
  2374. #define F367CAB_AGC_LCK_TH 0xf41000f0
  2375. #define F367CAB_AGC_ACCUMRSTSEL 0xf4100007
  2376. /* AGC_IF_CFG */
  2377. #define R367CAB_AGC_IF_CFG 0xf411
  2378. #define F367CAB_AGC_IF_BWSEL 0xf41100f0
  2379. #define F367CAB_AGC_IF_FREEZE 0xf4110002
  2380. /* AGC_RF_CFG */
  2381. #define R367CAB_AGC_RF_CFG 0xf412
  2382. #define F367CAB_AGC_RF_BWSEL 0xf4120070
  2383. #define F367CAB_AGC_RF_FREEZE 0xf4120002
  2384. /* AGC_PWM_CFG */
  2385. #define R367CAB_AGC_PWM_CFG 0xf413
  2386. #define F367CAB_AGC_RF_PWM_TST 0xf4130080
  2387. #define F367CAB_AGC_RF_PWM_INV 0xf4130040
  2388. #define F367CAB_AGC_IF_PWM_TST 0xf4130008
  2389. #define F367CAB_AGC_IF_PWM_INV 0xf4130004
  2390. #define F367CAB_AGC_PWM_CLKDIV 0xf4130003
  2391. /* AGC_PWR_REF_L */
  2392. #define R367CAB_AGC_PWR_REF_L 0xf414
  2393. #define F367CAB_AGC_PWRREF_LO 0xf41400ff
  2394. /* AGC_PWR_REF_H */
  2395. #define R367CAB_AGC_PWR_REF_H 0xf415
  2396. #define F367CAB_AGC_PWRREF_HI 0xf4150003
  2397. /* AGC_RF_TH_L */
  2398. #define R367CAB_AGC_RF_TH_L 0xf416
  2399. #define F367CAB_AGC_RF_TH_LO 0xf41600ff
  2400. /* AGC_RF_TH_H */
  2401. #define R367CAB_AGC_RF_TH_H 0xf417
  2402. #define F367CAB_AGC_RF_TH_HI 0xf417000f
  2403. /* AGC_IF_LTH_L */
  2404. #define R367CAB_AGC_IF_LTH_L 0xf418
  2405. #define F367CAB_AGC_IF_THLO_LO 0xf41800ff
  2406. /* AGC_IF_LTH_H */
  2407. #define R367CAB_AGC_IF_LTH_H 0xf419
  2408. #define F367CAB_AGC_IF_THLO_HI 0xf419000f
  2409. /* AGC_IF_HTH_L */
  2410. #define R367CAB_AGC_IF_HTH_L 0xf41a
  2411. #define F367CAB_AGC_IF_THHI_LO 0xf41a00ff
  2412. /* AGC_IF_HTH_H */
  2413. #define R367CAB_AGC_IF_HTH_H 0xf41b
  2414. #define F367CAB_AGC_IF_THHI_HI 0xf41b000f
  2415. /* AGC_PWR_RD_L */
  2416. #define R367CAB_AGC_PWR_RD_L 0xf41c
  2417. #define F367CAB_AGC_PWR_WORD_LO 0xf41c00ff
  2418. /* AGC_PWR_RD_M */
  2419. #define R367CAB_AGC_PWR_RD_M 0xf41d
  2420. #define F367CAB_AGC_PWR_WORD_ME 0xf41d00ff
  2421. /* AGC_PWR_RD_H */
  2422. #define R367CAB_AGC_PWR_RD_H 0xf41e
  2423. #define F367CAB_AGC_PWR_WORD_HI 0xf41e0003
  2424. /* AGC_PWM_IFCMD_L */
  2425. #define R367CAB_AGC_PWM_IFCMD_L 0xf420
  2426. #define F367CAB_AGC_IF_PWMCMD_LO 0xf42000ff
  2427. /* AGC_PWM_IFCMD_H */
  2428. #define R367CAB_AGC_PWM_IFCMD_H 0xf421
  2429. #define F367CAB_AGC_IF_PWMCMD_HI 0xf421000f
  2430. /* AGC_PWM_RFCMD_L */
  2431. #define R367CAB_AGC_PWM_RFCMD_L 0xf422
  2432. #define F367CAB_AGC_RF_PWMCMD_LO 0xf42200ff
  2433. /* AGC_PWM_RFCMD_H */
  2434. #define R367CAB_AGC_PWM_RFCMD_H 0xf423
  2435. #define F367CAB_AGC_RF_PWMCMD_HI 0xf423000f
  2436. /* IQDEM_CFG */
  2437. #define R367CAB_IQDEM_CFG 0xf424
  2438. #define F367CAB_IQDEM_CLK_SEL 0xf4240004
  2439. #define F367CAB_IQDEM_INVIQ 0xf4240002
  2440. #define F367CAB_IQDEM_A2dTYPE 0xf4240001
  2441. /* MIX_NCO_LL */
  2442. #define R367CAB_MIX_NCO_LL 0xf425
  2443. #define F367CAB_MIX_NCO_INC_LL 0xf42500ff
  2444. /* MIX_NCO_HL */
  2445. #define R367CAB_MIX_NCO_HL 0xf426
  2446. #define F367CAB_MIX_NCO_INC_HL 0xf42600ff
  2447. /* MIX_NCO_HH */
  2448. #define R367CAB_MIX_NCO_HH 0xf427
  2449. #define F367CAB_MIX_NCO_INVCNST 0xf4270080
  2450. #define F367CAB_MIX_NCO_INC_HH 0xf427007f
  2451. /* SRC_NCO_LL */
  2452. #define R367CAB_SRC_NCO_LL 0xf428
  2453. #define F367CAB_SRC_NCO_INC_LL 0xf42800ff
  2454. /* SRC_NCO_LH */
  2455. #define R367CAB_SRC_NCO_LH 0xf429
  2456. #define F367CAB_SRC_NCO_INC_LH 0xf42900ff
  2457. /* SRC_NCO_HL */
  2458. #define R367CAB_SRC_NCO_HL 0xf42a
  2459. #define F367CAB_SRC_NCO_INC_HL 0xf42a00ff
  2460. /* SRC_NCO_HH */
  2461. #define R367CAB_SRC_NCO_HH 0xf42b
  2462. #define F367CAB_SRC_NCO_INC_HH 0xf42b007f
  2463. /* IQDEM_GAIN_SRC_L */
  2464. #define R367CAB_IQDEM_GAIN_SRC_L 0xf42c
  2465. #define F367CAB_GAIN_SRC_LO 0xf42c00ff
  2466. /* IQDEM_GAIN_SRC_H */
  2467. #define R367CAB_IQDEM_GAIN_SRC_H 0xf42d
  2468. #define F367CAB_GAIN_SRC_HI 0xf42d0003
  2469. /* IQDEM_DCRM_CFG_LL */
  2470. #define R367CAB_IQDEM_DCRM_CFG_LL 0xf430
  2471. #define F367CAB_DCRM0_DCIN_L 0xf43000ff
  2472. /* IQDEM_DCRM_CFG_LH */
  2473. #define R367CAB_IQDEM_DCRM_CFG_LH 0xf431
  2474. #define F367CAB_DCRM1_I_DCIN_L 0xf43100fc
  2475. #define F367CAB_DCRM0_DCIN_H 0xf4310003
  2476. /* IQDEM_DCRM_CFG_HL */
  2477. #define R367CAB_IQDEM_DCRM_CFG_HL 0xf432
  2478. #define F367CAB_DCRM1_Q_DCIN_L 0xf43200f0
  2479. #define F367CAB_DCRM1_I_DCIN_H 0xf432000f
  2480. /* IQDEM_DCRM_CFG_HH */
  2481. #define R367CAB_IQDEM_DCRM_CFG_HH 0xf433
  2482. #define F367CAB_DCRM1_FRZ 0xf4330080
  2483. #define F367CAB_DCRM0_FRZ 0xf4330040
  2484. #define F367CAB_DCRM1_Q_DCIN_H 0xf433003f
  2485. /* IQDEM_ADJ_COEFf0 */
  2486. #define R367CAB_IQDEM_ADJ_COEFF0 0xf434
  2487. #define F367CAB_ADJIIR_COEFF10_L 0xf43400ff
  2488. /* IQDEM_ADJ_COEFF1 */
  2489. #define R367CAB_IQDEM_ADJ_COEFF1 0xf435
  2490. #define F367CAB_ADJIIR_COEFF11_L 0xf43500fc
  2491. #define F367CAB_ADJIIR_COEFF10_H 0xf4350003
  2492. /* IQDEM_ADJ_COEFF2 */
  2493. #define R367CAB_IQDEM_ADJ_COEFF2 0xf436
  2494. #define F367CAB_ADJIIR_COEFF12_L 0xf43600f0
  2495. #define F367CAB_ADJIIR_COEFF11_H 0xf436000f
  2496. /* IQDEM_ADJ_COEFF3 */
  2497. #define R367CAB_IQDEM_ADJ_COEFF3 0xf437
  2498. #define F367CAB_ADJIIR_COEFF20_L 0xf43700c0
  2499. #define F367CAB_ADJIIR_COEFF12_H 0xf437003f
  2500. /* IQDEM_ADJ_COEFF4 */
  2501. #define R367CAB_IQDEM_ADJ_COEFF4 0xf438
  2502. #define F367CAB_ADJIIR_COEFF20_H 0xf43800ff
  2503. /* IQDEM_ADJ_COEFF5 */
  2504. #define R367CAB_IQDEM_ADJ_COEFF5 0xf439
  2505. #define F367CAB_ADJIIR_COEFF21_L 0xf43900ff
  2506. /* IQDEM_ADJ_COEFF6 */
  2507. #define R367CAB_IQDEM_ADJ_COEFF6 0xf43a
  2508. #define F367CAB_ADJIIR_COEFF22_L 0xf43a00fc
  2509. #define F367CAB_ADJIIR_COEFF21_H 0xf43a0003
  2510. /* IQDEM_ADJ_COEFF7 */
  2511. #define R367CAB_IQDEM_ADJ_COEFF7 0xf43b
  2512. #define F367CAB_ADJIIR_COEFF22_H 0xf43b000f
  2513. /* IQDEM_ADJ_EN */
  2514. #define R367CAB_IQDEM_ADJ_EN 0xf43c
  2515. #define F367CAB_ALLPASSFILT_EN 0xf43c0008
  2516. #define F367CAB_ADJ_AGC_EN 0xf43c0004
  2517. #define F367CAB_ADJ_COEFF_FRZ 0xf43c0002
  2518. #define F367CAB_ADJ_EN 0xf43c0001
  2519. /* IQDEM_ADJ_AGC_REF */
  2520. #define R367CAB_IQDEM_ADJ_AGC_REF 0xf43d
  2521. #define F367CAB_ADJ_AGC_REF 0xf43d00ff
  2522. /* ALLPASSFILT1 */
  2523. #define R367CAB_ALLPASSFILT1 0xf440
  2524. #define F367CAB_ALLPASSFILT_COEFF1_LO 0xf44000ff
  2525. /* ALLPASSFILT2 */
  2526. #define R367CAB_ALLPASSFILT2 0xf441
  2527. #define F367CAB_ALLPASSFILT_COEFF1_ME 0xf44100ff
  2528. /* ALLPASSFILT3 */
  2529. #define R367CAB_ALLPASSFILT3 0xf442
  2530. #define F367CAB_ALLPASSFILT_COEFF2_LO 0xf44200c0
  2531. #define F367CAB_ALLPASSFILT_COEFF1_HI 0xf442003f
  2532. /* ALLPASSFILT4 */
  2533. #define R367CAB_ALLPASSFILT4 0xf443
  2534. #define F367CAB_ALLPASSFILT_COEFF2_MEL 0xf44300ff
  2535. /* ALLPASSFILT5 */
  2536. #define R367CAB_ALLPASSFILT5 0xf444
  2537. #define F367CAB_ALLPASSFILT_COEFF2_MEH 0xf44400ff
  2538. /* ALLPASSFILT6 */
  2539. #define R367CAB_ALLPASSFILT6 0xf445
  2540. #define F367CAB_ALLPASSFILT_COEFF3_LO 0xf44500f0
  2541. #define F367CAB_ALLPASSFILT_COEFF2_HI 0xf445000f
  2542. /* ALLPASSFILT7 */
  2543. #define R367CAB_ALLPASSFILT7 0xf446
  2544. #define F367CAB_ALLPASSFILT_COEFF3_MEL 0xf44600ff
  2545. /* ALLPASSFILT8 */
  2546. #define R367CAB_ALLPASSFILT8 0xf447
  2547. #define F367CAB_ALLPASSFILT_COEFF3_MEH 0xf44700ff
  2548. /* ALLPASSFILT9 */
  2549. #define R367CAB_ALLPASSFILT9 0xf448
  2550. #define F367CAB_ALLPASSFILT_COEFF4_LO 0xf44800fc
  2551. #define F367CAB_ALLPASSFILT_COEFF3_HI 0xf4480003
  2552. /* ALLPASSFILT10 */
  2553. #define R367CAB_ALLPASSFILT10 0xf449
  2554. #define F367CAB_ALLPASSFILT_COEFF4_ME 0xf44900ff
  2555. /* ALLPASSFILT11 */
  2556. #define R367CAB_ALLPASSFILT11 0xf44a
  2557. #define F367CAB_ALLPASSFILT_COEFF4_HI 0xf44a00ff
  2558. /* TRL_AGC_CFG */
  2559. #define R367CAB_TRL_AGC_CFG 0xf450
  2560. #define F367CAB_TRL_AGC_FREEZE 0xf4500080
  2561. #define F367CAB_TRL_AGC_REF 0xf450007f
  2562. /* TRL_LPF_CFG */
  2563. #define R367CAB_TRL_LPF_CFG 0xf454
  2564. #define F367CAB_NYQPOINT_INV 0xf4540040
  2565. #define F367CAB_TRL_SHIFT 0xf4540030
  2566. #define F367CAB_NYQ_COEFF_SEL 0xf454000c
  2567. #define F367CAB_TRL_LPF_FREEZE 0xf4540002
  2568. #define F367CAB_TRL_LPF_CRT 0xf4540001
  2569. /* TRL_LPF_ACQ_GAIN */
  2570. #define R367CAB_TRL_LPF_ACQ_GAIN 0xf455
  2571. #define F367CAB_TRL_GDIR_ACQ 0xf4550070
  2572. #define F367CAB_TRL_GINT_ACQ 0xf4550007
  2573. /* TRL_LPF_TRK_GAIN */
  2574. #define R367CAB_TRL_LPF_TRK_GAIN 0xf456
  2575. #define F367CAB_TRL_GDIR_TRK 0xf4560070
  2576. #define F367CAB_TRL_GINT_TRK 0xf4560007
  2577. /* TRL_LPF_OUT_GAIN */
  2578. #define R367CAB_TRL_LPF_OUT_GAIN 0xf457
  2579. #define F367CAB_TRL_GAIN_OUT 0xf4570007
  2580. /* TRL_LOCKDET_LTH */
  2581. #define R367CAB_TRL_LOCKDET_LTH 0xf458
  2582. #define F367CAB_TRL_LCK_THLO 0xf4580007
  2583. /* TRL_LOCKDET_HTH */
  2584. #define R367CAB_TRL_LOCKDET_HTH 0xf459
  2585. #define F367CAB_TRL_LCK_THHI 0xf45900ff
  2586. /* TRL_LOCKDET_TRGVAL */
  2587. #define R367CAB_TRL_LOCKDET_TRGVAL 0xf45a
  2588. #define F367CAB_TRL_LCK_TRG 0xf45a00ff
  2589. /* IQ_QAM */
  2590. #define R367CAB_IQ_QAM 0xf45c
  2591. #define F367CAB_IQ_INPUT 0xf45c0008
  2592. #define F367CAB_DETECT_MODE 0xf45c0007
  2593. /* FSM_STATE */
  2594. #define R367CAB_FSM_STATE 0xf460
  2595. #define F367CAB_CRL_DFE 0xf4600080
  2596. #define F367CAB_DFE_START 0xf4600040
  2597. #define F367CAB_CTRLG_START 0xf4600030
  2598. #define F367CAB_FSM_FORCESTATE 0xf460000f
  2599. /* FSM_CTL */
  2600. #define R367CAB_FSM_CTL 0xf461
  2601. #define F367CAB_FEC2_EN 0xf4610040
  2602. #define F367CAB_SIT_EN 0xf4610020
  2603. #define F367CAB_TRL_AHEAD 0xf4610010
  2604. #define F367CAB_TRL2_EN 0xf4610008
  2605. #define F367CAB_FSM_EQA1_EN 0xf4610004
  2606. #define F367CAB_FSM_BKP_DIS 0xf4610002
  2607. #define F367CAB_FSM_FORCE_EN 0xf4610001
  2608. /* FSM_STS */
  2609. #define R367CAB_FSM_STS 0xf462
  2610. #define F367CAB_FSM_STATUS 0xf462000f
  2611. /* FSM_SNR0_HTH */
  2612. #define R367CAB_FSM_SNR0_HTH 0xf463
  2613. #define F367CAB_SNR0_HTH 0xf46300ff
  2614. /* FSM_SNR1_HTH */
  2615. #define R367CAB_FSM_SNR1_HTH 0xf464
  2616. #define F367CAB_SNR1_HTH 0xf46400ff
  2617. /* FSM_SNR2_HTH */
  2618. #define R367CAB_FSM_SNR2_HTH 0xf465
  2619. #define F367CAB_SNR2_HTH 0xf46500ff
  2620. /* FSM_SNR0_LTH */
  2621. #define R367CAB_FSM_SNR0_LTH 0xf466
  2622. #define F367CAB_SNR0_LTH 0xf46600ff
  2623. /* FSM_SNR1_LTH */
  2624. #define R367CAB_FSM_SNR1_LTH 0xf467
  2625. #define F367CAB_SNR1_LTH 0xf46700ff
  2626. /* FSM_EQA1_HTH */
  2627. #define R367CAB_FSM_EQA1_HTH 0xf468
  2628. #define F367CAB_SNR3_HTH_LO 0xf46800f0
  2629. #define F367CAB_EQA1_HTH 0xf468000f
  2630. /* FSM_TEMPO */
  2631. #define R367CAB_FSM_TEMPO 0xf469
  2632. #define F367CAB_SIT 0xf46900c0
  2633. #define F367CAB_WST 0xf4690038
  2634. #define F367CAB_ELT 0xf4690006
  2635. #define F367CAB_SNR3_HTH_HI 0xf4690001
  2636. /* FSM_CONFIG */
  2637. #define R367CAB_FSM_CONFIG 0xf46a
  2638. #define F367CAB_FEC2_DFEOFF 0xf46a0004
  2639. #define F367CAB_PRIT_STATE 0xf46a0002
  2640. #define F367CAB_MODMAP_STATE 0xf46a0001
  2641. /* EQU_I_TESTTAP_L */
  2642. #define R367CAB_EQU_I_TESTTAP_L 0xf474
  2643. #define F367CAB_I_TEST_TAP_L 0xf47400ff
  2644. /* EQU_I_TESTTAP_M */
  2645. #define R367CAB_EQU_I_TESTTAP_M 0xf475
  2646. #define F367CAB_I_TEST_TAP_M 0xf47500ff
  2647. /* EQU_I_TESTTAP_H */
  2648. #define R367CAB_EQU_I_TESTTAP_H 0xf476
  2649. #define F367CAB_I_TEST_TAP_H 0xf476001f
  2650. /* EQU_TESTAP_CFG */
  2651. #define R367CAB_EQU_TESTAP_CFG 0xf477
  2652. #define F367CAB_TEST_FFE_DFE_SEL 0xf4770040
  2653. #define F367CAB_TEST_TAP_SELECT 0xf477003f
  2654. /* EQU_Q_TESTTAP_L */
  2655. #define R367CAB_EQU_Q_TESTTAP_L 0xf478
  2656. #define F367CAB_Q_TEST_TAP_L 0xf47800ff
  2657. /* EQU_Q_TESTTAP_M */
  2658. #define R367CAB_EQU_Q_TESTTAP_M 0xf479
  2659. #define F367CAB_Q_TEST_TAP_M 0xf47900ff
  2660. /* EQU_Q_TESTTAP_H */
  2661. #define R367CAB_EQU_Q_TESTTAP_H 0xf47a
  2662. #define F367CAB_Q_TEST_TAP_H 0xf47a001f
  2663. /* EQU_TAP_CTRL */
  2664. #define R367CAB_EQU_TAP_CTRL 0xf47b
  2665. #define F367CAB_MTAP_FRZ 0xf47b0010
  2666. #define F367CAB_PRE_FREEZE 0xf47b0008
  2667. #define F367CAB_DFE_TAPMON_EN 0xf47b0004
  2668. #define F367CAB_FFE_TAPMON_EN 0xf47b0002
  2669. #define F367CAB_MTAP_ONLY 0xf47b0001
  2670. /* EQU_CTR_CRL_CONTROL_L */
  2671. #define R367CAB_EQU_CTR_CRL_CONTROL_L 0xf47c
  2672. #define F367CAB_EQU_CTR_CRL_CONTROL_LO 0xf47c00ff
  2673. /* EQU_CTR_CRL_CONTROL_H */
  2674. #define R367CAB_EQU_CTR_CRL_CONTROL_H 0xf47d
  2675. #define F367CAB_EQU_CTR_CRL_CONTROL_HI 0xf47d00ff
  2676. /* EQU_CTR_HIPOW_L */
  2677. #define R367CAB_EQU_CTR_HIPOW_L 0xf47e
  2678. #define F367CAB_CTR_HIPOW_L 0xf47e00ff
  2679. /* EQU_CTR_HIPOW_H */
  2680. #define R367CAB_EQU_CTR_HIPOW_H 0xf47f
  2681. #define F367CAB_CTR_HIPOW_H 0xf47f00ff
  2682. /* EQU_I_EQU_LO */
  2683. #define R367CAB_EQU_I_EQU_LO 0xf480
  2684. #define F367CAB_EQU_I_EQU_L 0xf48000ff
  2685. /* EQU_I_EQU_HI */
  2686. #define R367CAB_EQU_I_EQU_HI 0xf481
  2687. #define F367CAB_EQU_I_EQU_H 0xf4810003
  2688. /* EQU_Q_EQU_LO */
  2689. #define R367CAB_EQU_Q_EQU_LO 0xf482
  2690. #define F367CAB_EQU_Q_EQU_L 0xf48200ff
  2691. /* EQU_Q_EQU_HI */
  2692. #define R367CAB_EQU_Q_EQU_HI 0xf483
  2693. #define F367CAB_EQU_Q_EQU_H 0xf4830003
  2694. /* EQU_MAPPER */
  2695. #define R367CAB_EQU_MAPPER 0xf484
  2696. #define F367CAB_QUAD_AUTO 0xf4840080
  2697. #define F367CAB_QUAD_INV 0xf4840040
  2698. #define F367CAB_QAM_MODE 0xf4840007
  2699. /* EQU_SWEEP_RATE */
  2700. #define R367CAB_EQU_SWEEP_RATE 0xf485
  2701. #define F367CAB_SNR_PER 0xf48500c0
  2702. #define F367CAB_SWEEP_RATE 0xf485003f
  2703. /* EQU_SNR_LO */
  2704. #define R367CAB_EQU_SNR_LO 0xf486
  2705. #define F367CAB_SNR_LO 0xf48600ff
  2706. /* EQU_SNR_HI */
  2707. #define R367CAB_EQU_SNR_HI 0xf487
  2708. #define F367CAB_SNR_HI 0xf48700ff
  2709. /* EQU_GAMMA_LO */
  2710. #define R367CAB_EQU_GAMMA_LO 0xf488
  2711. #define F367CAB_GAMMA_LO 0xf48800ff
  2712. /* EQU_GAMMA_HI */
  2713. #define R367CAB_EQU_GAMMA_HI 0xf489
  2714. #define F367CAB_GAMMA_ME 0xf48900ff
  2715. /* EQU_ERR_GAIN */
  2716. #define R367CAB_EQU_ERR_GAIN 0xf48a
  2717. #define F367CAB_EQA1MU 0xf48a0070
  2718. #define F367CAB_CRL2MU 0xf48a000e
  2719. #define F367CAB_GAMMA_HI 0xf48a0001
  2720. /* EQU_RADIUS */
  2721. #define R367CAB_EQU_RADIUS 0xf48b
  2722. #define F367CAB_RADIUS 0xf48b00ff
  2723. /* EQU_FFE_MAINTAP */
  2724. #define R367CAB_EQU_FFE_MAINTAP 0xf48c
  2725. #define F367CAB_FFE_MAINTAP_INIT 0xf48c00ff
  2726. /* EQU_FFE_LEAKAGE */
  2727. #define R367CAB_EQU_FFE_LEAKAGE 0xf48e
  2728. #define F367CAB_LEAK_PER 0xf48e00f0
  2729. #define F367CAB_EQU_OUTSEL 0xf48e0002
  2730. #define F367CAB_PNT2dFE 0xf48e0001
  2731. /* EQU_FFE_MAINTAP_POS */
  2732. #define R367CAB_EQU_FFE_MAINTAP_POS 0xf48f
  2733. #define F367CAB_FFE_LEAK_EN 0xf48f0080
  2734. #define F367CAB_DFE_LEAK_EN 0xf48f0040
  2735. #define F367CAB_FFE_MAINTAP_POS 0xf48f003f
  2736. /* EQU_GAIN_WIDE */
  2737. #define R367CAB_EQU_GAIN_WIDE 0xf490
  2738. #define F367CAB_DFE_GAIN_WIDE 0xf49000f0
  2739. #define F367CAB_FFE_GAIN_WIDE 0xf490000f
  2740. /* EQU_GAIN_NARROW */
  2741. #define R367CAB_EQU_GAIN_NARROW 0xf491
  2742. #define F367CAB_DFE_GAIN_NARROW 0xf49100f0
  2743. #define F367CAB_FFE_GAIN_NARROW 0xf491000f
  2744. /* EQU_CTR_LPF_GAIN */
  2745. #define R367CAB_EQU_CTR_LPF_GAIN 0xf492
  2746. #define F367CAB_CTR_GTO 0xf4920080
  2747. #define F367CAB_CTR_GDIR 0xf4920070
  2748. #define F367CAB_SWEEP_EN 0xf4920008
  2749. #define F367CAB_CTR_GINT 0xf4920007
  2750. /* EQU_CRL_LPF_GAIN */
  2751. #define R367CAB_EQU_CRL_LPF_GAIN 0xf493
  2752. #define F367CAB_CRL_GTO 0xf4930080
  2753. #define F367CAB_CRL_GDIR 0xf4930070
  2754. #define F367CAB_SWEEP_DIR 0xf4930008
  2755. #define F367CAB_CRL_GINT 0xf4930007
  2756. /* EQU_GLOBAL_GAIN */
  2757. #define R367CAB_EQU_GLOBAL_GAIN 0xf494
  2758. #define F367CAB_CRL_GAIN 0xf49400f8
  2759. #define F367CAB_CTR_INC_GAIN 0xf4940004
  2760. #define F367CAB_CTR_FRAC 0xf4940003
  2761. /* EQU_CRL_LD_SEN */
  2762. #define R367CAB_EQU_CRL_LD_SEN 0xf495
  2763. #define F367CAB_CTR_BADPOINT_EN 0xf4950080
  2764. #define F367CAB_CTR_GAIN 0xf4950070
  2765. #define F367CAB_LIMANEN 0xf4950008
  2766. #define F367CAB_CRL_LD_SEN 0xf4950007
  2767. /* EQU_CRL_LD_VAL */
  2768. #define R367CAB_EQU_CRL_LD_VAL 0xf496
  2769. #define F367CAB_CRL_BISTH_LIMIT 0xf4960080
  2770. #define F367CAB_CARE_EN 0xf4960040
  2771. #define F367CAB_CRL_LD_PER 0xf4960030
  2772. #define F367CAB_CRL_LD_WST 0xf496000c
  2773. #define F367CAB_CRL_LD_TFS 0xf4960003
  2774. /* EQU_CRL_TFR */
  2775. #define R367CAB_EQU_CRL_TFR 0xf497
  2776. #define F367CAB_CRL_LD_TFR 0xf49700ff
  2777. /* EQU_CRL_BISTH_LO */
  2778. #define R367CAB_EQU_CRL_BISTH_LO 0xf498
  2779. #define F367CAB_CRL_BISTH_LO 0xf49800ff
  2780. /* EQU_CRL_BISTH_HI */
  2781. #define R367CAB_EQU_CRL_BISTH_HI 0xf499
  2782. #define F367CAB_CRL_BISTH_HI 0xf49900ff
  2783. /* EQU_SWEEP_RANGE_LO */
  2784. #define R367CAB_EQU_SWEEP_RANGE_LO 0xf49a
  2785. #define F367CAB_SWEEP_RANGE_LO 0xf49a00ff
  2786. /* EQU_SWEEP_RANGE_HI */
  2787. #define R367CAB_EQU_SWEEP_RANGE_HI 0xf49b
  2788. #define F367CAB_SWEEP_RANGE_HI 0xf49b00ff
  2789. /* EQU_CRL_LIMITER */
  2790. #define R367CAB_EQU_CRL_LIMITER 0xf49c
  2791. #define F367CAB_BISECTOR_EN 0xf49c0080
  2792. #define F367CAB_PHEST128_EN 0xf49c0040
  2793. #define F367CAB_CRL_LIM 0xf49c003f
  2794. /* EQU_MODULUS_MAP */
  2795. #define R367CAB_EQU_MODULUS_MAP 0xf49d
  2796. #define F367CAB_PNT_DEPTH 0xf49d00e0
  2797. #define F367CAB_MODULUS_CMP 0xf49d001f
  2798. /* EQU_PNT_GAIN */
  2799. #define R367CAB_EQU_PNT_GAIN 0xf49e
  2800. #define F367CAB_PNT_EN 0xf49e0080
  2801. #define F367CAB_MODULUSMAP_EN 0xf49e0040
  2802. #define F367CAB_PNT_GAIN 0xf49e003f
  2803. /* FEC_AC_CTR_0 */
  2804. #define R367CAB_FEC_AC_CTR_0 0xf4a8
  2805. #define F367CAB_BE_BYPASS 0xf4a80020
  2806. #define F367CAB_REFRESH47 0xf4a80010
  2807. #define F367CAB_CT_NBST 0xf4a80008
  2808. #define F367CAB_TEI_ENA 0xf4a80004
  2809. #define F367CAB_DS_ENA 0xf4a80002
  2810. #define F367CAB_TSMF_EN 0xf4a80001
  2811. /* FEC_AC_CTR_1 */
  2812. #define R367CAB_FEC_AC_CTR_1 0xf4a9
  2813. #define F367CAB_DEINT_DEPTH 0xf4a900ff
  2814. /* FEC_AC_CTR_2 */
  2815. #define R367CAB_FEC_AC_CTR_2 0xf4aa
  2816. #define F367CAB_DEINT_M 0xf4aa00f8
  2817. #define F367CAB_DIS_UNLOCK 0xf4aa0004
  2818. #define F367CAB_DESCR_MODE 0xf4aa0003
  2819. /* FEC_AC_CTR_3 */
  2820. #define R367CAB_FEC_AC_CTR_3 0xf4ab
  2821. #define F367CAB_DI_UNLOCK 0xf4ab0080
  2822. #define F367CAB_DI_FREEZE 0xf4ab0040
  2823. #define F367CAB_MISMATCH 0xf4ab0030
  2824. #define F367CAB_ACQ_MODE 0xf4ab000c
  2825. #define F367CAB_TRK_MODE 0xf4ab0003
  2826. /* FEC_STATUS */
  2827. #define R367CAB_FEC_STATUS 0xf4ac
  2828. #define F367CAB_DEINT_SMCNTR 0xf4ac00e0
  2829. #define F367CAB_DEINT_SYNCSTATE 0xf4ac0018
  2830. #define F367CAB_DEINT_SYNLOST 0xf4ac0004
  2831. #define F367CAB_DESCR_SYNCSTATE 0xf4ac0002
  2832. /* RS_COUNTER_0 */
  2833. #define R367CAB_RS_COUNTER_0 0xf4ae
  2834. #define F367CAB_BK_CT_L 0xf4ae00ff
  2835. /* RS_COUNTER_1 */
  2836. #define R367CAB_RS_COUNTER_1 0xf4af
  2837. #define F367CAB_BK_CT_H 0xf4af00ff
  2838. /* RS_COUNTER_2 */
  2839. #define R367CAB_RS_COUNTER_2 0xf4b0
  2840. #define F367CAB_CORR_CT_L 0xf4b000ff
  2841. /* RS_COUNTER_3 */
  2842. #define R367CAB_RS_COUNTER_3 0xf4b1
  2843. #define F367CAB_CORR_CT_H 0xf4b100ff
  2844. /* RS_COUNTER_4 */
  2845. #define R367CAB_RS_COUNTER_4 0xf4b2
  2846. #define F367CAB_UNCORR_CT_L 0xf4b200ff
  2847. /* RS_COUNTER_5 */
  2848. #define R367CAB_RS_COUNTER_5 0xf4b3
  2849. #define F367CAB_UNCORR_CT_H 0xf4b300ff
  2850. /* BERT_0 */
  2851. #define R367CAB_BERT_0 0xf4b4
  2852. #define F367CAB_RS_NOCORR 0xf4b40004
  2853. #define F367CAB_CT_HOLD 0xf4b40002
  2854. #define F367CAB_CT_CLEAR 0xf4b40001
  2855. /* BERT_1 */
  2856. #define R367CAB_BERT_1 0xf4b5
  2857. #define F367CAB_BERT_ON 0xf4b50020
  2858. #define F367CAB_BERT_ERR_SRC 0xf4b50010
  2859. #define F367CAB_BERT_ERR_MODE 0xf4b50008
  2860. #define F367CAB_BERT_NBYTE 0xf4b50007
  2861. /* BERT_2 */
  2862. #define R367CAB_BERT_2 0xf4b6
  2863. #define F367CAB_BERT_ERRCOUNT_L 0xf4b600ff
  2864. /* BERT_3 */
  2865. #define R367CAB_BERT_3 0xf4b7
  2866. #define F367CAB_BERT_ERRCOUNT_H 0xf4b700ff
  2867. /* OUTFORMAT_0 */
  2868. #define R367CAB_OUTFORMAT_0 0xf4b8
  2869. #define F367CAB_CLK_POLARITY 0xf4b80080
  2870. #define F367CAB_FEC_TYPE 0xf4b80040
  2871. #define F367CAB_SYNC_STRIP 0xf4b80008
  2872. #define F367CAB_TS_SWAP 0xf4b80004
  2873. #define F367CAB_OUTFORMAT 0xf4b80003
  2874. /* OUTFORMAT_1 */
  2875. #define R367CAB_OUTFORMAT_1 0xf4b9
  2876. #define F367CAB_CI_DIVRANGE 0xf4b900ff
  2877. /* SMOOTHER_2 */
  2878. #define R367CAB_SMOOTHER_2 0xf4be
  2879. #define F367CAB_FIFO_BYPASS 0xf4be0020
  2880. /* TSMF_CTRL_0 */
  2881. #define R367CAB_TSMF_CTRL_0 0xf4c0
  2882. #define F367CAB_TS_NUMBER 0xf4c0001e
  2883. #define F367CAB_SEL_MODE 0xf4c00001
  2884. /* TSMF_CTRL_1 */
  2885. #define R367CAB_TSMF_CTRL_1 0xf4c1
  2886. #define F367CAB_CHECK_ERROR_BIT 0xf4c10080
  2887. #define F367CAB_CHCK_F_SYNC 0xf4c10040
  2888. #define F367CAB_H_MODE 0xf4c10008
  2889. #define F367CAB_D_V_MODE 0xf4c10004
  2890. #define F367CAB_MODE 0xf4c10003
  2891. /* TSMF_CTRL_3 */
  2892. #define R367CAB_TSMF_CTRL_3 0xf4c3
  2893. #define F367CAB_SYNC_IN_COUNT 0xf4c300f0
  2894. #define F367CAB_SYNC_OUT_COUNT 0xf4c3000f
  2895. /* TS_ON_ID_0 */
  2896. #define R367CAB_TS_ON_ID_0 0xf4c4
  2897. #define F367CAB_TS_ID_L 0xf4c400ff
  2898. /* TS_ON_ID_1 */
  2899. #define R367CAB_TS_ON_ID_1 0xf4c5
  2900. #define F367CAB_TS_ID_H 0xf4c500ff
  2901. /* TS_ON_ID_2 */
  2902. #define R367CAB_TS_ON_ID_2 0xf4c6
  2903. #define F367CAB_ON_ID_L 0xf4c600ff
  2904. /* TS_ON_ID_3 */
  2905. #define R367CAB_TS_ON_ID_3 0xf4c7
  2906. #define F367CAB_ON_ID_H 0xf4c700ff
  2907. /* RE_STATUS_0 */
  2908. #define R367CAB_RE_STATUS_0 0xf4c8
  2909. #define F367CAB_RECEIVE_STATUS_L 0xf4c800ff
  2910. /* RE_STATUS_1 */
  2911. #define R367CAB_RE_STATUS_1 0xf4c9
  2912. #define F367CAB_RECEIVE_STATUS_LH 0xf4c900ff
  2913. /* RE_STATUS_2 */
  2914. #define R367CAB_RE_STATUS_2 0xf4ca
  2915. #define F367CAB_RECEIVE_STATUS_HL 0xf4ca00ff
  2916. /* RE_STATUS_3 */
  2917. #define R367CAB_RE_STATUS_3 0xf4cb
  2918. #define F367CAB_RECEIVE_STATUS_HH 0xf4cb003f
  2919. /* TS_STATUS_0 */
  2920. #define R367CAB_TS_STATUS_0 0xf4cc
  2921. #define F367CAB_TS_STATUS_L 0xf4cc00ff
  2922. /* TS_STATUS_1 */
  2923. #define R367CAB_TS_STATUS_1 0xf4cd
  2924. #define F367CAB_TS_STATUS_H 0xf4cd007f
  2925. /* TS_STATUS_2 */
  2926. #define R367CAB_TS_STATUS_2 0xf4ce
  2927. #define F367CAB_ERROR 0xf4ce0080
  2928. #define F367CAB_EMERGENCY 0xf4ce0040
  2929. #define F367CAB_CRE_TS 0xf4ce0030
  2930. #define F367CAB_VER 0xf4ce000e
  2931. #define F367CAB_M_LOCK 0xf4ce0001
  2932. /* TS_STATUS_3 */
  2933. #define R367CAB_TS_STATUS_3 0xf4cf
  2934. #define F367CAB_UPDATE_READY 0xf4cf0080
  2935. #define F367CAB_END_FRAME_HEADER 0xf4cf0040
  2936. #define F367CAB_CONTCNT 0xf4cf0020
  2937. #define F367CAB_TS_IDENTIFIER_SEL 0xf4cf000f
  2938. /* T_O_ID_0 */
  2939. #define R367CAB_T_O_ID_0 0xf4d0
  2940. #define F367CAB_ON_ID_I_L 0xf4d000ff
  2941. /* T_O_ID_1 */
  2942. #define R367CAB_T_O_ID_1 0xf4d1
  2943. #define F367CAB_ON_ID_I_H 0xf4d100ff
  2944. /* T_O_ID_2 */
  2945. #define R367CAB_T_O_ID_2 0xf4d2
  2946. #define F367CAB_TS_ID_I_L 0xf4d200ff
  2947. /* T_O_ID_3 */
  2948. #define R367CAB_T_O_ID_3 0xf4d3
  2949. #define F367CAB_TS_ID_I_H 0xf4d300ff
  2950. #define STV0367CAB_NBREGS 187
  2951. #endif