tda18271c2dd.c 29 KB

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  1. /*
  2. * tda18271c2dd: Driver for the TDA18271C2 tuner
  3. *
  4. * Copyright (C) 2010 Digital Devices GmbH
  5. *
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * version 2 only, as published by the Free Software Foundation.
  10. *
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  21. * 02110-1301, USA
  22. * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
  23. */
  24. #include <linux/kernel.h>
  25. #include <linux/module.h>
  26. #include <linux/moduleparam.h>
  27. #include <linux/init.h>
  28. #include <linux/delay.h>
  29. #include <linux/firmware.h>
  30. #include <linux/i2c.h>
  31. #include <asm/div64.h>
  32. #include "dvb_frontend.h"
  33. #include "tda18271c2dd.h"
  34. /* Max transfer size done by I2C transfer functions */
  35. #define MAX_XFER_SIZE 64
  36. struct SStandardParam {
  37. s32 m_IFFrequency;
  38. u32 m_BandWidth;
  39. u8 m_EP3_4_0;
  40. u8 m_EB22;
  41. };
  42. struct SMap {
  43. u32 m_Frequency;
  44. u8 m_Param;
  45. };
  46. struct SMapI {
  47. u32 m_Frequency;
  48. s32 m_Param;
  49. };
  50. struct SMap2 {
  51. u32 m_Frequency;
  52. u8 m_Param1;
  53. u8 m_Param2;
  54. };
  55. struct SRFBandMap {
  56. u32 m_RF_max;
  57. u32 m_RF1_Default;
  58. u32 m_RF2_Default;
  59. u32 m_RF3_Default;
  60. };
  61. enum ERegister {
  62. ID = 0,
  63. TM,
  64. PL,
  65. EP1, EP2, EP3, EP4, EP5,
  66. CPD, CD1, CD2, CD3,
  67. MPD, MD1, MD2, MD3,
  68. EB1, EB2, EB3, EB4, EB5, EB6, EB7, EB8, EB9, EB10,
  69. EB11, EB12, EB13, EB14, EB15, EB16, EB17, EB18, EB19, EB20,
  70. EB21, EB22, EB23,
  71. NUM_REGS
  72. };
  73. struct tda_state {
  74. struct i2c_adapter *i2c;
  75. u8 adr;
  76. u32 m_Frequency;
  77. u32 IF;
  78. u8 m_IFLevelAnalog;
  79. u8 m_IFLevelDigital;
  80. u8 m_IFLevelDVBC;
  81. u8 m_IFLevelDVBT;
  82. u8 m_EP4;
  83. u8 m_EP3_Standby;
  84. bool m_bMaster;
  85. s32 m_SettlingTime;
  86. u8 m_Regs[NUM_REGS];
  87. /* Tracking filter settings for band 0..6 */
  88. u32 m_RF1[7];
  89. s32 m_RF_A1[7];
  90. s32 m_RF_B1[7];
  91. u32 m_RF2[7];
  92. s32 m_RF_A2[7];
  93. s32 m_RF_B2[7];
  94. u32 m_RF3[7];
  95. u8 m_TMValue_RFCal; /* Calibration temperatur */
  96. bool m_bFMInput; /* true to use Pin 8 for FM Radio */
  97. };
  98. static int PowerScan(struct tda_state *state,
  99. u8 RFBand, u32 RF_in,
  100. u32 *pRF_Out, bool *pbcal);
  101. static int i2c_readn(struct i2c_adapter *adapter, u8 adr, u8 *data, int len)
  102. {
  103. struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD,
  104. .buf = data, .len = len} };
  105. return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1;
  106. }
  107. static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
  108. {
  109. struct i2c_msg msg = {.addr = adr, .flags = 0,
  110. .buf = data, .len = len};
  111. if (i2c_transfer(adap, &msg, 1) != 1) {
  112. printk(KERN_ERR "tda18271c2dd: i2c write error at addr %i\n", adr);
  113. return -1;
  114. }
  115. return 0;
  116. }
  117. static int WriteRegs(struct tda_state *state,
  118. u8 SubAddr, u8 *Regs, u16 nRegs)
  119. {
  120. u8 data[MAX_XFER_SIZE];
  121. if (1 + nRegs > sizeof(data)) {
  122. printk(KERN_WARNING
  123. "%s: i2c wr: len=%d is too big!\n",
  124. KBUILD_MODNAME, nRegs);
  125. return -EINVAL;
  126. }
  127. data[0] = SubAddr;
  128. memcpy(data + 1, Regs, nRegs);
  129. return i2c_write(state->i2c, state->adr, data, nRegs + 1);
  130. }
  131. static int WriteReg(struct tda_state *state, u8 SubAddr, u8 Reg)
  132. {
  133. u8 msg[2] = {SubAddr, Reg};
  134. return i2c_write(state->i2c, state->adr, msg, 2);
  135. }
  136. static int Read(struct tda_state *state, u8 * Regs)
  137. {
  138. return i2c_readn(state->i2c, state->adr, Regs, 16);
  139. }
  140. static int ReadExtented(struct tda_state *state, u8 * Regs)
  141. {
  142. return i2c_readn(state->i2c, state->adr, Regs, NUM_REGS);
  143. }
  144. static int UpdateRegs(struct tda_state *state, u8 RegFrom, u8 RegTo)
  145. {
  146. return WriteRegs(state, RegFrom,
  147. &state->m_Regs[RegFrom], RegTo-RegFrom+1);
  148. }
  149. static int UpdateReg(struct tda_state *state, u8 Reg)
  150. {
  151. return WriteReg(state, Reg, state->m_Regs[Reg]);
  152. }
  153. #include "tda18271c2dd_maps.h"
  154. static void reset(struct tda_state *state)
  155. {
  156. u32 ulIFLevelAnalog = 0;
  157. u32 ulIFLevelDigital = 2;
  158. u32 ulIFLevelDVBC = 7;
  159. u32 ulIFLevelDVBT = 6;
  160. u32 ulXTOut = 0;
  161. u32 ulStandbyMode = 0x06; /* Send in stdb, but leave osc on */
  162. u32 ulSlave = 0;
  163. u32 ulFMInput = 0;
  164. u32 ulSettlingTime = 100;
  165. state->m_Frequency = 0;
  166. state->m_SettlingTime = 100;
  167. state->m_IFLevelAnalog = (ulIFLevelAnalog & 0x07) << 2;
  168. state->m_IFLevelDigital = (ulIFLevelDigital & 0x07) << 2;
  169. state->m_IFLevelDVBC = (ulIFLevelDVBC & 0x07) << 2;
  170. state->m_IFLevelDVBT = (ulIFLevelDVBT & 0x07) << 2;
  171. state->m_EP4 = 0x20;
  172. if (ulXTOut != 0)
  173. state->m_EP4 |= 0x40;
  174. state->m_EP3_Standby = ((ulStandbyMode & 0x07) << 5) | 0x0F;
  175. state->m_bMaster = (ulSlave == 0);
  176. state->m_SettlingTime = ulSettlingTime;
  177. state->m_bFMInput = (ulFMInput == 2);
  178. }
  179. static bool SearchMap1(struct SMap Map[],
  180. u32 Frequency, u8 *pParam)
  181. {
  182. int i = 0;
  183. while ((Map[i].m_Frequency != 0) && (Frequency > Map[i].m_Frequency))
  184. i += 1;
  185. if (Map[i].m_Frequency == 0)
  186. return false;
  187. *pParam = Map[i].m_Param;
  188. return true;
  189. }
  190. static bool SearchMap2(struct SMapI Map[],
  191. u32 Frequency, s32 *pParam)
  192. {
  193. int i = 0;
  194. while ((Map[i].m_Frequency != 0) &&
  195. (Frequency > Map[i].m_Frequency))
  196. i += 1;
  197. if (Map[i].m_Frequency == 0)
  198. return false;
  199. *pParam = Map[i].m_Param;
  200. return true;
  201. }
  202. static bool SearchMap3(struct SMap2 Map[], u32 Frequency,
  203. u8 *pParam1, u8 *pParam2)
  204. {
  205. int i = 0;
  206. while ((Map[i].m_Frequency != 0) &&
  207. (Frequency > Map[i].m_Frequency))
  208. i += 1;
  209. if (Map[i].m_Frequency == 0)
  210. return false;
  211. *pParam1 = Map[i].m_Param1;
  212. *pParam2 = Map[i].m_Param2;
  213. return true;
  214. }
  215. static bool SearchMap4(struct SRFBandMap Map[],
  216. u32 Frequency, u8 *pRFBand)
  217. {
  218. int i = 0;
  219. while (i < 7 && (Frequency > Map[i].m_RF_max))
  220. i += 1;
  221. if (i == 7)
  222. return false;
  223. *pRFBand = i;
  224. return true;
  225. }
  226. static int ThermometerRead(struct tda_state *state, u8 *pTM_Value)
  227. {
  228. int status = 0;
  229. do {
  230. u8 Regs[16];
  231. state->m_Regs[TM] |= 0x10;
  232. status = UpdateReg(state, TM);
  233. if (status < 0)
  234. break;
  235. status = Read(state, Regs);
  236. if (status < 0)
  237. break;
  238. if (((Regs[TM] & 0x0F) == 0 && (Regs[TM] & 0x20) == 0x20) ||
  239. ((Regs[TM] & 0x0F) == 8 && (Regs[TM] & 0x20) == 0x00)) {
  240. state->m_Regs[TM] ^= 0x20;
  241. status = UpdateReg(state, TM);
  242. if (status < 0)
  243. break;
  244. msleep(10);
  245. status = Read(state, Regs);
  246. if (status < 0)
  247. break;
  248. }
  249. *pTM_Value = (Regs[TM] & 0x20)
  250. ? m_Thermometer_Map_2[Regs[TM] & 0x0F]
  251. : m_Thermometer_Map_1[Regs[TM] & 0x0F] ;
  252. state->m_Regs[TM] &= ~0x10; /* Thermometer off */
  253. status = UpdateReg(state, TM);
  254. if (status < 0)
  255. break;
  256. state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 ????????? */
  257. status = UpdateReg(state, EP4);
  258. if (status < 0)
  259. break;
  260. } while (0);
  261. return status;
  262. }
  263. static int StandBy(struct tda_state *state)
  264. {
  265. int status = 0;
  266. do {
  267. state->m_Regs[EB12] &= ~0x20; /* PD_AGC1_Det = 0 */
  268. status = UpdateReg(state, EB12);
  269. if (status < 0)
  270. break;
  271. state->m_Regs[EB18] &= ~0x83; /* AGC1_loop_off = 0, AGC1_Gain = 6 dB */
  272. status = UpdateReg(state, EB18);
  273. if (status < 0)
  274. break;
  275. state->m_Regs[EB21] |= 0x03; /* AGC2_Gain = -6 dB */
  276. state->m_Regs[EP3] = state->m_EP3_Standby;
  277. status = UpdateReg(state, EP3);
  278. if (status < 0)
  279. break;
  280. state->m_Regs[EB23] &= ~0x06; /* ForceLP_Fc2_En = 0, LP_Fc[2] = 0 */
  281. status = UpdateRegs(state, EB21, EB23);
  282. if (status < 0)
  283. break;
  284. } while (0);
  285. return status;
  286. }
  287. static int CalcMainPLL(struct tda_state *state, u32 freq)
  288. {
  289. u8 PostDiv;
  290. u8 Div;
  291. u64 OscFreq;
  292. u32 MainDiv;
  293. if (!SearchMap3(m_Main_PLL_Map, freq, &PostDiv, &Div))
  294. return -EINVAL;
  295. OscFreq = (u64) freq * (u64) Div;
  296. OscFreq *= (u64) 16384;
  297. do_div(OscFreq, (u64)16000000);
  298. MainDiv = OscFreq;
  299. state->m_Regs[MPD] = PostDiv & 0x77;
  300. state->m_Regs[MD1] = ((MainDiv >> 16) & 0x7F);
  301. state->m_Regs[MD2] = ((MainDiv >> 8) & 0xFF);
  302. state->m_Regs[MD3] = (MainDiv & 0xFF);
  303. return UpdateRegs(state, MPD, MD3);
  304. }
  305. static int CalcCalPLL(struct tda_state *state, u32 freq)
  306. {
  307. u8 PostDiv;
  308. u8 Div;
  309. u64 OscFreq;
  310. u32 CalDiv;
  311. if (!SearchMap3(m_Cal_PLL_Map, freq, &PostDiv, &Div))
  312. return -EINVAL;
  313. OscFreq = (u64)freq * (u64)Div;
  314. /* CalDiv = u32( OscFreq * 16384 / 16000000 ); */
  315. OscFreq *= (u64)16384;
  316. do_div(OscFreq, (u64)16000000);
  317. CalDiv = OscFreq;
  318. state->m_Regs[CPD] = PostDiv;
  319. state->m_Regs[CD1] = ((CalDiv >> 16) & 0xFF);
  320. state->m_Regs[CD2] = ((CalDiv >> 8) & 0xFF);
  321. state->m_Regs[CD3] = (CalDiv & 0xFF);
  322. return UpdateRegs(state, CPD, CD3);
  323. }
  324. static int CalibrateRF(struct tda_state *state,
  325. u8 RFBand, u32 freq, s32 *pCprog)
  326. {
  327. int status = 0;
  328. u8 Regs[NUM_REGS];
  329. do {
  330. u8 BP_Filter = 0;
  331. u8 GainTaper = 0;
  332. u8 RFC_K = 0;
  333. u8 RFC_M = 0;
  334. state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 */
  335. status = UpdateReg(state, EP4);
  336. if (status < 0)
  337. break;
  338. state->m_Regs[EB18] |= 0x03; /* AGC1_Gain = 3 */
  339. status = UpdateReg(state, EB18);
  340. if (status < 0)
  341. break;
  342. /* Switching off LT (as datasheet says) causes calibration on C1 to fail */
  343. /* (Readout of Cprog is allways 255) */
  344. if (state->m_Regs[ID] != 0x83) /* C1: ID == 83, C2: ID == 84 */
  345. state->m_Regs[EP3] |= 0x40; /* SM_LT = 1 */
  346. if (!(SearchMap1(m_BP_Filter_Map, freq, &BP_Filter) &&
  347. SearchMap1(m_GainTaper_Map, freq, &GainTaper) &&
  348. SearchMap3(m_KM_Map, freq, &RFC_K, &RFC_M)))
  349. return -EINVAL;
  350. state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | BP_Filter;
  351. state->m_Regs[EP2] = (RFBand << 5) | GainTaper;
  352. state->m_Regs[EB13] = (state->m_Regs[EB13] & ~0x7C) | (RFC_K << 4) | (RFC_M << 2);
  353. status = UpdateRegs(state, EP1, EP3);
  354. if (status < 0)
  355. break;
  356. status = UpdateReg(state, EB13);
  357. if (status < 0)
  358. break;
  359. state->m_Regs[EB4] |= 0x20; /* LO_ForceSrce = 1 */
  360. status = UpdateReg(state, EB4);
  361. if (status < 0)
  362. break;
  363. state->m_Regs[EB7] |= 0x20; /* CAL_ForceSrce = 1 */
  364. status = UpdateReg(state, EB7);
  365. if (status < 0)
  366. break;
  367. state->m_Regs[EB14] = 0; /* RFC_Cprog = 0 */
  368. status = UpdateReg(state, EB14);
  369. if (status < 0)
  370. break;
  371. state->m_Regs[EB20] &= ~0x20; /* ForceLock = 0; */
  372. status = UpdateReg(state, EB20);
  373. if (status < 0)
  374. break;
  375. state->m_Regs[EP4] |= 0x03; /* CAL_Mode = 3 */
  376. status = UpdateRegs(state, EP4, EP5);
  377. if (status < 0)
  378. break;
  379. status = CalcCalPLL(state, freq);
  380. if (status < 0)
  381. break;
  382. status = CalcMainPLL(state, freq + 1000000);
  383. if (status < 0)
  384. break;
  385. msleep(5);
  386. status = UpdateReg(state, EP2);
  387. if (status < 0)
  388. break;
  389. status = UpdateReg(state, EP1);
  390. if (status < 0)
  391. break;
  392. status = UpdateReg(state, EP2);
  393. if (status < 0)
  394. break;
  395. status = UpdateReg(state, EP1);
  396. if (status < 0)
  397. break;
  398. state->m_Regs[EB4] &= ~0x20; /* LO_ForceSrce = 0 */
  399. status = UpdateReg(state, EB4);
  400. if (status < 0)
  401. break;
  402. state->m_Regs[EB7] &= ~0x20; /* CAL_ForceSrce = 0 */
  403. status = UpdateReg(state, EB7);
  404. if (status < 0)
  405. break;
  406. msleep(10);
  407. state->m_Regs[EB20] |= 0x20; /* ForceLock = 1; */
  408. status = UpdateReg(state, EB20);
  409. if (status < 0)
  410. break;
  411. msleep(60);
  412. state->m_Regs[EP4] &= ~0x03; /* CAL_Mode = 0 */
  413. state->m_Regs[EP3] &= ~0x40; /* SM_LT = 0 */
  414. state->m_Regs[EB18] &= ~0x03; /* AGC1_Gain = 0 */
  415. status = UpdateReg(state, EB18);
  416. if (status < 0)
  417. break;
  418. status = UpdateRegs(state, EP3, EP4);
  419. if (status < 0)
  420. break;
  421. status = UpdateReg(state, EP1);
  422. if (status < 0)
  423. break;
  424. status = ReadExtented(state, Regs);
  425. if (status < 0)
  426. break;
  427. *pCprog = Regs[EB14];
  428. } while (0);
  429. return status;
  430. }
  431. static int RFTrackingFiltersInit(struct tda_state *state,
  432. u8 RFBand)
  433. {
  434. int status = 0;
  435. u32 RF1 = m_RF_Band_Map[RFBand].m_RF1_Default;
  436. u32 RF2 = m_RF_Band_Map[RFBand].m_RF2_Default;
  437. u32 RF3 = m_RF_Band_Map[RFBand].m_RF3_Default;
  438. bool bcal = false;
  439. s32 Cprog_cal1 = 0;
  440. s32 Cprog_table1 = 0;
  441. s32 Cprog_cal2 = 0;
  442. s32 Cprog_table2 = 0;
  443. s32 Cprog_cal3 = 0;
  444. s32 Cprog_table3 = 0;
  445. state->m_RF_A1[RFBand] = 0;
  446. state->m_RF_B1[RFBand] = 0;
  447. state->m_RF_A2[RFBand] = 0;
  448. state->m_RF_B2[RFBand] = 0;
  449. do {
  450. status = PowerScan(state, RFBand, RF1, &RF1, &bcal);
  451. if (status < 0)
  452. break;
  453. if (bcal) {
  454. status = CalibrateRF(state, RFBand, RF1, &Cprog_cal1);
  455. if (status < 0)
  456. break;
  457. }
  458. SearchMap2(m_RF_Cal_Map, RF1, &Cprog_table1);
  459. if (!bcal)
  460. Cprog_cal1 = Cprog_table1;
  461. state->m_RF_B1[RFBand] = Cprog_cal1 - Cprog_table1;
  462. /* state->m_RF_A1[RF_Band] = ???? */
  463. if (RF2 == 0)
  464. break;
  465. status = PowerScan(state, RFBand, RF2, &RF2, &bcal);
  466. if (status < 0)
  467. break;
  468. if (bcal) {
  469. status = CalibrateRF(state, RFBand, RF2, &Cprog_cal2);
  470. if (status < 0)
  471. break;
  472. }
  473. SearchMap2(m_RF_Cal_Map, RF2, &Cprog_table2);
  474. if (!bcal)
  475. Cprog_cal2 = Cprog_table2;
  476. state->m_RF_A1[RFBand] =
  477. (Cprog_cal2 - Cprog_table2 - Cprog_cal1 + Cprog_table1) /
  478. ((s32)(RF2) - (s32)(RF1));
  479. if (RF3 == 0)
  480. break;
  481. status = PowerScan(state, RFBand, RF3, &RF3, &bcal);
  482. if (status < 0)
  483. break;
  484. if (bcal) {
  485. status = CalibrateRF(state, RFBand, RF3, &Cprog_cal3);
  486. if (status < 0)
  487. break;
  488. }
  489. SearchMap2(m_RF_Cal_Map, RF3, &Cprog_table3);
  490. if (!bcal)
  491. Cprog_cal3 = Cprog_table3;
  492. state->m_RF_A2[RFBand] = (Cprog_cal3 - Cprog_table3 - Cprog_cal2 + Cprog_table2) / ((s32)(RF3) - (s32)(RF2));
  493. state->m_RF_B2[RFBand] = Cprog_cal2 - Cprog_table2;
  494. } while (0);
  495. state->m_RF1[RFBand] = RF1;
  496. state->m_RF2[RFBand] = RF2;
  497. state->m_RF3[RFBand] = RF3;
  498. #if 0
  499. printk(KERN_ERR "tda18271c2dd: %s %d RF1 = %d A1 = %d B1 = %d RF2 = %d A2 = %d B2 = %d RF3 = %d\n", __func__,
  500. RFBand, RF1, state->m_RF_A1[RFBand], state->m_RF_B1[RFBand], RF2,
  501. state->m_RF_A2[RFBand], state->m_RF_B2[RFBand], RF3);
  502. #endif
  503. return status;
  504. }
  505. static int PowerScan(struct tda_state *state,
  506. u8 RFBand, u32 RF_in, u32 *pRF_Out, bool *pbcal)
  507. {
  508. int status = 0;
  509. do {
  510. u8 Gain_Taper = 0;
  511. s32 RFC_Cprog = 0;
  512. u8 CID_Target = 0;
  513. u8 CountLimit = 0;
  514. u32 freq_MainPLL;
  515. u8 Regs[NUM_REGS];
  516. u8 CID_Gain;
  517. s32 Count = 0;
  518. int sign = 1;
  519. bool wait = false;
  520. if (!(SearchMap2(m_RF_Cal_Map, RF_in, &RFC_Cprog) &&
  521. SearchMap1(m_GainTaper_Map, RF_in, &Gain_Taper) &&
  522. SearchMap3(m_CID_Target_Map, RF_in, &CID_Target, &CountLimit))) {
  523. printk(KERN_ERR "tda18271c2dd: %s Search map failed\n", __func__);
  524. return -EINVAL;
  525. }
  526. state->m_Regs[EP2] = (RFBand << 5) | Gain_Taper;
  527. state->m_Regs[EB14] = (RFC_Cprog);
  528. status = UpdateReg(state, EP2);
  529. if (status < 0)
  530. break;
  531. status = UpdateReg(state, EB14);
  532. if (status < 0)
  533. break;
  534. freq_MainPLL = RF_in + 1000000;
  535. status = CalcMainPLL(state, freq_MainPLL);
  536. if (status < 0)
  537. break;
  538. msleep(5);
  539. state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x03) | 1; /* CAL_mode = 1 */
  540. status = UpdateReg(state, EP4);
  541. if (status < 0)
  542. break;
  543. status = UpdateReg(state, EP2); /* Launch power measurement */
  544. if (status < 0)
  545. break;
  546. status = ReadExtented(state, Regs);
  547. if (status < 0)
  548. break;
  549. CID_Gain = Regs[EB10] & 0x3F;
  550. state->m_Regs[ID] = Regs[ID]; /* Chip version, (needed for C1 workarround in CalibrateRF) */
  551. *pRF_Out = RF_in;
  552. while (CID_Gain < CID_Target) {
  553. freq_MainPLL = RF_in + sign * Count + 1000000;
  554. status = CalcMainPLL(state, freq_MainPLL);
  555. if (status < 0)
  556. break;
  557. msleep(wait ? 5 : 1);
  558. wait = false;
  559. status = UpdateReg(state, EP2); /* Launch power measurement */
  560. if (status < 0)
  561. break;
  562. status = ReadExtented(state, Regs);
  563. if (status < 0)
  564. break;
  565. CID_Gain = Regs[EB10] & 0x3F;
  566. Count += 200000;
  567. if (Count < CountLimit * 100000)
  568. continue;
  569. if (sign < 0)
  570. break;
  571. sign = -sign;
  572. Count = 200000;
  573. wait = true;
  574. }
  575. status = status;
  576. if (status < 0)
  577. break;
  578. if (CID_Gain >= CID_Target) {
  579. *pbcal = true;
  580. *pRF_Out = freq_MainPLL - 1000000;
  581. } else
  582. *pbcal = false;
  583. } while (0);
  584. return status;
  585. }
  586. static int PowerScanInit(struct tda_state *state)
  587. {
  588. int status = 0;
  589. do {
  590. state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | 0x12;
  591. state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x1F); /* If level = 0, Cal mode = 0 */
  592. status = UpdateRegs(state, EP3, EP4);
  593. if (status < 0)
  594. break;
  595. state->m_Regs[EB18] = (state->m_Regs[EB18] & ~0x03); /* AGC 1 Gain = 0 */
  596. status = UpdateReg(state, EB18);
  597. if (status < 0)
  598. break;
  599. state->m_Regs[EB21] = (state->m_Regs[EB21] & ~0x03); /* AGC 2 Gain = 0 (Datasheet = 3) */
  600. state->m_Regs[EB23] = (state->m_Regs[EB23] | 0x06); /* ForceLP_Fc2_En = 1, LPFc[2] = 1 */
  601. status = UpdateRegs(state, EB21, EB23);
  602. if (status < 0)
  603. break;
  604. } while (0);
  605. return status;
  606. }
  607. static int CalcRFFilterCurve(struct tda_state *state)
  608. {
  609. int status = 0;
  610. do {
  611. msleep(200); /* Temperature stabilisation */
  612. status = PowerScanInit(state);
  613. if (status < 0)
  614. break;
  615. status = RFTrackingFiltersInit(state, 0);
  616. if (status < 0)
  617. break;
  618. status = RFTrackingFiltersInit(state, 1);
  619. if (status < 0)
  620. break;
  621. status = RFTrackingFiltersInit(state, 2);
  622. if (status < 0)
  623. break;
  624. status = RFTrackingFiltersInit(state, 3);
  625. if (status < 0)
  626. break;
  627. status = RFTrackingFiltersInit(state, 4);
  628. if (status < 0)
  629. break;
  630. status = RFTrackingFiltersInit(state, 5);
  631. if (status < 0)
  632. break;
  633. status = RFTrackingFiltersInit(state, 6);
  634. if (status < 0)
  635. break;
  636. status = ThermometerRead(state, &state->m_TMValue_RFCal); /* also switches off Cal mode !!! */
  637. if (status < 0)
  638. break;
  639. } while (0);
  640. return status;
  641. }
  642. static int FixedContentsI2CUpdate(struct tda_state *state)
  643. {
  644. static u8 InitRegs[] = {
  645. 0x08, 0x80, 0xC6,
  646. 0xDF, 0x16, 0x60, 0x80,
  647. 0x80, 0x00, 0x00, 0x00,
  648. 0x00, 0x00, 0x00, 0x00,
  649. 0xFC, 0x01, 0x84, 0x41,
  650. 0x01, 0x84, 0x40, 0x07,
  651. 0x00, 0x00, 0x96, 0x3F,
  652. 0xC1, 0x00, 0x8F, 0x00,
  653. 0x00, 0x8C, 0x00, 0x20,
  654. 0xB3, 0x48, 0xB0,
  655. };
  656. int status = 0;
  657. memcpy(&state->m_Regs[TM], InitRegs, EB23 - TM + 1);
  658. do {
  659. status = UpdateRegs(state, TM, EB23);
  660. if (status < 0)
  661. break;
  662. /* AGC1 gain setup */
  663. state->m_Regs[EB17] = 0x00;
  664. status = UpdateReg(state, EB17);
  665. if (status < 0)
  666. break;
  667. state->m_Regs[EB17] = 0x03;
  668. status = UpdateReg(state, EB17);
  669. if (status < 0)
  670. break;
  671. state->m_Regs[EB17] = 0x43;
  672. status = UpdateReg(state, EB17);
  673. if (status < 0)
  674. break;
  675. state->m_Regs[EB17] = 0x4C;
  676. status = UpdateReg(state, EB17);
  677. if (status < 0)
  678. break;
  679. /* IRC Cal Low band */
  680. state->m_Regs[EP3] = 0x1F;
  681. state->m_Regs[EP4] = 0x66;
  682. state->m_Regs[EP5] = 0x81;
  683. state->m_Regs[CPD] = 0xCC;
  684. state->m_Regs[CD1] = 0x6C;
  685. state->m_Regs[CD2] = 0x00;
  686. state->m_Regs[CD3] = 0x00;
  687. state->m_Regs[MPD] = 0xC5;
  688. state->m_Regs[MD1] = 0x77;
  689. state->m_Regs[MD2] = 0x08;
  690. state->m_Regs[MD3] = 0x00;
  691. status = UpdateRegs(state, EP2, MD3); /* diff between sw and datasheet (ep3-md3) */
  692. if (status < 0)
  693. break;
  694. #if 0
  695. state->m_Regs[EB4] = 0x61; /* missing in sw */
  696. status = UpdateReg(state, EB4);
  697. if (status < 0)
  698. break;
  699. msleep(1);
  700. state->m_Regs[EB4] = 0x41;
  701. status = UpdateReg(state, EB4);
  702. if (status < 0)
  703. break;
  704. #endif
  705. msleep(5);
  706. status = UpdateReg(state, EP1);
  707. if (status < 0)
  708. break;
  709. msleep(5);
  710. state->m_Regs[EP5] = 0x85;
  711. state->m_Regs[CPD] = 0xCB;
  712. state->m_Regs[CD1] = 0x66;
  713. state->m_Regs[CD2] = 0x70;
  714. status = UpdateRegs(state, EP3, CD3);
  715. if (status < 0)
  716. break;
  717. msleep(5);
  718. status = UpdateReg(state, EP2);
  719. if (status < 0)
  720. break;
  721. msleep(30);
  722. /* IRC Cal mid band */
  723. state->m_Regs[EP5] = 0x82;
  724. state->m_Regs[CPD] = 0xA8;
  725. state->m_Regs[CD2] = 0x00;
  726. state->m_Regs[MPD] = 0xA1; /* Datasheet = 0xA9 */
  727. state->m_Regs[MD1] = 0x73;
  728. state->m_Regs[MD2] = 0x1A;
  729. status = UpdateRegs(state, EP3, MD3);
  730. if (status < 0)
  731. break;
  732. msleep(5);
  733. status = UpdateReg(state, EP1);
  734. if (status < 0)
  735. break;
  736. msleep(5);
  737. state->m_Regs[EP5] = 0x86;
  738. state->m_Regs[CPD] = 0xA8;
  739. state->m_Regs[CD1] = 0x66;
  740. state->m_Regs[CD2] = 0xA0;
  741. status = UpdateRegs(state, EP3, CD3);
  742. if (status < 0)
  743. break;
  744. msleep(5);
  745. status = UpdateReg(state, EP2);
  746. if (status < 0)
  747. break;
  748. msleep(30);
  749. /* IRC Cal high band */
  750. state->m_Regs[EP5] = 0x83;
  751. state->m_Regs[CPD] = 0x98;
  752. state->m_Regs[CD1] = 0x65;
  753. state->m_Regs[CD2] = 0x00;
  754. state->m_Regs[MPD] = 0x91; /* Datasheet = 0x91 */
  755. state->m_Regs[MD1] = 0x71;
  756. state->m_Regs[MD2] = 0xCD;
  757. status = UpdateRegs(state, EP3, MD3);
  758. if (status < 0)
  759. break;
  760. msleep(5);
  761. status = UpdateReg(state, EP1);
  762. if (status < 0)
  763. break;
  764. msleep(5);
  765. state->m_Regs[EP5] = 0x87;
  766. state->m_Regs[CD1] = 0x65;
  767. state->m_Regs[CD2] = 0x50;
  768. status = UpdateRegs(state, EP3, CD3);
  769. if (status < 0)
  770. break;
  771. msleep(5);
  772. status = UpdateReg(state, EP2);
  773. if (status < 0)
  774. break;
  775. msleep(30);
  776. /* Back to normal */
  777. state->m_Regs[EP4] = 0x64;
  778. status = UpdateReg(state, EP4);
  779. if (status < 0)
  780. break;
  781. status = UpdateReg(state, EP1);
  782. if (status < 0)
  783. break;
  784. } while (0);
  785. return status;
  786. }
  787. static int InitCal(struct tda_state *state)
  788. {
  789. int status = 0;
  790. do {
  791. status = FixedContentsI2CUpdate(state);
  792. if (status < 0)
  793. break;
  794. status = CalcRFFilterCurve(state);
  795. if (status < 0)
  796. break;
  797. status = StandBy(state);
  798. if (status < 0)
  799. break;
  800. /* m_bInitDone = true; */
  801. } while (0);
  802. return status;
  803. };
  804. static int RFTrackingFiltersCorrection(struct tda_state *state,
  805. u32 Frequency)
  806. {
  807. int status = 0;
  808. s32 Cprog_table;
  809. u8 RFBand;
  810. u8 dCoverdT;
  811. if (!SearchMap2(m_RF_Cal_Map, Frequency, &Cprog_table) ||
  812. !SearchMap4(m_RF_Band_Map, Frequency, &RFBand) ||
  813. !SearchMap1(m_RF_Cal_DC_Over_DT_Map, Frequency, &dCoverdT))
  814. return -EINVAL;
  815. do {
  816. u8 TMValue_Current;
  817. u32 RF1 = state->m_RF1[RFBand];
  818. u32 RF2 = state->m_RF1[RFBand];
  819. u32 RF3 = state->m_RF1[RFBand];
  820. s32 RF_A1 = state->m_RF_A1[RFBand];
  821. s32 RF_B1 = state->m_RF_B1[RFBand];
  822. s32 RF_A2 = state->m_RF_A2[RFBand];
  823. s32 RF_B2 = state->m_RF_B2[RFBand];
  824. s32 Capprox = 0;
  825. int TComp;
  826. state->m_Regs[EP3] &= ~0xE0; /* Power up */
  827. status = UpdateReg(state, EP3);
  828. if (status < 0)
  829. break;
  830. status = ThermometerRead(state, &TMValue_Current);
  831. if (status < 0)
  832. break;
  833. if (RF3 == 0 || Frequency < RF2)
  834. Capprox = RF_A1 * ((s32)(Frequency) - (s32)(RF1)) + RF_B1 + Cprog_table;
  835. else
  836. Capprox = RF_A2 * ((s32)(Frequency) - (s32)(RF2)) + RF_B2 + Cprog_table;
  837. TComp = (int)(dCoverdT) * ((int)(TMValue_Current) - (int)(state->m_TMValue_RFCal))/1000;
  838. Capprox += TComp;
  839. if (Capprox < 0)
  840. Capprox = 0;
  841. else if (Capprox > 255)
  842. Capprox = 255;
  843. /* TODO Temperature compensation. There is defenitely a scale factor */
  844. /* missing in the datasheet, so leave it out for now. */
  845. state->m_Regs[EB14] = Capprox;
  846. status = UpdateReg(state, EB14);
  847. if (status < 0)
  848. break;
  849. } while (0);
  850. return status;
  851. }
  852. static int ChannelConfiguration(struct tda_state *state,
  853. u32 Frequency, int Standard)
  854. {
  855. s32 IntermediateFrequency = m_StandardTable[Standard].m_IFFrequency;
  856. int status = 0;
  857. u8 BP_Filter = 0;
  858. u8 RF_Band = 0;
  859. u8 GainTaper = 0;
  860. u8 IR_Meas = 0;
  861. state->IF = IntermediateFrequency;
  862. /* printk("tda18271c2dd: %s Freq = %d Standard = %d IF = %d\n", __func__, Frequency, Standard, IntermediateFrequency); */
  863. /* get values from tables */
  864. if (!(SearchMap1(m_BP_Filter_Map, Frequency, &BP_Filter) &&
  865. SearchMap1(m_GainTaper_Map, Frequency, &GainTaper) &&
  866. SearchMap1(m_IR_Meas_Map, Frequency, &IR_Meas) &&
  867. SearchMap4(m_RF_Band_Map, Frequency, &RF_Band))) {
  868. printk(KERN_ERR "tda18271c2dd: %s SearchMap failed\n", __func__);
  869. return -EINVAL;
  870. }
  871. do {
  872. state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | m_StandardTable[Standard].m_EP3_4_0;
  873. state->m_Regs[EP3] &= ~0x04; /* switch RFAGC to high speed mode */
  874. /* m_EP4 default for XToutOn, CAL_Mode (0) */
  875. state->m_Regs[EP4] = state->m_EP4 | ((Standard > HF_AnalogMax) ? state->m_IFLevelDigital : state->m_IFLevelAnalog);
  876. /* state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital; */
  877. if (Standard <= HF_AnalogMax)
  878. state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelAnalog;
  879. else if (Standard <= HF_ATSC)
  880. state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBT;
  881. else if (Standard <= HF_DVBC)
  882. state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBC;
  883. else
  884. state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital;
  885. if ((Standard == HF_FM_Radio) && state->m_bFMInput)
  886. state->m_Regs[EP4] |= 0x80;
  887. state->m_Regs[MPD] &= ~0x80;
  888. if (Standard > HF_AnalogMax)
  889. state->m_Regs[MPD] |= 0x80; /* Add IF_notch for digital */
  890. state->m_Regs[EB22] = m_StandardTable[Standard].m_EB22;
  891. /* Note: This is missing from flowchart in TDA18271 specification ( 1.5 MHz cutoff for FM ) */
  892. if (Standard == HF_FM_Radio)
  893. state->m_Regs[EB23] |= 0x06; /* ForceLP_Fc2_En = 1, LPFc[2] = 1 */
  894. else
  895. state->m_Regs[EB23] &= ~0x06; /* ForceLP_Fc2_En = 0, LPFc[2] = 0 */
  896. status = UpdateRegs(state, EB22, EB23);
  897. if (status < 0)
  898. break;
  899. state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | 0x40 | BP_Filter; /* Dis_Power_level = 1, Filter */
  900. state->m_Regs[EP5] = (state->m_Regs[EP5] & ~0x07) | IR_Meas;
  901. state->m_Regs[EP2] = (RF_Band << 5) | GainTaper;
  902. state->m_Regs[EB1] = (state->m_Regs[EB1] & ~0x07) |
  903. (state->m_bMaster ? 0x04 : 0x00); /* CALVCO_FortLOn = MS */
  904. /* AGC1_always_master = 0 */
  905. /* AGC_firstn = 0 */
  906. status = UpdateReg(state, EB1);
  907. if (status < 0)
  908. break;
  909. if (state->m_bMaster) {
  910. status = CalcMainPLL(state, Frequency + IntermediateFrequency);
  911. if (status < 0)
  912. break;
  913. status = UpdateRegs(state, TM, EP5);
  914. if (status < 0)
  915. break;
  916. state->m_Regs[EB4] |= 0x20; /* LO_forceSrce = 1 */
  917. status = UpdateReg(state, EB4);
  918. if (status < 0)
  919. break;
  920. msleep(1);
  921. state->m_Regs[EB4] &= ~0x20; /* LO_forceSrce = 0 */
  922. status = UpdateReg(state, EB4);
  923. if (status < 0)
  924. break;
  925. } else {
  926. u8 PostDiv = 0;
  927. u8 Div;
  928. status = CalcCalPLL(state, Frequency + IntermediateFrequency);
  929. if (status < 0)
  930. break;
  931. SearchMap3(m_Cal_PLL_Map, Frequency + IntermediateFrequency, &PostDiv, &Div);
  932. state->m_Regs[MPD] = (state->m_Regs[MPD] & ~0x7F) | (PostDiv & 0x77);
  933. status = UpdateReg(state, MPD);
  934. if (status < 0)
  935. break;
  936. status = UpdateRegs(state, TM, EP5);
  937. if (status < 0)
  938. break;
  939. state->m_Regs[EB7] |= 0x20; /* CAL_forceSrce = 1 */
  940. status = UpdateReg(state, EB7);
  941. if (status < 0)
  942. break;
  943. msleep(1);
  944. state->m_Regs[EB7] &= ~0x20; /* CAL_forceSrce = 0 */
  945. status = UpdateReg(state, EB7);
  946. if (status < 0)
  947. break;
  948. }
  949. msleep(20);
  950. if (Standard != HF_FM_Radio)
  951. state->m_Regs[EP3] |= 0x04; /* RFAGC to normal mode */
  952. status = UpdateReg(state, EP3);
  953. if (status < 0)
  954. break;
  955. } while (0);
  956. return status;
  957. }
  958. static int sleep(struct dvb_frontend *fe)
  959. {
  960. struct tda_state *state = fe->tuner_priv;
  961. StandBy(state);
  962. return 0;
  963. }
  964. static int init(struct dvb_frontend *fe)
  965. {
  966. return 0;
  967. }
  968. static int release(struct dvb_frontend *fe)
  969. {
  970. kfree(fe->tuner_priv);
  971. fe->tuner_priv = NULL;
  972. return 0;
  973. }
  974. static int set_params(struct dvb_frontend *fe)
  975. {
  976. struct tda_state *state = fe->tuner_priv;
  977. int status = 0;
  978. int Standard;
  979. u32 bw = fe->dtv_property_cache.bandwidth_hz;
  980. u32 delsys = fe->dtv_property_cache.delivery_system;
  981. state->m_Frequency = fe->dtv_property_cache.frequency;
  982. switch (delsys) {
  983. case SYS_DVBT:
  984. case SYS_DVBT2:
  985. switch (bw) {
  986. case 6000000:
  987. Standard = HF_DVBT_6MHZ;
  988. break;
  989. case 7000000:
  990. Standard = HF_DVBT_7MHZ;
  991. break;
  992. case 8000000:
  993. Standard = HF_DVBT_8MHZ;
  994. break;
  995. default:
  996. return -EINVAL;
  997. }
  998. case SYS_DVBC_ANNEX_A:
  999. case SYS_DVBC_ANNEX_C:
  1000. if (bw <= 6000000)
  1001. Standard = HF_DVBC_6MHZ;
  1002. else if (bw <= 7000000)
  1003. Standard = HF_DVBC_7MHZ;
  1004. else
  1005. Standard = HF_DVBC_8MHZ;
  1006. break;
  1007. default:
  1008. return -EINVAL;
  1009. }
  1010. do {
  1011. status = RFTrackingFiltersCorrection(state, state->m_Frequency);
  1012. if (status < 0)
  1013. break;
  1014. status = ChannelConfiguration(state, state->m_Frequency,
  1015. Standard);
  1016. if (status < 0)
  1017. break;
  1018. msleep(state->m_SettlingTime); /* Allow AGC's to settle down */
  1019. } while (0);
  1020. return status;
  1021. }
  1022. #if 0
  1023. static int GetSignalStrength(s32 *pSignalStrength, u32 RFAgc, u32 IFAgc)
  1024. {
  1025. if (IFAgc < 500) {
  1026. /* Scale this from 0 to 50000 */
  1027. *pSignalStrength = IFAgc * 100;
  1028. } else {
  1029. /* Scale range 500-1500 to 50000-80000 */
  1030. *pSignalStrength = 50000 + (IFAgc - 500) * 30;
  1031. }
  1032. return 0;
  1033. }
  1034. #endif
  1035. static int get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
  1036. {
  1037. struct tda_state *state = fe->tuner_priv;
  1038. *frequency = state->IF;
  1039. return 0;
  1040. }
  1041. static int get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
  1042. {
  1043. /* struct tda_state *state = fe->tuner_priv; */
  1044. /* *bandwidth = priv->bandwidth; */
  1045. return 0;
  1046. }
  1047. static struct dvb_tuner_ops tuner_ops = {
  1048. .info = {
  1049. .name = "NXP TDA18271C2D",
  1050. .frequency_min = 47125000,
  1051. .frequency_max = 865000000,
  1052. .frequency_step = 62500
  1053. },
  1054. .init = init,
  1055. .sleep = sleep,
  1056. .set_params = set_params,
  1057. .release = release,
  1058. .get_if_frequency = get_if_frequency,
  1059. .get_bandwidth = get_bandwidth,
  1060. };
  1061. struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe,
  1062. struct i2c_adapter *i2c, u8 adr)
  1063. {
  1064. struct tda_state *state;
  1065. state = kzalloc(sizeof(struct tda_state), GFP_KERNEL);
  1066. if (!state)
  1067. return NULL;
  1068. fe->tuner_priv = state;
  1069. state->adr = adr;
  1070. state->i2c = i2c;
  1071. memcpy(&fe->ops.tuner_ops, &tuner_ops, sizeof(struct dvb_tuner_ops));
  1072. reset(state);
  1073. InitCal(state);
  1074. return fe;
  1075. }
  1076. EXPORT_SYMBOL_GPL(tda18271c2dd_attach);
  1077. MODULE_DESCRIPTION("TDA18271C2 driver");
  1078. MODULE_AUTHOR("DD");
  1079. MODULE_LICENSE("GPL");