adv7393.c 11 KB

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  1. /*
  2. * adv7393 - ADV7393 Video Encoder Driver
  3. *
  4. * The encoder hardware does not support SECAM.
  5. *
  6. * Copyright (C) 2010-2012 ADVANSEE - http://www.advansee.com/
  7. * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
  8. *
  9. * Based on ADV7343 driver,
  10. *
  11. * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License as
  15. * published by the Free Software Foundation version 2.
  16. *
  17. * This program is distributed .as is. WITHOUT ANY WARRANTY of any
  18. * kind, whether express or implied; without even the implied warranty
  19. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. */
  22. #include <linux/kernel.h>
  23. #include <linux/init.h>
  24. #include <linux/ctype.h>
  25. #include <linux/slab.h>
  26. #include <linux/i2c.h>
  27. #include <linux/device.h>
  28. #include <linux/delay.h>
  29. #include <linux/module.h>
  30. #include <linux/videodev2.h>
  31. #include <linux/uaccess.h>
  32. #include <media/adv7393.h>
  33. #include <media/v4l2-device.h>
  34. #include <media/v4l2-ctrls.h>
  35. #include "adv7393_regs.h"
  36. MODULE_DESCRIPTION("ADV7393 video encoder driver");
  37. MODULE_LICENSE("GPL");
  38. static bool debug;
  39. module_param(debug, bool, 0644);
  40. MODULE_PARM_DESC(debug, "Debug level 0-1");
  41. struct adv7393_state {
  42. struct v4l2_subdev sd;
  43. struct v4l2_ctrl_handler hdl;
  44. u8 reg00;
  45. u8 reg01;
  46. u8 reg02;
  47. u8 reg35;
  48. u8 reg80;
  49. u8 reg82;
  50. u32 output;
  51. v4l2_std_id std;
  52. };
  53. static inline struct adv7393_state *to_state(struct v4l2_subdev *sd)
  54. {
  55. return container_of(sd, struct adv7393_state, sd);
  56. }
  57. static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
  58. {
  59. return &container_of(ctrl->handler, struct adv7393_state, hdl)->sd;
  60. }
  61. static inline int adv7393_write(struct v4l2_subdev *sd, u8 reg, u8 value)
  62. {
  63. struct i2c_client *client = v4l2_get_subdevdata(sd);
  64. return i2c_smbus_write_byte_data(client, reg, value);
  65. }
  66. static const u8 adv7393_init_reg_val[] = {
  67. ADV7393_SOFT_RESET, ADV7393_SOFT_RESET_DEFAULT,
  68. ADV7393_POWER_MODE_REG, ADV7393_POWER_MODE_REG_DEFAULT,
  69. ADV7393_HD_MODE_REG1, ADV7393_HD_MODE_REG1_DEFAULT,
  70. ADV7393_HD_MODE_REG2, ADV7393_HD_MODE_REG2_DEFAULT,
  71. ADV7393_HD_MODE_REG3, ADV7393_HD_MODE_REG3_DEFAULT,
  72. ADV7393_HD_MODE_REG4, ADV7393_HD_MODE_REG4_DEFAULT,
  73. ADV7393_HD_MODE_REG5, ADV7393_HD_MODE_REG5_DEFAULT,
  74. ADV7393_HD_MODE_REG6, ADV7393_HD_MODE_REG6_DEFAULT,
  75. ADV7393_HD_MODE_REG7, ADV7393_HD_MODE_REG7_DEFAULT,
  76. ADV7393_SD_MODE_REG1, ADV7393_SD_MODE_REG1_DEFAULT,
  77. ADV7393_SD_MODE_REG2, ADV7393_SD_MODE_REG2_DEFAULT,
  78. ADV7393_SD_MODE_REG3, ADV7393_SD_MODE_REG3_DEFAULT,
  79. ADV7393_SD_MODE_REG4, ADV7393_SD_MODE_REG4_DEFAULT,
  80. ADV7393_SD_MODE_REG5, ADV7393_SD_MODE_REG5_DEFAULT,
  81. ADV7393_SD_MODE_REG6, ADV7393_SD_MODE_REG6_DEFAULT,
  82. ADV7393_SD_MODE_REG7, ADV7393_SD_MODE_REG7_DEFAULT,
  83. ADV7393_SD_MODE_REG8, ADV7393_SD_MODE_REG8_DEFAULT,
  84. ADV7393_SD_TIMING_REG0, ADV7393_SD_TIMING_REG0_DEFAULT,
  85. ADV7393_SD_HUE_ADJUST, ADV7393_SD_HUE_ADJUST_DEFAULT,
  86. ADV7393_SD_CGMS_WSS0, ADV7393_SD_CGMS_WSS0_DEFAULT,
  87. ADV7393_SD_BRIGHTNESS_WSS, ADV7393_SD_BRIGHTNESS_WSS_DEFAULT,
  88. };
  89. /*
  90. * 2^32
  91. * FSC(reg) = FSC (HZ) * --------
  92. * 27000000
  93. */
  94. static const struct adv7393_std_info stdinfo[] = {
  95. {
  96. /* FSC(Hz) = 4,433,618.75 Hz */
  97. SD_STD_NTSC, 705268427, V4L2_STD_NTSC_443,
  98. }, {
  99. /* FSC(Hz) = 3,579,545.45 Hz */
  100. SD_STD_NTSC, 569408542, V4L2_STD_NTSC,
  101. }, {
  102. /* FSC(Hz) = 3,575,611.00 Hz */
  103. SD_STD_PAL_M, 568782678, V4L2_STD_PAL_M,
  104. }, {
  105. /* FSC(Hz) = 3,582,056.00 Hz */
  106. SD_STD_PAL_N, 569807903, V4L2_STD_PAL_Nc,
  107. }, {
  108. /* FSC(Hz) = 4,433,618.75 Hz */
  109. SD_STD_PAL_N, 705268427, V4L2_STD_PAL_N,
  110. }, {
  111. /* FSC(Hz) = 4,433,618.75 Hz */
  112. SD_STD_PAL_M, 705268427, V4L2_STD_PAL_60,
  113. }, {
  114. /* FSC(Hz) = 4,433,618.75 Hz */
  115. SD_STD_PAL_BDGHI, 705268427, V4L2_STD_PAL,
  116. },
  117. };
  118. static int adv7393_setstd(struct v4l2_subdev *sd, v4l2_std_id std)
  119. {
  120. struct adv7393_state *state = to_state(sd);
  121. const struct adv7393_std_info *std_info;
  122. int num_std;
  123. u8 reg;
  124. u32 val;
  125. int err = 0;
  126. int i;
  127. num_std = ARRAY_SIZE(stdinfo);
  128. for (i = 0; i < num_std; i++) {
  129. if (stdinfo[i].stdid & std)
  130. break;
  131. }
  132. if (i == num_std) {
  133. v4l2_dbg(1, debug, sd,
  134. "Invalid std or std is not supported: %llx\n",
  135. (unsigned long long)std);
  136. return -EINVAL;
  137. }
  138. std_info = &stdinfo[i];
  139. /* Set the standard */
  140. val = state->reg80 & ~SD_STD_MASK;
  141. val |= std_info->standard_val3;
  142. err = adv7393_write(sd, ADV7393_SD_MODE_REG1, val);
  143. if (err < 0)
  144. goto setstd_exit;
  145. state->reg80 = val;
  146. /* Configure the input mode register */
  147. val = state->reg01 & ~INPUT_MODE_MASK;
  148. val |= SD_INPUT_MODE;
  149. err = adv7393_write(sd, ADV7393_MODE_SELECT_REG, val);
  150. if (err < 0)
  151. goto setstd_exit;
  152. state->reg01 = val;
  153. /* Program the sub carrier frequency registers */
  154. val = std_info->fsc_val;
  155. for (reg = ADV7393_FSC_REG0; reg <= ADV7393_FSC_REG3; reg++) {
  156. err = adv7393_write(sd, reg, val);
  157. if (err < 0)
  158. goto setstd_exit;
  159. val >>= 8;
  160. }
  161. val = state->reg82;
  162. /* Pedestal settings */
  163. if (std & (V4L2_STD_NTSC | V4L2_STD_NTSC_443))
  164. val |= SD_PEDESTAL_EN;
  165. else
  166. val &= SD_PEDESTAL_DI;
  167. err = adv7393_write(sd, ADV7393_SD_MODE_REG2, val);
  168. if (err < 0)
  169. goto setstd_exit;
  170. state->reg82 = val;
  171. setstd_exit:
  172. if (err != 0)
  173. v4l2_err(sd, "Error setting std, write failed\n");
  174. return err;
  175. }
  176. static int adv7393_setoutput(struct v4l2_subdev *sd, u32 output_type)
  177. {
  178. struct adv7393_state *state = to_state(sd);
  179. u8 val;
  180. int err = 0;
  181. if (output_type > ADV7393_SVIDEO_ID) {
  182. v4l2_dbg(1, debug, sd,
  183. "Invalid output type or output type not supported:%d\n",
  184. output_type);
  185. return -EINVAL;
  186. }
  187. /* Enable Appropriate DAC */
  188. val = state->reg00 & 0x03;
  189. if (output_type == ADV7393_COMPOSITE_ID)
  190. val |= ADV7393_COMPOSITE_POWER_VALUE;
  191. else if (output_type == ADV7393_COMPONENT_ID)
  192. val |= ADV7393_COMPONENT_POWER_VALUE;
  193. else
  194. val |= ADV7393_SVIDEO_POWER_VALUE;
  195. err = adv7393_write(sd, ADV7393_POWER_MODE_REG, val);
  196. if (err < 0)
  197. goto setoutput_exit;
  198. state->reg00 = val;
  199. /* Enable YUV output */
  200. val = state->reg02 | YUV_OUTPUT_SELECT;
  201. err = adv7393_write(sd, ADV7393_MODE_REG0, val);
  202. if (err < 0)
  203. goto setoutput_exit;
  204. state->reg02 = val;
  205. /* configure SD DAC Output 1 bit */
  206. val = state->reg82;
  207. if (output_type == ADV7393_COMPONENT_ID)
  208. val &= SD_DAC_OUT1_DI;
  209. else
  210. val |= SD_DAC_OUT1_EN;
  211. err = adv7393_write(sd, ADV7393_SD_MODE_REG2, val);
  212. if (err < 0)
  213. goto setoutput_exit;
  214. state->reg82 = val;
  215. /* configure ED/HD Color DAC Swap bit to zero */
  216. val = state->reg35 & HD_DAC_SWAP_DI;
  217. err = adv7393_write(sd, ADV7393_HD_MODE_REG6, val);
  218. if (err < 0)
  219. goto setoutput_exit;
  220. state->reg35 = val;
  221. setoutput_exit:
  222. if (err != 0)
  223. v4l2_err(sd, "Error setting output, write failed\n");
  224. return err;
  225. }
  226. static int adv7393_log_status(struct v4l2_subdev *sd)
  227. {
  228. struct adv7393_state *state = to_state(sd);
  229. v4l2_info(sd, "Standard: %llx\n", (unsigned long long)state->std);
  230. v4l2_info(sd, "Output: %s\n", (state->output == 0) ? "Composite" :
  231. ((state->output == 1) ? "Component" : "S-Video"));
  232. return 0;
  233. }
  234. static int adv7393_s_ctrl(struct v4l2_ctrl *ctrl)
  235. {
  236. struct v4l2_subdev *sd = to_sd(ctrl);
  237. switch (ctrl->id) {
  238. case V4L2_CID_BRIGHTNESS:
  239. return adv7393_write(sd, ADV7393_SD_BRIGHTNESS_WSS,
  240. ctrl->val & SD_BRIGHTNESS_VALUE_MASK);
  241. case V4L2_CID_HUE:
  242. return adv7393_write(sd, ADV7393_SD_HUE_ADJUST,
  243. ctrl->val - ADV7393_HUE_MIN);
  244. case V4L2_CID_GAIN:
  245. return adv7393_write(sd, ADV7393_DAC123_OUTPUT_LEVEL,
  246. ctrl->val);
  247. }
  248. return -EINVAL;
  249. }
  250. static const struct v4l2_ctrl_ops adv7393_ctrl_ops = {
  251. .s_ctrl = adv7393_s_ctrl,
  252. };
  253. static const struct v4l2_subdev_core_ops adv7393_core_ops = {
  254. .log_status = adv7393_log_status,
  255. };
  256. static int adv7393_s_std_output(struct v4l2_subdev *sd, v4l2_std_id std)
  257. {
  258. struct adv7393_state *state = to_state(sd);
  259. int err = 0;
  260. if (state->std == std)
  261. return 0;
  262. err = adv7393_setstd(sd, std);
  263. if (!err)
  264. state->std = std;
  265. return err;
  266. }
  267. static int adv7393_s_routing(struct v4l2_subdev *sd,
  268. u32 input, u32 output, u32 config)
  269. {
  270. struct adv7393_state *state = to_state(sd);
  271. int err = 0;
  272. if (state->output == output)
  273. return 0;
  274. err = adv7393_setoutput(sd, output);
  275. if (!err)
  276. state->output = output;
  277. return err;
  278. }
  279. static const struct v4l2_subdev_video_ops adv7393_video_ops = {
  280. .s_std_output = adv7393_s_std_output,
  281. .s_routing = adv7393_s_routing,
  282. };
  283. static const struct v4l2_subdev_ops adv7393_ops = {
  284. .core = &adv7393_core_ops,
  285. .video = &adv7393_video_ops,
  286. };
  287. static int adv7393_initialize(struct v4l2_subdev *sd)
  288. {
  289. struct adv7393_state *state = to_state(sd);
  290. int err = 0;
  291. int i;
  292. for (i = 0; i < ARRAY_SIZE(adv7393_init_reg_val); i += 2) {
  293. err = adv7393_write(sd, adv7393_init_reg_val[i],
  294. adv7393_init_reg_val[i+1]);
  295. if (err) {
  296. v4l2_err(sd, "Error initializing\n");
  297. return err;
  298. }
  299. }
  300. /* Configure for default video standard */
  301. err = adv7393_setoutput(sd, state->output);
  302. if (err < 0) {
  303. v4l2_err(sd, "Error setting output during init\n");
  304. return -EINVAL;
  305. }
  306. err = adv7393_setstd(sd, state->std);
  307. if (err < 0) {
  308. v4l2_err(sd, "Error setting std during init\n");
  309. return -EINVAL;
  310. }
  311. return err;
  312. }
  313. static int adv7393_probe(struct i2c_client *client,
  314. const struct i2c_device_id *id)
  315. {
  316. struct adv7393_state *state;
  317. int err;
  318. if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
  319. return -ENODEV;
  320. v4l_info(client, "chip found @ 0x%x (%s)\n",
  321. client->addr << 1, client->adapter->name);
  322. state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
  323. if (state == NULL)
  324. return -ENOMEM;
  325. state->reg00 = ADV7393_POWER_MODE_REG_DEFAULT;
  326. state->reg01 = 0x00;
  327. state->reg02 = 0x20;
  328. state->reg35 = ADV7393_HD_MODE_REG6_DEFAULT;
  329. state->reg80 = ADV7393_SD_MODE_REG1_DEFAULT;
  330. state->reg82 = ADV7393_SD_MODE_REG2_DEFAULT;
  331. state->output = ADV7393_COMPOSITE_ID;
  332. state->std = V4L2_STD_NTSC;
  333. v4l2_i2c_subdev_init(&state->sd, client, &adv7393_ops);
  334. v4l2_ctrl_handler_init(&state->hdl, 3);
  335. v4l2_ctrl_new_std(&state->hdl, &adv7393_ctrl_ops,
  336. V4L2_CID_BRIGHTNESS, ADV7393_BRIGHTNESS_MIN,
  337. ADV7393_BRIGHTNESS_MAX, 1,
  338. ADV7393_BRIGHTNESS_DEF);
  339. v4l2_ctrl_new_std(&state->hdl, &adv7393_ctrl_ops,
  340. V4L2_CID_HUE, ADV7393_HUE_MIN,
  341. ADV7393_HUE_MAX, 1,
  342. ADV7393_HUE_DEF);
  343. v4l2_ctrl_new_std(&state->hdl, &adv7393_ctrl_ops,
  344. V4L2_CID_GAIN, ADV7393_GAIN_MIN,
  345. ADV7393_GAIN_MAX, 1,
  346. ADV7393_GAIN_DEF);
  347. state->sd.ctrl_handler = &state->hdl;
  348. if (state->hdl.error) {
  349. int err = state->hdl.error;
  350. v4l2_ctrl_handler_free(&state->hdl);
  351. return err;
  352. }
  353. v4l2_ctrl_handler_setup(&state->hdl);
  354. err = adv7393_initialize(&state->sd);
  355. if (err)
  356. v4l2_ctrl_handler_free(&state->hdl);
  357. return err;
  358. }
  359. static int adv7393_remove(struct i2c_client *client)
  360. {
  361. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  362. struct adv7393_state *state = to_state(sd);
  363. v4l2_device_unregister_subdev(sd);
  364. v4l2_ctrl_handler_free(&state->hdl);
  365. return 0;
  366. }
  367. static const struct i2c_device_id adv7393_id[] = {
  368. {"adv7393", 0},
  369. {},
  370. };
  371. MODULE_DEVICE_TABLE(i2c, adv7393_id);
  372. static struct i2c_driver adv7393_driver = {
  373. .driver = {
  374. .owner = THIS_MODULE,
  375. .name = "adv7393",
  376. },
  377. .probe = adv7393_probe,
  378. .remove = adv7393_remove,
  379. .id_table = adv7393_id,
  380. };
  381. module_i2c_driver(adv7393_driver);