adv7842.c 96 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373
  1. /*
  2. * adv7842 - Analog Devices ADV7842 video decoder driver
  3. *
  4. * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
  5. *
  6. * This program is free software; you may redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; version 2 of the License.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  11. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  12. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  13. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  14. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  15. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  16. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  17. * SOFTWARE.
  18. *
  19. */
  20. /*
  21. * References (c = chapter, p = page):
  22. * REF_01 - Analog devices, ADV7842,
  23. * Register Settings Recommendations, Rev. 1.9, April 2011
  24. * REF_02 - Analog devices, Software User Guide, UG-206,
  25. * ADV7842 I2C Register Maps, Rev. 0, November 2010
  26. * REF_03 - Analog devices, Hardware User Guide, UG-214,
  27. * ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb
  28. * Decoder and Digitizer , Rev. 0, January 2011
  29. */
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include <linux/slab.h>
  33. #include <linux/i2c.h>
  34. #include <linux/delay.h>
  35. #include <linux/videodev2.h>
  36. #include <linux/workqueue.h>
  37. #include <linux/v4l2-dv-timings.h>
  38. #include <linux/hdmi.h>
  39. #include <media/v4l2-device.h>
  40. #include <media/v4l2-event.h>
  41. #include <media/v4l2-ctrls.h>
  42. #include <media/v4l2-dv-timings.h>
  43. #include <media/adv7842.h>
  44. static int debug;
  45. module_param(debug, int, 0644);
  46. MODULE_PARM_DESC(debug, "debug level (0-2)");
  47. MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver");
  48. MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
  49. MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
  50. MODULE_LICENSE("GPL");
  51. /* ADV7842 system clock frequency */
  52. #define ADV7842_fsc (28636360)
  53. #define ADV7842_RGB_OUT (1 << 1)
  54. #define ADV7842_OP_FORMAT_SEL_8BIT (0 << 0)
  55. #define ADV7842_OP_FORMAT_SEL_10BIT (1 << 0)
  56. #define ADV7842_OP_FORMAT_SEL_12BIT (2 << 0)
  57. #define ADV7842_OP_MODE_SEL_SDR_422 (0 << 5)
  58. #define ADV7842_OP_MODE_SEL_DDR_422 (1 << 5)
  59. #define ADV7842_OP_MODE_SEL_SDR_444 (2 << 5)
  60. #define ADV7842_OP_MODE_SEL_DDR_444 (3 << 5)
  61. #define ADV7842_OP_MODE_SEL_SDR_422_2X (4 << 5)
  62. #define ADV7842_OP_MODE_SEL_ADI_CM (5 << 5)
  63. #define ADV7842_OP_CH_SEL_GBR (0 << 5)
  64. #define ADV7842_OP_CH_SEL_GRB (1 << 5)
  65. #define ADV7842_OP_CH_SEL_BGR (2 << 5)
  66. #define ADV7842_OP_CH_SEL_RGB (3 << 5)
  67. #define ADV7842_OP_CH_SEL_BRG (4 << 5)
  68. #define ADV7842_OP_CH_SEL_RBG (5 << 5)
  69. #define ADV7842_OP_SWAP_CB_CR (1 << 0)
  70. /*
  71. **********************************************************************
  72. *
  73. * Arrays with configuration parameters for the ADV7842
  74. *
  75. **********************************************************************
  76. */
  77. struct adv7842_format_info {
  78. u32 code;
  79. u8 op_ch_sel;
  80. bool rgb_out;
  81. bool swap_cb_cr;
  82. u8 op_format_sel;
  83. };
  84. struct adv7842_state {
  85. struct adv7842_platform_data pdata;
  86. struct v4l2_subdev sd;
  87. struct media_pad pad;
  88. struct v4l2_ctrl_handler hdl;
  89. enum adv7842_mode mode;
  90. struct v4l2_dv_timings timings;
  91. enum adv7842_vid_std_select vid_std_select;
  92. const struct adv7842_format_info *format;
  93. v4l2_std_id norm;
  94. struct {
  95. u8 edid[256];
  96. u32 present;
  97. } hdmi_edid;
  98. struct {
  99. u8 edid[256];
  100. u32 present;
  101. } vga_edid;
  102. struct v4l2_fract aspect_ratio;
  103. u32 rgb_quantization_range;
  104. bool is_cea_format;
  105. struct workqueue_struct *work_queues;
  106. struct delayed_work delayed_work_enable_hotplug;
  107. bool restart_stdi_once;
  108. bool hdmi_port_a;
  109. /* i2c clients */
  110. struct i2c_client *i2c_sdp_io;
  111. struct i2c_client *i2c_sdp;
  112. struct i2c_client *i2c_cp;
  113. struct i2c_client *i2c_vdp;
  114. struct i2c_client *i2c_afe;
  115. struct i2c_client *i2c_hdmi;
  116. struct i2c_client *i2c_repeater;
  117. struct i2c_client *i2c_edid;
  118. struct i2c_client *i2c_infoframe;
  119. struct i2c_client *i2c_cec;
  120. struct i2c_client *i2c_avlink;
  121. /* controls */
  122. struct v4l2_ctrl *detect_tx_5v_ctrl;
  123. struct v4l2_ctrl *analog_sampling_phase_ctrl;
  124. struct v4l2_ctrl *free_run_color_ctrl_manual;
  125. struct v4l2_ctrl *free_run_color_ctrl;
  126. struct v4l2_ctrl *rgb_quantization_range_ctrl;
  127. };
  128. /* Unsupported timings. This device cannot support 720p30. */
  129. static const struct v4l2_dv_timings adv7842_timings_exceptions[] = {
  130. V4L2_DV_BT_CEA_1280X720P30,
  131. { }
  132. };
  133. static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
  134. {
  135. int i;
  136. for (i = 0; adv7842_timings_exceptions[i].bt.width; i++)
  137. if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0))
  138. return false;
  139. return true;
  140. }
  141. struct adv7842_video_standards {
  142. struct v4l2_dv_timings timings;
  143. u8 vid_std;
  144. u8 v_freq;
  145. };
  146. /* sorted by number of lines */
  147. static const struct adv7842_video_standards adv7842_prim_mode_comp[] = {
  148. /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
  149. { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
  150. { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
  151. { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
  152. { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
  153. { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
  154. { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
  155. { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
  156. { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
  157. /* TODO add 1920x1080P60_RB (CVT timing) */
  158. { },
  159. };
  160. /* sorted by number of lines */
  161. static const struct adv7842_video_standards adv7842_prim_mode_gr[] = {
  162. { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
  163. { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
  164. { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
  165. { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
  166. { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
  167. { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
  168. { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
  169. { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
  170. { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
  171. { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
  172. { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
  173. { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
  174. { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
  175. { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
  176. { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
  177. { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
  178. { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
  179. { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
  180. { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
  181. { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
  182. /* TODO add 1600X1200P60_RB (not a DMT timing) */
  183. { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
  184. { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
  185. { },
  186. };
  187. /* sorted by number of lines */
  188. static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = {
  189. { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
  190. { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
  191. { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
  192. { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
  193. { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
  194. { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
  195. { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
  196. { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
  197. { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
  198. { },
  199. };
  200. /* sorted by number of lines */
  201. static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = {
  202. { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
  203. { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
  204. { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
  205. { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
  206. { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
  207. { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
  208. { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
  209. { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
  210. { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
  211. { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
  212. { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
  213. { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
  214. { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
  215. { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
  216. { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
  217. { },
  218. };
  219. static const struct v4l2_event adv7842_ev_fmt = {
  220. .type = V4L2_EVENT_SOURCE_CHANGE,
  221. .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
  222. };
  223. /* ----------------------------------------------------------------------- */
  224. static inline struct adv7842_state *to_state(struct v4l2_subdev *sd)
  225. {
  226. return container_of(sd, struct adv7842_state, sd);
  227. }
  228. static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
  229. {
  230. return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd;
  231. }
  232. static inline unsigned hblanking(const struct v4l2_bt_timings *t)
  233. {
  234. return V4L2_DV_BT_BLANKING_WIDTH(t);
  235. }
  236. static inline unsigned htotal(const struct v4l2_bt_timings *t)
  237. {
  238. return V4L2_DV_BT_FRAME_WIDTH(t);
  239. }
  240. static inline unsigned vblanking(const struct v4l2_bt_timings *t)
  241. {
  242. return V4L2_DV_BT_BLANKING_HEIGHT(t);
  243. }
  244. static inline unsigned vtotal(const struct v4l2_bt_timings *t)
  245. {
  246. return V4L2_DV_BT_FRAME_HEIGHT(t);
  247. }
  248. /* ----------------------------------------------------------------------- */
  249. static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
  250. u8 command, bool check)
  251. {
  252. union i2c_smbus_data data;
  253. if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
  254. I2C_SMBUS_READ, command,
  255. I2C_SMBUS_BYTE_DATA, &data))
  256. return data.byte;
  257. if (check)
  258. v4l_err(client, "error reading %02x, %02x\n",
  259. client->addr, command);
  260. return -EIO;
  261. }
  262. static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
  263. {
  264. int i;
  265. for (i = 0; i < 3; i++) {
  266. int ret = adv_smbus_read_byte_data_check(client, command, true);
  267. if (ret >= 0) {
  268. if (i)
  269. v4l_err(client, "read ok after %d retries\n", i);
  270. return ret;
  271. }
  272. }
  273. v4l_err(client, "read failed\n");
  274. return -EIO;
  275. }
  276. static s32 adv_smbus_write_byte_data(struct i2c_client *client,
  277. u8 command, u8 value)
  278. {
  279. union i2c_smbus_data data;
  280. int err;
  281. int i;
  282. data.byte = value;
  283. for (i = 0; i < 3; i++) {
  284. err = i2c_smbus_xfer(client->adapter, client->addr,
  285. client->flags,
  286. I2C_SMBUS_WRITE, command,
  287. I2C_SMBUS_BYTE_DATA, &data);
  288. if (!err)
  289. break;
  290. }
  291. if (err < 0)
  292. v4l_err(client, "error writing %02x, %02x, %02x\n",
  293. client->addr, command, value);
  294. return err;
  295. }
  296. static void adv_smbus_write_byte_no_check(struct i2c_client *client,
  297. u8 command, u8 value)
  298. {
  299. union i2c_smbus_data data;
  300. data.byte = value;
  301. i2c_smbus_xfer(client->adapter, client->addr,
  302. client->flags,
  303. I2C_SMBUS_WRITE, command,
  304. I2C_SMBUS_BYTE_DATA, &data);
  305. }
  306. static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
  307. u8 command, unsigned length, const u8 *values)
  308. {
  309. union i2c_smbus_data data;
  310. if (length > I2C_SMBUS_BLOCK_MAX)
  311. length = I2C_SMBUS_BLOCK_MAX;
  312. data.block[0] = length;
  313. memcpy(data.block + 1, values, length);
  314. return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
  315. I2C_SMBUS_WRITE, command,
  316. I2C_SMBUS_I2C_BLOCK_DATA, &data);
  317. }
  318. /* ----------------------------------------------------------------------- */
  319. static inline int io_read(struct v4l2_subdev *sd, u8 reg)
  320. {
  321. struct i2c_client *client = v4l2_get_subdevdata(sd);
  322. return adv_smbus_read_byte_data(client, reg);
  323. }
  324. static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  325. {
  326. struct i2c_client *client = v4l2_get_subdevdata(sd);
  327. return adv_smbus_write_byte_data(client, reg, val);
  328. }
  329. static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
  330. {
  331. return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
  332. }
  333. static inline int io_write_clr_set(struct v4l2_subdev *sd,
  334. u8 reg, u8 mask, u8 val)
  335. {
  336. return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
  337. }
  338. static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
  339. {
  340. struct adv7842_state *state = to_state(sd);
  341. return adv_smbus_read_byte_data(state->i2c_avlink, reg);
  342. }
  343. static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  344. {
  345. struct adv7842_state *state = to_state(sd);
  346. return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
  347. }
  348. static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
  349. {
  350. struct adv7842_state *state = to_state(sd);
  351. return adv_smbus_read_byte_data(state->i2c_cec, reg);
  352. }
  353. static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  354. {
  355. struct adv7842_state *state = to_state(sd);
  356. return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
  357. }
  358. static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
  359. {
  360. return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
  361. }
  362. static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
  363. {
  364. struct adv7842_state *state = to_state(sd);
  365. return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
  366. }
  367. static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  368. {
  369. struct adv7842_state *state = to_state(sd);
  370. return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
  371. }
  372. static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg)
  373. {
  374. struct adv7842_state *state = to_state(sd);
  375. return adv_smbus_read_byte_data(state->i2c_sdp_io, reg);
  376. }
  377. static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  378. {
  379. struct adv7842_state *state = to_state(sd);
  380. return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val);
  381. }
  382. static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
  383. {
  384. return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val);
  385. }
  386. static inline int sdp_read(struct v4l2_subdev *sd, u8 reg)
  387. {
  388. struct adv7842_state *state = to_state(sd);
  389. return adv_smbus_read_byte_data(state->i2c_sdp, reg);
  390. }
  391. static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  392. {
  393. struct adv7842_state *state = to_state(sd);
  394. return adv_smbus_write_byte_data(state->i2c_sdp, reg, val);
  395. }
  396. static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
  397. {
  398. return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val);
  399. }
  400. static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
  401. {
  402. struct adv7842_state *state = to_state(sd);
  403. return adv_smbus_read_byte_data(state->i2c_afe, reg);
  404. }
  405. static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  406. {
  407. struct adv7842_state *state = to_state(sd);
  408. return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
  409. }
  410. static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
  411. {
  412. return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);
  413. }
  414. static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
  415. {
  416. struct adv7842_state *state = to_state(sd);
  417. return adv_smbus_read_byte_data(state->i2c_repeater, reg);
  418. }
  419. static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  420. {
  421. struct adv7842_state *state = to_state(sd);
  422. return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
  423. }
  424. static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
  425. {
  426. return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
  427. }
  428. static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
  429. {
  430. struct adv7842_state *state = to_state(sd);
  431. return adv_smbus_read_byte_data(state->i2c_edid, reg);
  432. }
  433. static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  434. {
  435. struct adv7842_state *state = to_state(sd);
  436. return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
  437. }
  438. static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
  439. {
  440. struct adv7842_state *state = to_state(sd);
  441. return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
  442. }
  443. static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  444. {
  445. struct adv7842_state *state = to_state(sd);
  446. return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
  447. }
  448. static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
  449. {
  450. return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
  451. }
  452. static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
  453. {
  454. struct adv7842_state *state = to_state(sd);
  455. return adv_smbus_read_byte_data(state->i2c_cp, reg);
  456. }
  457. static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  458. {
  459. struct adv7842_state *state = to_state(sd);
  460. return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
  461. }
  462. static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
  463. {
  464. return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
  465. }
  466. static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
  467. {
  468. struct adv7842_state *state = to_state(sd);
  469. return adv_smbus_read_byte_data(state->i2c_vdp, reg);
  470. }
  471. static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  472. {
  473. struct adv7842_state *state = to_state(sd);
  474. return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
  475. }
  476. static void main_reset(struct v4l2_subdev *sd)
  477. {
  478. struct i2c_client *client = v4l2_get_subdevdata(sd);
  479. v4l2_dbg(1, debug, sd, "%s:\n", __func__);
  480. adv_smbus_write_byte_no_check(client, 0xff, 0x80);
  481. mdelay(5);
  482. }
  483. /* -----------------------------------------------------------------------------
  484. * Format helpers
  485. */
  486. static const struct adv7842_format_info adv7842_formats[] = {
  487. { MEDIA_BUS_FMT_RGB888_1X24, ADV7842_OP_CH_SEL_RGB, true, false,
  488. ADV7842_OP_MODE_SEL_SDR_444 | ADV7842_OP_FORMAT_SEL_8BIT },
  489. { MEDIA_BUS_FMT_YUYV8_2X8, ADV7842_OP_CH_SEL_RGB, false, false,
  490. ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT },
  491. { MEDIA_BUS_FMT_YVYU8_2X8, ADV7842_OP_CH_SEL_RGB, false, true,
  492. ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT },
  493. { MEDIA_BUS_FMT_YUYV10_2X10, ADV7842_OP_CH_SEL_RGB, false, false,
  494. ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT },
  495. { MEDIA_BUS_FMT_YVYU10_2X10, ADV7842_OP_CH_SEL_RGB, false, true,
  496. ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT },
  497. { MEDIA_BUS_FMT_YUYV12_2X12, ADV7842_OP_CH_SEL_RGB, false, false,
  498. ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT },
  499. { MEDIA_BUS_FMT_YVYU12_2X12, ADV7842_OP_CH_SEL_RGB, false, true,
  500. ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT },
  501. { MEDIA_BUS_FMT_UYVY8_1X16, ADV7842_OP_CH_SEL_RBG, false, false,
  502. ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
  503. { MEDIA_BUS_FMT_VYUY8_1X16, ADV7842_OP_CH_SEL_RBG, false, true,
  504. ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
  505. { MEDIA_BUS_FMT_YUYV8_1X16, ADV7842_OP_CH_SEL_RGB, false, false,
  506. ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
  507. { MEDIA_BUS_FMT_YVYU8_1X16, ADV7842_OP_CH_SEL_RGB, false, true,
  508. ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
  509. { MEDIA_BUS_FMT_UYVY10_1X20, ADV7842_OP_CH_SEL_RBG, false, false,
  510. ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
  511. { MEDIA_BUS_FMT_VYUY10_1X20, ADV7842_OP_CH_SEL_RBG, false, true,
  512. ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
  513. { MEDIA_BUS_FMT_YUYV10_1X20, ADV7842_OP_CH_SEL_RGB, false, false,
  514. ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
  515. { MEDIA_BUS_FMT_YVYU10_1X20, ADV7842_OP_CH_SEL_RGB, false, true,
  516. ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
  517. { MEDIA_BUS_FMT_UYVY12_1X24, ADV7842_OP_CH_SEL_RBG, false, false,
  518. ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
  519. { MEDIA_BUS_FMT_VYUY12_1X24, ADV7842_OP_CH_SEL_RBG, false, true,
  520. ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
  521. { MEDIA_BUS_FMT_YUYV12_1X24, ADV7842_OP_CH_SEL_RGB, false, false,
  522. ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
  523. { MEDIA_BUS_FMT_YVYU12_1X24, ADV7842_OP_CH_SEL_RGB, false, true,
  524. ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
  525. };
  526. static const struct adv7842_format_info *
  527. adv7842_format_info(struct adv7842_state *state, u32 code)
  528. {
  529. unsigned int i;
  530. for (i = 0; i < ARRAY_SIZE(adv7842_formats); ++i) {
  531. if (adv7842_formats[i].code == code)
  532. return &adv7842_formats[i];
  533. }
  534. return NULL;
  535. }
  536. /* ----------------------------------------------------------------------- */
  537. static inline bool is_analog_input(struct v4l2_subdev *sd)
  538. {
  539. struct adv7842_state *state = to_state(sd);
  540. return ((state->mode == ADV7842_MODE_RGB) ||
  541. (state->mode == ADV7842_MODE_COMP));
  542. }
  543. static inline bool is_digital_input(struct v4l2_subdev *sd)
  544. {
  545. struct adv7842_state *state = to_state(sd);
  546. return state->mode == ADV7842_MODE_HDMI;
  547. }
  548. static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = {
  549. .type = V4L2_DV_BT_656_1120,
  550. /* keep this initialization for compatibility with GCC < 4.4.6 */
  551. .reserved = { 0 },
  552. V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
  553. V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
  554. V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
  555. V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
  556. V4L2_DV_BT_CAP_CUSTOM)
  557. };
  558. static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = {
  559. .type = V4L2_DV_BT_656_1120,
  560. /* keep this initialization for compatibility with GCC < 4.4.6 */
  561. .reserved = { 0 },
  562. V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
  563. V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
  564. V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
  565. V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
  566. V4L2_DV_BT_CAP_CUSTOM)
  567. };
  568. static inline const struct v4l2_dv_timings_cap *
  569. adv7842_get_dv_timings_cap(struct v4l2_subdev *sd)
  570. {
  571. return is_digital_input(sd) ? &adv7842_timings_cap_digital :
  572. &adv7842_timings_cap_analog;
  573. }
  574. /* ----------------------------------------------------------------------- */
  575. static void adv7842_delayed_work_enable_hotplug(struct work_struct *work)
  576. {
  577. struct delayed_work *dwork = to_delayed_work(work);
  578. struct adv7842_state *state = container_of(dwork,
  579. struct adv7842_state, delayed_work_enable_hotplug);
  580. struct v4l2_subdev *sd = &state->sd;
  581. int present = state->hdmi_edid.present;
  582. u8 mask = 0;
  583. v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n",
  584. __func__, present);
  585. if (present & (0x04 << ADV7842_EDID_PORT_A))
  586. mask |= 0x20;
  587. if (present & (0x04 << ADV7842_EDID_PORT_B))
  588. mask |= 0x10;
  589. io_write_and_or(sd, 0x20, 0xcf, mask);
  590. }
  591. static int edid_write_vga_segment(struct v4l2_subdev *sd)
  592. {
  593. struct i2c_client *client = v4l2_get_subdevdata(sd);
  594. struct adv7842_state *state = to_state(sd);
  595. const u8 *val = state->vga_edid.edid;
  596. int err = 0;
  597. int i;
  598. v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__);
  599. /* HPA disable on port A and B */
  600. io_write_and_or(sd, 0x20, 0xcf, 0x00);
  601. /* Disable I2C access to internal EDID ram from VGA DDC port */
  602. rep_write_and_or(sd, 0x7f, 0x7f, 0x00);
  603. /* edid segment pointer '1' for VGA port */
  604. rep_write_and_or(sd, 0x77, 0xef, 0x10);
  605. for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
  606. err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
  607. I2C_SMBUS_BLOCK_MAX, val + i);
  608. if (err)
  609. return err;
  610. /* Calculates the checksums and enables I2C access
  611. * to internal EDID ram from VGA DDC port.
  612. */
  613. rep_write_and_or(sd, 0x7f, 0x7f, 0x80);
  614. for (i = 0; i < 1000; i++) {
  615. if (rep_read(sd, 0x79) & 0x20)
  616. break;
  617. mdelay(1);
  618. }
  619. if (i == 1000) {
  620. v4l_err(client, "error enabling edid on VGA port\n");
  621. return -EIO;
  622. }
  623. /* enable hotplug after 200 ms */
  624. queue_delayed_work(state->work_queues,
  625. &state->delayed_work_enable_hotplug, HZ / 5);
  626. return 0;
  627. }
  628. static int edid_spa_location(const u8 *edid)
  629. {
  630. u8 d;
  631. /*
  632. * TODO, improve and update for other CEA extensions
  633. * currently only for 1 segment (256 bytes),
  634. * i.e. 1 extension block and CEA revision 3.
  635. */
  636. if ((edid[0x7e] != 1) ||
  637. (edid[0x80] != 0x02) ||
  638. (edid[0x81] != 0x03)) {
  639. return -EINVAL;
  640. }
  641. /*
  642. * search Vendor Specific Data Block (tag 3)
  643. */
  644. d = edid[0x82] & 0x7f;
  645. if (d > 4) {
  646. int i = 0x84;
  647. int end = 0x80 + d;
  648. do {
  649. u8 tag = edid[i]>>5;
  650. u8 len = edid[i] & 0x1f;
  651. if ((tag == 3) && (len >= 5))
  652. return i + 4;
  653. i += len + 1;
  654. } while (i < end);
  655. }
  656. return -EINVAL;
  657. }
  658. static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port)
  659. {
  660. struct i2c_client *client = v4l2_get_subdevdata(sd);
  661. struct adv7842_state *state = to_state(sd);
  662. const u8 *val = state->hdmi_edid.edid;
  663. int spa_loc = edid_spa_location(val);
  664. int err = 0;
  665. int i;
  666. v4l2_dbg(2, debug, sd, "%s: write EDID on port %c (spa at 0x%x)\n",
  667. __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B', spa_loc);
  668. /* HPA disable on port A and B */
  669. io_write_and_or(sd, 0x20, 0xcf, 0x00);
  670. /* Disable I2C access to internal EDID ram from HDMI DDC ports */
  671. rep_write_and_or(sd, 0x77, 0xf3, 0x00);
  672. if (!state->hdmi_edid.present)
  673. return 0;
  674. /* edid segment pointer '0' for HDMI ports */
  675. rep_write_and_or(sd, 0x77, 0xef, 0x00);
  676. for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
  677. err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
  678. I2C_SMBUS_BLOCK_MAX, val + i);
  679. if (err)
  680. return err;
  681. if (spa_loc < 0)
  682. spa_loc = 0xc0; /* Default value [REF_02, p. 199] */
  683. if (port == ADV7842_EDID_PORT_A) {
  684. rep_write(sd, 0x72, val[spa_loc]);
  685. rep_write(sd, 0x73, val[spa_loc + 1]);
  686. } else {
  687. rep_write(sd, 0x74, val[spa_loc]);
  688. rep_write(sd, 0x75, val[spa_loc + 1]);
  689. }
  690. rep_write(sd, 0x76, spa_loc & 0xff);
  691. rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
  692. /* Calculates the checksums and enables I2C access to internal
  693. * EDID ram from HDMI DDC ports
  694. */
  695. rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present);
  696. for (i = 0; i < 1000; i++) {
  697. if (rep_read(sd, 0x7d) & state->hdmi_edid.present)
  698. break;
  699. mdelay(1);
  700. }
  701. if (i == 1000) {
  702. v4l_err(client, "error enabling edid on port %c\n",
  703. (port == ADV7842_EDID_PORT_A) ? 'A' : 'B');
  704. return -EIO;
  705. }
  706. /* enable hotplug after 200 ms */
  707. queue_delayed_work(state->work_queues,
  708. &state->delayed_work_enable_hotplug, HZ / 5);
  709. return 0;
  710. }
  711. /* ----------------------------------------------------------------------- */
  712. #ifdef CONFIG_VIDEO_ADV_DEBUG
  713. static void adv7842_inv_register(struct v4l2_subdev *sd)
  714. {
  715. v4l2_info(sd, "0x000-0x0ff: IO Map\n");
  716. v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
  717. v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
  718. v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
  719. v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n");
  720. v4l2_info(sd, "0x500-0x5ff: SDP Map\n");
  721. v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
  722. v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
  723. v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
  724. v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
  725. v4l2_info(sd, "0xa00-0xaff: CP Map\n");
  726. v4l2_info(sd, "0xb00-0xbff: VDP Map\n");
  727. }
  728. static int adv7842_g_register(struct v4l2_subdev *sd,
  729. struct v4l2_dbg_register *reg)
  730. {
  731. reg->size = 1;
  732. switch (reg->reg >> 8) {
  733. case 0:
  734. reg->val = io_read(sd, reg->reg & 0xff);
  735. break;
  736. case 1:
  737. reg->val = avlink_read(sd, reg->reg & 0xff);
  738. break;
  739. case 2:
  740. reg->val = cec_read(sd, reg->reg & 0xff);
  741. break;
  742. case 3:
  743. reg->val = infoframe_read(sd, reg->reg & 0xff);
  744. break;
  745. case 4:
  746. reg->val = sdp_io_read(sd, reg->reg & 0xff);
  747. break;
  748. case 5:
  749. reg->val = sdp_read(sd, reg->reg & 0xff);
  750. break;
  751. case 6:
  752. reg->val = afe_read(sd, reg->reg & 0xff);
  753. break;
  754. case 7:
  755. reg->val = rep_read(sd, reg->reg & 0xff);
  756. break;
  757. case 8:
  758. reg->val = edid_read(sd, reg->reg & 0xff);
  759. break;
  760. case 9:
  761. reg->val = hdmi_read(sd, reg->reg & 0xff);
  762. break;
  763. case 0xa:
  764. reg->val = cp_read(sd, reg->reg & 0xff);
  765. break;
  766. case 0xb:
  767. reg->val = vdp_read(sd, reg->reg & 0xff);
  768. break;
  769. default:
  770. v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
  771. adv7842_inv_register(sd);
  772. break;
  773. }
  774. return 0;
  775. }
  776. static int adv7842_s_register(struct v4l2_subdev *sd,
  777. const struct v4l2_dbg_register *reg)
  778. {
  779. u8 val = reg->val & 0xff;
  780. switch (reg->reg >> 8) {
  781. case 0:
  782. io_write(sd, reg->reg & 0xff, val);
  783. break;
  784. case 1:
  785. avlink_write(sd, reg->reg & 0xff, val);
  786. break;
  787. case 2:
  788. cec_write(sd, reg->reg & 0xff, val);
  789. break;
  790. case 3:
  791. infoframe_write(sd, reg->reg & 0xff, val);
  792. break;
  793. case 4:
  794. sdp_io_write(sd, reg->reg & 0xff, val);
  795. break;
  796. case 5:
  797. sdp_write(sd, reg->reg & 0xff, val);
  798. break;
  799. case 6:
  800. afe_write(sd, reg->reg & 0xff, val);
  801. break;
  802. case 7:
  803. rep_write(sd, reg->reg & 0xff, val);
  804. break;
  805. case 8:
  806. edid_write(sd, reg->reg & 0xff, val);
  807. break;
  808. case 9:
  809. hdmi_write(sd, reg->reg & 0xff, val);
  810. break;
  811. case 0xa:
  812. cp_write(sd, reg->reg & 0xff, val);
  813. break;
  814. case 0xb:
  815. vdp_write(sd, reg->reg & 0xff, val);
  816. break;
  817. default:
  818. v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
  819. adv7842_inv_register(sd);
  820. break;
  821. }
  822. return 0;
  823. }
  824. #endif
  825. static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
  826. {
  827. struct adv7842_state *state = to_state(sd);
  828. int prev = v4l2_ctrl_g_ctrl(state->detect_tx_5v_ctrl);
  829. u8 reg_io_6f = io_read(sd, 0x6f);
  830. int val = 0;
  831. if (reg_io_6f & 0x02)
  832. val |= 1; /* port A */
  833. if (reg_io_6f & 0x01)
  834. val |= 2; /* port B */
  835. v4l2_dbg(1, debug, sd, "%s: 0x%x -> 0x%x\n", __func__, prev, val);
  836. if (val != prev)
  837. return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, val);
  838. return 0;
  839. }
  840. static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
  841. u8 prim_mode,
  842. const struct adv7842_video_standards *predef_vid_timings,
  843. const struct v4l2_dv_timings *timings)
  844. {
  845. int i;
  846. for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
  847. if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
  848. is_digital_input(sd) ? 250000 : 1000000))
  849. continue;
  850. /* video std */
  851. io_write(sd, 0x00, predef_vid_timings[i].vid_std);
  852. /* v_freq and prim mode */
  853. io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);
  854. return 0;
  855. }
  856. return -1;
  857. }
  858. static int configure_predefined_video_timings(struct v4l2_subdev *sd,
  859. struct v4l2_dv_timings *timings)
  860. {
  861. struct adv7842_state *state = to_state(sd);
  862. int err;
  863. v4l2_dbg(1, debug, sd, "%s\n", __func__);
  864. /* reset to default values */
  865. io_write(sd, 0x16, 0x43);
  866. io_write(sd, 0x17, 0x5a);
  867. /* disable embedded syncs for auto graphics mode */
  868. cp_write_and_or(sd, 0x81, 0xef, 0x00);
  869. cp_write(sd, 0x26, 0x00);
  870. cp_write(sd, 0x27, 0x00);
  871. cp_write(sd, 0x28, 0x00);
  872. cp_write(sd, 0x29, 0x00);
  873. cp_write(sd, 0x8f, 0x40);
  874. cp_write(sd, 0x90, 0x00);
  875. cp_write(sd, 0xa5, 0x00);
  876. cp_write(sd, 0xa6, 0x00);
  877. cp_write(sd, 0xa7, 0x00);
  878. cp_write(sd, 0xab, 0x00);
  879. cp_write(sd, 0xac, 0x00);
  880. switch (state->mode) {
  881. case ADV7842_MODE_COMP:
  882. case ADV7842_MODE_RGB:
  883. err = find_and_set_predefined_video_timings(sd,
  884. 0x01, adv7842_prim_mode_comp, timings);
  885. if (err)
  886. err = find_and_set_predefined_video_timings(sd,
  887. 0x02, adv7842_prim_mode_gr, timings);
  888. break;
  889. case ADV7842_MODE_HDMI:
  890. err = find_and_set_predefined_video_timings(sd,
  891. 0x05, adv7842_prim_mode_hdmi_comp, timings);
  892. if (err)
  893. err = find_and_set_predefined_video_timings(sd,
  894. 0x06, adv7842_prim_mode_hdmi_gr, timings);
  895. break;
  896. default:
  897. v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
  898. __func__, state->mode);
  899. err = -1;
  900. break;
  901. }
  902. return err;
  903. }
  904. static void configure_custom_video_timings(struct v4l2_subdev *sd,
  905. const struct v4l2_bt_timings *bt)
  906. {
  907. struct adv7842_state *state = to_state(sd);
  908. struct i2c_client *client = v4l2_get_subdevdata(sd);
  909. u32 width = htotal(bt);
  910. u32 height = vtotal(bt);
  911. u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
  912. u16 cp_start_eav = width - bt->hfrontporch;
  913. u16 cp_start_vbi = height - bt->vfrontporch + 1;
  914. u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1;
  915. u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
  916. ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
  917. const u8 pll[2] = {
  918. 0xc0 | ((width >> 8) & 0x1f),
  919. width & 0xff
  920. };
  921. v4l2_dbg(2, debug, sd, "%s\n", __func__);
  922. switch (state->mode) {
  923. case ADV7842_MODE_COMP:
  924. case ADV7842_MODE_RGB:
  925. /* auto graphics */
  926. io_write(sd, 0x00, 0x07); /* video std */
  927. io_write(sd, 0x01, 0x02); /* prim mode */
  928. /* enable embedded syncs for auto graphics mode */
  929. cp_write_and_or(sd, 0x81, 0xef, 0x10);
  930. /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
  931. /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
  932. /* IO-map reg. 0x16 and 0x17 should be written in sequence */
  933. if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
  934. v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
  935. break;
  936. }
  937. /* active video - horizontal timing */
  938. cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf);
  939. cp_write(sd, 0x27, (cp_start_sav & 0xff));
  940. cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf);
  941. cp_write(sd, 0x29, (cp_start_eav & 0xff));
  942. /* active video - vertical timing */
  943. cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
  944. cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
  945. ((cp_end_vbi >> 8) & 0xf));
  946. cp_write(sd, 0xa7, cp_end_vbi & 0xff);
  947. break;
  948. case ADV7842_MODE_HDMI:
  949. /* set default prim_mode/vid_std for HDMI
  950. according to [REF_03, c. 4.2] */
  951. io_write(sd, 0x00, 0x02); /* video std */
  952. io_write(sd, 0x01, 0x06); /* prim mode */
  953. break;
  954. default:
  955. v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
  956. __func__, state->mode);
  957. break;
  958. }
  959. cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
  960. cp_write(sd, 0x90, ch1_fr_ll & 0xff);
  961. cp_write(sd, 0xab, (height >> 4) & 0xff);
  962. cp_write(sd, 0xac, (height & 0x0f) << 4);
  963. }
  964. static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
  965. {
  966. struct adv7842_state *state = to_state(sd);
  967. u8 offset_buf[4];
  968. if (auto_offset) {
  969. offset_a = 0x3ff;
  970. offset_b = 0x3ff;
  971. offset_c = 0x3ff;
  972. }
  973. v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
  974. __func__, auto_offset ? "Auto" : "Manual",
  975. offset_a, offset_b, offset_c);
  976. offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
  977. offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
  978. offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
  979. offset_buf[3] = offset_c & 0x0ff;
  980. /* Registers must be written in this order with no i2c access in between */
  981. if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf))
  982. v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
  983. }
  984. static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
  985. {
  986. struct adv7842_state *state = to_state(sd);
  987. u8 gain_buf[4];
  988. u8 gain_man = 1;
  989. u8 agc_mode_man = 1;
  990. if (auto_gain) {
  991. gain_man = 0;
  992. agc_mode_man = 0;
  993. gain_a = 0x100;
  994. gain_b = 0x100;
  995. gain_c = 0x100;
  996. }
  997. v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
  998. __func__, auto_gain ? "Auto" : "Manual",
  999. gain_a, gain_b, gain_c);
  1000. gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
  1001. gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
  1002. gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
  1003. gain_buf[3] = ((gain_c & 0x0ff));
  1004. /* Registers must be written in this order with no i2c access in between */
  1005. if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf))
  1006. v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
  1007. }
  1008. static void set_rgb_quantization_range(struct v4l2_subdev *sd)
  1009. {
  1010. struct adv7842_state *state = to_state(sd);
  1011. bool rgb_output = io_read(sd, 0x02) & 0x02;
  1012. bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
  1013. v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
  1014. __func__, state->rgb_quantization_range,
  1015. rgb_output, hdmi_signal);
  1016. adv7842_set_gain(sd, true, 0x0, 0x0, 0x0);
  1017. adv7842_set_offset(sd, true, 0x0, 0x0, 0x0);
  1018. switch (state->rgb_quantization_range) {
  1019. case V4L2_DV_RGB_RANGE_AUTO:
  1020. if (state->mode == ADV7842_MODE_RGB) {
  1021. /* Receiving analog RGB signal
  1022. * Set RGB full range (0-255) */
  1023. io_write_and_or(sd, 0x02, 0x0f, 0x10);
  1024. break;
  1025. }
  1026. if (state->mode == ADV7842_MODE_COMP) {
  1027. /* Receiving analog YPbPr signal
  1028. * Set automode */
  1029. io_write_and_or(sd, 0x02, 0x0f, 0xf0);
  1030. break;
  1031. }
  1032. if (hdmi_signal) {
  1033. /* Receiving HDMI signal
  1034. * Set automode */
  1035. io_write_and_or(sd, 0x02, 0x0f, 0xf0);
  1036. break;
  1037. }
  1038. /* Receiving DVI-D signal
  1039. * ADV7842 selects RGB limited range regardless of
  1040. * input format (CE/IT) in automatic mode */
  1041. if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
  1042. /* RGB limited range (16-235) */
  1043. io_write_and_or(sd, 0x02, 0x0f, 0x00);
  1044. } else {
  1045. /* RGB full range (0-255) */
  1046. io_write_and_or(sd, 0x02, 0x0f, 0x10);
  1047. if (is_digital_input(sd) && rgb_output) {
  1048. adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
  1049. } else {
  1050. adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
  1051. adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
  1052. }
  1053. }
  1054. break;
  1055. case V4L2_DV_RGB_RANGE_LIMITED:
  1056. if (state->mode == ADV7842_MODE_COMP) {
  1057. /* YCrCb limited range (16-235) */
  1058. io_write_and_or(sd, 0x02, 0x0f, 0x20);
  1059. break;
  1060. }
  1061. /* RGB limited range (16-235) */
  1062. io_write_and_or(sd, 0x02, 0x0f, 0x00);
  1063. break;
  1064. case V4L2_DV_RGB_RANGE_FULL:
  1065. if (state->mode == ADV7842_MODE_COMP) {
  1066. /* YCrCb full range (0-255) */
  1067. io_write_and_or(sd, 0x02, 0x0f, 0x60);
  1068. break;
  1069. }
  1070. /* RGB full range (0-255) */
  1071. io_write_and_or(sd, 0x02, 0x0f, 0x10);
  1072. if (is_analog_input(sd) || hdmi_signal)
  1073. break;
  1074. /* Adjust gain/offset for DVI-D signals only */
  1075. if (rgb_output) {
  1076. adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
  1077. } else {
  1078. adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
  1079. adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
  1080. }
  1081. break;
  1082. }
  1083. }
  1084. static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl)
  1085. {
  1086. struct v4l2_subdev *sd = to_sd(ctrl);
  1087. struct adv7842_state *state = to_state(sd);
  1088. /* TODO SDP ctrls
  1089. contrast/brightness/hue/free run is acting a bit strange,
  1090. not sure if sdp csc is correct.
  1091. */
  1092. switch (ctrl->id) {
  1093. /* standard ctrls */
  1094. case V4L2_CID_BRIGHTNESS:
  1095. cp_write(sd, 0x3c, ctrl->val);
  1096. sdp_write(sd, 0x14, ctrl->val);
  1097. /* ignore lsb sdp 0x17[3:2] */
  1098. return 0;
  1099. case V4L2_CID_CONTRAST:
  1100. cp_write(sd, 0x3a, ctrl->val);
  1101. sdp_write(sd, 0x13, ctrl->val);
  1102. /* ignore lsb sdp 0x17[1:0] */
  1103. return 0;
  1104. case V4L2_CID_SATURATION:
  1105. cp_write(sd, 0x3b, ctrl->val);
  1106. sdp_write(sd, 0x15, ctrl->val);
  1107. /* ignore lsb sdp 0x17[5:4] */
  1108. return 0;
  1109. case V4L2_CID_HUE:
  1110. cp_write(sd, 0x3d, ctrl->val);
  1111. sdp_write(sd, 0x16, ctrl->val);
  1112. /* ignore lsb sdp 0x17[7:6] */
  1113. return 0;
  1114. /* custom ctrls */
  1115. case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
  1116. afe_write(sd, 0xc8, ctrl->val);
  1117. return 0;
  1118. case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
  1119. cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
  1120. sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2));
  1121. return 0;
  1122. case V4L2_CID_ADV_RX_FREE_RUN_COLOR: {
  1123. u8 R = (ctrl->val & 0xff0000) >> 16;
  1124. u8 G = (ctrl->val & 0x00ff00) >> 8;
  1125. u8 B = (ctrl->val & 0x0000ff);
  1126. /* RGB -> YUV, numerical approximation */
  1127. int Y = 66 * R + 129 * G + 25 * B;
  1128. int U = -38 * R - 74 * G + 112 * B;
  1129. int V = 112 * R - 94 * G - 18 * B;
  1130. /* Scale down to 8 bits with rounding */
  1131. Y = (Y + 128) >> 8;
  1132. U = (U + 128) >> 8;
  1133. V = (V + 128) >> 8;
  1134. /* make U,V positive */
  1135. Y += 16;
  1136. U += 128;
  1137. V += 128;
  1138. v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B);
  1139. v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V);
  1140. /* CP */
  1141. cp_write(sd, 0xc1, R);
  1142. cp_write(sd, 0xc0, G);
  1143. cp_write(sd, 0xc2, B);
  1144. /* SDP */
  1145. sdp_write(sd, 0xde, Y);
  1146. sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f));
  1147. return 0;
  1148. }
  1149. case V4L2_CID_DV_RX_RGB_RANGE:
  1150. state->rgb_quantization_range = ctrl->val;
  1151. set_rgb_quantization_range(sd);
  1152. return 0;
  1153. }
  1154. return -EINVAL;
  1155. }
  1156. static inline bool no_power(struct v4l2_subdev *sd)
  1157. {
  1158. return io_read(sd, 0x0c) & 0x24;
  1159. }
  1160. static inline bool no_cp_signal(struct v4l2_subdev *sd)
  1161. {
  1162. return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80);
  1163. }
  1164. static inline bool is_hdmi(struct v4l2_subdev *sd)
  1165. {
  1166. return hdmi_read(sd, 0x05) & 0x80;
  1167. }
  1168. static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status)
  1169. {
  1170. struct adv7842_state *state = to_state(sd);
  1171. *status = 0;
  1172. if (io_read(sd, 0x0c) & 0x24)
  1173. *status |= V4L2_IN_ST_NO_POWER;
  1174. if (state->mode == ADV7842_MODE_SDP) {
  1175. /* status from SDP block */
  1176. if (!(sdp_read(sd, 0x5A) & 0x01))
  1177. *status |= V4L2_IN_ST_NO_SIGNAL;
  1178. v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n",
  1179. __func__, *status);
  1180. return 0;
  1181. }
  1182. /* status from CP block */
  1183. if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 ||
  1184. !(cp_read(sd, 0xb1) & 0x80))
  1185. /* TODO channel 2 */
  1186. *status |= V4L2_IN_ST_NO_SIGNAL;
  1187. if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))
  1188. *status |= V4L2_IN_ST_NO_SIGNAL;
  1189. v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n",
  1190. __func__, *status);
  1191. return 0;
  1192. }
  1193. struct stdi_readback {
  1194. u16 bl, lcf, lcvs;
  1195. u8 hs_pol, vs_pol;
  1196. bool interlaced;
  1197. };
  1198. static int stdi2dv_timings(struct v4l2_subdev *sd,
  1199. struct stdi_readback *stdi,
  1200. struct v4l2_dv_timings *timings)
  1201. {
  1202. struct adv7842_state *state = to_state(sd);
  1203. u32 hfreq = (ADV7842_fsc * 8) / stdi->bl;
  1204. u32 pix_clk;
  1205. int i;
  1206. for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
  1207. const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
  1208. if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
  1209. adv7842_get_dv_timings_cap(sd),
  1210. adv7842_check_dv_timings, NULL))
  1211. continue;
  1212. if (vtotal(bt) != stdi->lcf + 1)
  1213. continue;
  1214. if (bt->vsync != stdi->lcvs)
  1215. continue;
  1216. pix_clk = hfreq * htotal(bt);
  1217. if ((pix_clk < bt->pixelclock + 1000000) &&
  1218. (pix_clk > bt->pixelclock - 1000000)) {
  1219. *timings = v4l2_dv_timings_presets[i];
  1220. return 0;
  1221. }
  1222. }
  1223. if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,
  1224. (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
  1225. (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
  1226. false, timings))
  1227. return 0;
  1228. if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
  1229. (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
  1230. (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
  1231. false, state->aspect_ratio, timings))
  1232. return 0;
  1233. v4l2_dbg(2, debug, sd,
  1234. "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
  1235. __func__, stdi->lcvs, stdi->lcf, stdi->bl,
  1236. stdi->hs_pol, stdi->vs_pol);
  1237. return -1;
  1238. }
  1239. static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
  1240. {
  1241. u32 status;
  1242. adv7842_g_input_status(sd, &status);
  1243. if (status & V4L2_IN_ST_NO_SIGNAL) {
  1244. v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__);
  1245. return -ENOLINK;
  1246. }
  1247. stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
  1248. stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
  1249. stdi->lcvs = cp_read(sd, 0xb3) >> 3;
  1250. if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) {
  1251. stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
  1252. ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
  1253. stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
  1254. ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
  1255. } else {
  1256. stdi->hs_pol = 'x';
  1257. stdi->vs_pol = 'x';
  1258. }
  1259. stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false;
  1260. if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
  1261. v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
  1262. return -ENOLINK;
  1263. }
  1264. v4l2_dbg(2, debug, sd,
  1265. "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
  1266. __func__, stdi->lcf, stdi->bl, stdi->lcvs,
  1267. stdi->hs_pol, stdi->vs_pol,
  1268. stdi->interlaced ? "interlaced" : "progressive");
  1269. return 0;
  1270. }
  1271. static int adv7842_enum_dv_timings(struct v4l2_subdev *sd,
  1272. struct v4l2_enum_dv_timings *timings)
  1273. {
  1274. if (timings->pad != 0)
  1275. return -EINVAL;
  1276. return v4l2_enum_dv_timings_cap(timings,
  1277. adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL);
  1278. }
  1279. static int adv7842_dv_timings_cap(struct v4l2_subdev *sd,
  1280. struct v4l2_dv_timings_cap *cap)
  1281. {
  1282. if (cap->pad != 0)
  1283. return -EINVAL;
  1284. *cap = *adv7842_get_dv_timings_cap(sd);
  1285. return 0;
  1286. }
  1287. /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
  1288. if the format is listed in adv7842_timings[] */
  1289. static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
  1290. struct v4l2_dv_timings *timings)
  1291. {
  1292. v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd),
  1293. is_digital_input(sd) ? 250000 : 1000000,
  1294. adv7842_check_dv_timings, NULL);
  1295. }
  1296. static int adv7842_query_dv_timings(struct v4l2_subdev *sd,
  1297. struct v4l2_dv_timings *timings)
  1298. {
  1299. struct adv7842_state *state = to_state(sd);
  1300. struct v4l2_bt_timings *bt = &timings->bt;
  1301. struct stdi_readback stdi = { 0 };
  1302. v4l2_dbg(1, debug, sd, "%s:\n", __func__);
  1303. memset(timings, 0, sizeof(struct v4l2_dv_timings));
  1304. /* SDP block */
  1305. if (state->mode == ADV7842_MODE_SDP)
  1306. return -ENODATA;
  1307. /* read STDI */
  1308. if (read_stdi(sd, &stdi)) {
  1309. state->restart_stdi_once = true;
  1310. v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
  1311. return -ENOLINK;
  1312. }
  1313. bt->interlaced = stdi.interlaced ?
  1314. V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
  1315. bt->standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
  1316. V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
  1317. if (is_digital_input(sd)) {
  1318. u32 freq;
  1319. timings->type = V4L2_DV_BT_656_1120;
  1320. bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
  1321. bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
  1322. freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000;
  1323. freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813);
  1324. if (is_hdmi(sd)) {
  1325. /* adjust for deep color mode */
  1326. freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8);
  1327. }
  1328. bt->pixelclock = freq;
  1329. bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
  1330. hdmi_read(sd, 0x21);
  1331. bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
  1332. hdmi_read(sd, 0x23);
  1333. bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
  1334. hdmi_read(sd, 0x25);
  1335. bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
  1336. hdmi_read(sd, 0x2b)) / 2;
  1337. bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
  1338. hdmi_read(sd, 0x2f)) / 2;
  1339. bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
  1340. hdmi_read(sd, 0x33)) / 2;
  1341. bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
  1342. ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
  1343. if (bt->interlaced == V4L2_DV_INTERLACED) {
  1344. bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
  1345. hdmi_read(sd, 0x0c);
  1346. bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
  1347. hdmi_read(sd, 0x2d)) / 2;
  1348. bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
  1349. hdmi_read(sd, 0x31)) / 2;
  1350. bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
  1351. hdmi_read(sd, 0x35)) / 2;
  1352. } else {
  1353. bt->il_vfrontporch = 0;
  1354. bt->il_vsync = 0;
  1355. bt->il_vbackporch = 0;
  1356. }
  1357. adv7842_fill_optional_dv_timings_fields(sd, timings);
  1358. } else {
  1359. /* find format
  1360. * Since LCVS values are inaccurate [REF_03, p. 339-340],
  1361. * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
  1362. */
  1363. if (!stdi2dv_timings(sd, &stdi, timings))
  1364. goto found;
  1365. stdi.lcvs += 1;
  1366. v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
  1367. if (!stdi2dv_timings(sd, &stdi, timings))
  1368. goto found;
  1369. stdi.lcvs -= 2;
  1370. v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
  1371. if (stdi2dv_timings(sd, &stdi, timings)) {
  1372. /*
  1373. * The STDI block may measure wrong values, especially
  1374. * for lcvs and lcf. If the driver can not find any
  1375. * valid timing, the STDI block is restarted to measure
  1376. * the video timings again. The function will return an
  1377. * error, but the restart of STDI will generate a new
  1378. * STDI interrupt and the format detection process will
  1379. * restart.
  1380. */
  1381. if (state->restart_stdi_once) {
  1382. v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
  1383. /* TODO restart STDI for Sync Channel 2 */
  1384. /* enter one-shot mode */
  1385. cp_write_and_or(sd, 0x86, 0xf9, 0x00);
  1386. /* trigger STDI restart */
  1387. cp_write_and_or(sd, 0x86, 0xf9, 0x04);
  1388. /* reset to continuous mode */
  1389. cp_write_and_or(sd, 0x86, 0xf9, 0x02);
  1390. state->restart_stdi_once = false;
  1391. return -ENOLINK;
  1392. }
  1393. v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
  1394. return -ERANGE;
  1395. }
  1396. state->restart_stdi_once = true;
  1397. }
  1398. found:
  1399. if (debug > 1)
  1400. v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:",
  1401. timings, true);
  1402. return 0;
  1403. }
  1404. static int adv7842_s_dv_timings(struct v4l2_subdev *sd,
  1405. struct v4l2_dv_timings *timings)
  1406. {
  1407. struct adv7842_state *state = to_state(sd);
  1408. struct v4l2_bt_timings *bt;
  1409. int err;
  1410. v4l2_dbg(1, debug, sd, "%s:\n", __func__);
  1411. if (state->mode == ADV7842_MODE_SDP)
  1412. return -ENODATA;
  1413. if (v4l2_match_dv_timings(&state->timings, timings, 0)) {
  1414. v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
  1415. return 0;
  1416. }
  1417. bt = &timings->bt;
  1418. if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd),
  1419. adv7842_check_dv_timings, NULL))
  1420. return -ERANGE;
  1421. adv7842_fill_optional_dv_timings_fields(sd, timings);
  1422. state->timings = *timings;
  1423. cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00);
  1424. /* Use prim_mode and vid_std when available */
  1425. err = configure_predefined_video_timings(sd, timings);
  1426. if (err) {
  1427. /* custom settings when the video format
  1428. does not have prim_mode/vid_std */
  1429. configure_custom_video_timings(sd, bt);
  1430. }
  1431. set_rgb_quantization_range(sd);
  1432. if (debug > 1)
  1433. v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ",
  1434. timings, true);
  1435. return 0;
  1436. }
  1437. static int adv7842_g_dv_timings(struct v4l2_subdev *sd,
  1438. struct v4l2_dv_timings *timings)
  1439. {
  1440. struct adv7842_state *state = to_state(sd);
  1441. if (state->mode == ADV7842_MODE_SDP)
  1442. return -ENODATA;
  1443. *timings = state->timings;
  1444. return 0;
  1445. }
  1446. static void enable_input(struct v4l2_subdev *sd)
  1447. {
  1448. struct adv7842_state *state = to_state(sd);
  1449. set_rgb_quantization_range(sd);
  1450. switch (state->mode) {
  1451. case ADV7842_MODE_SDP:
  1452. case ADV7842_MODE_COMP:
  1453. case ADV7842_MODE_RGB:
  1454. io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
  1455. break;
  1456. case ADV7842_MODE_HDMI:
  1457. hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
  1458. io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
  1459. hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */
  1460. break;
  1461. default:
  1462. v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
  1463. __func__, state->mode);
  1464. break;
  1465. }
  1466. }
  1467. static void disable_input(struct v4l2_subdev *sd)
  1468. {
  1469. hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */
  1470. msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */
  1471. io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
  1472. hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
  1473. }
  1474. static void sdp_csc_coeff(struct v4l2_subdev *sd,
  1475. const struct adv7842_sdp_csc_coeff *c)
  1476. {
  1477. /* csc auto/manual */
  1478. sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);
  1479. if (!c->manual)
  1480. return;
  1481. /* csc scaling */
  1482. sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);
  1483. /* A coeff */
  1484. sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);
  1485. sdp_io_write(sd, 0xe1, c->A1);
  1486. sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);
  1487. sdp_io_write(sd, 0xe3, c->A2);
  1488. sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8);
  1489. sdp_io_write(sd, 0xe5, c->A3);
  1490. /* A scale */
  1491. sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8);
  1492. sdp_io_write(sd, 0xe7, c->A4);
  1493. /* B coeff */
  1494. sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8);
  1495. sdp_io_write(sd, 0xe9, c->B1);
  1496. sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);
  1497. sdp_io_write(sd, 0xeb, c->B2);
  1498. sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8);
  1499. sdp_io_write(sd, 0xed, c->B3);
  1500. /* B scale */
  1501. sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8);
  1502. sdp_io_write(sd, 0xef, c->B4);
  1503. /* C coeff */
  1504. sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);
  1505. sdp_io_write(sd, 0xf1, c->C1);
  1506. sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);
  1507. sdp_io_write(sd, 0xf3, c->C2);
  1508. sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8);
  1509. sdp_io_write(sd, 0xf5, c->C3);
  1510. /* C scale */
  1511. sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8);
  1512. sdp_io_write(sd, 0xf7, c->C4);
  1513. }
  1514. static void select_input(struct v4l2_subdev *sd,
  1515. enum adv7842_vid_std_select vid_std_select)
  1516. {
  1517. struct adv7842_state *state = to_state(sd);
  1518. switch (state->mode) {
  1519. case ADV7842_MODE_SDP:
  1520. io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */
  1521. io_write(sd, 0x01, 0); /* prim mode */
  1522. /* enable embedded syncs for auto graphics mode */
  1523. cp_write_and_or(sd, 0x81, 0xef, 0x10);
  1524. afe_write(sd, 0x00, 0x00); /* power up ADC */
  1525. afe_write(sd, 0xc8, 0x00); /* phase control */
  1526. io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
  1527. /* script says register 0xde, which don't exist in manual */
  1528. /* Manual analog input muxing mode, CVBS (6.4)*/
  1529. afe_write_and_or(sd, 0x02, 0x7f, 0x80);
  1530. if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) {
  1531. afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
  1532. afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
  1533. } else {
  1534. afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
  1535. afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/
  1536. }
  1537. afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */
  1538. afe_write(sd, 0x12, 0x63); /* ADI recommend write */
  1539. sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */
  1540. sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */
  1541. /* SDP recommended settings */
  1542. sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */
  1543. sdp_write(sd, 0x01, 0x00); /* Pedestal Off */
  1544. sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */
  1545. sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */
  1546. sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */
  1547. sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */
  1548. sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */
  1549. sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */
  1550. sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */
  1551. /* deinterlacer enabled and 3D comb */
  1552. sdp_write_and_or(sd, 0x12, 0xf6, 0x09);
  1553. break;
  1554. case ADV7842_MODE_COMP:
  1555. case ADV7842_MODE_RGB:
  1556. /* Automatic analog input muxing mode */
  1557. afe_write_and_or(sd, 0x02, 0x7f, 0x00);
  1558. /* set mode and select free run resolution */
  1559. io_write(sd, 0x00, vid_std_select); /* video std */
  1560. io_write(sd, 0x01, 0x02); /* prim mode */
  1561. cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs
  1562. for auto graphics mode */
  1563. afe_write(sd, 0x00, 0x00); /* power up ADC */
  1564. afe_write(sd, 0xc8, 0x00); /* phase control */
  1565. if (state->mode == ADV7842_MODE_COMP) {
  1566. /* force to YCrCb */
  1567. io_write_and_or(sd, 0x02, 0x0f, 0x60);
  1568. } else {
  1569. /* force to RGB */
  1570. io_write_and_or(sd, 0x02, 0x0f, 0x10);
  1571. }
  1572. /* set ADI recommended settings for digitizer */
  1573. /* "ADV7842 Register Settings Recommendations
  1574. * (rev. 1.8, November 2010)" p. 9. */
  1575. afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */
  1576. afe_write(sd, 0x12, 0x63); /* ADC Range improvement */
  1577. /* set to default gain for RGB */
  1578. cp_write(sd, 0x73, 0x10);
  1579. cp_write(sd, 0x74, 0x04);
  1580. cp_write(sd, 0x75, 0x01);
  1581. cp_write(sd, 0x76, 0x00);
  1582. cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
  1583. cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
  1584. cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
  1585. break;
  1586. case ADV7842_MODE_HDMI:
  1587. /* Automatic analog input muxing mode */
  1588. afe_write_and_or(sd, 0x02, 0x7f, 0x00);
  1589. /* set mode and select free run resolution */
  1590. if (state->hdmi_port_a)
  1591. hdmi_write(sd, 0x00, 0x02); /* select port A */
  1592. else
  1593. hdmi_write(sd, 0x00, 0x03); /* select port B */
  1594. io_write(sd, 0x00, vid_std_select); /* video std */
  1595. io_write(sd, 0x01, 5); /* prim mode */
  1596. cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs
  1597. for auto graphics mode */
  1598. /* set ADI recommended settings for HDMI: */
  1599. /* "ADV7842 Register Settings Recommendations
  1600. * (rev. 1.8, November 2010)" p. 3. */
  1601. hdmi_write(sd, 0xc0, 0x00);
  1602. hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */
  1603. hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */
  1604. hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */
  1605. hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */
  1606. hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
  1607. hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
  1608. hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */
  1609. hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */
  1610. hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,
  1611. Improve robustness */
  1612. hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */
  1613. hdmi_write(sd, 0x85, 0x1f); /* equaliser */
  1614. hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */
  1615. hdmi_write(sd, 0x89, 0x04); /* equaliser */
  1616. hdmi_write(sd, 0x8a, 0x1e); /* equaliser */
  1617. hdmi_write(sd, 0x93, 0x04); /* equaliser */
  1618. hdmi_write(sd, 0x94, 0x1e); /* equaliser */
  1619. hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */
  1620. hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */
  1621. hdmi_write(sd, 0x9d, 0x02); /* equaliser */
  1622. afe_write(sd, 0x00, 0xff); /* power down ADC */
  1623. afe_write(sd, 0xc8, 0x40); /* phase control */
  1624. /* set to default gain for HDMI */
  1625. cp_write(sd, 0x73, 0x10);
  1626. cp_write(sd, 0x74, 0x04);
  1627. cp_write(sd, 0x75, 0x01);
  1628. cp_write(sd, 0x76, 0x00);
  1629. /* reset ADI recommended settings for digitizer */
  1630. /* "ADV7842 Register Settings Recommendations
  1631. * (rev. 2.5, June 2010)" p. 17. */
  1632. afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
  1633. afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
  1634. cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
  1635. /* CP coast control */
  1636. cp_write(sd, 0xc3, 0x33); /* Component mode */
  1637. /* color space conversion, autodetect color space */
  1638. io_write_and_or(sd, 0x02, 0x0f, 0xf0);
  1639. break;
  1640. default:
  1641. v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
  1642. __func__, state->mode);
  1643. break;
  1644. }
  1645. }
  1646. static int adv7842_s_routing(struct v4l2_subdev *sd,
  1647. u32 input, u32 output, u32 config)
  1648. {
  1649. struct adv7842_state *state = to_state(sd);
  1650. v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input);
  1651. switch (input) {
  1652. case ADV7842_SELECT_HDMI_PORT_A:
  1653. state->mode = ADV7842_MODE_HDMI;
  1654. state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
  1655. state->hdmi_port_a = true;
  1656. break;
  1657. case ADV7842_SELECT_HDMI_PORT_B:
  1658. state->mode = ADV7842_MODE_HDMI;
  1659. state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
  1660. state->hdmi_port_a = false;
  1661. break;
  1662. case ADV7842_SELECT_VGA_COMP:
  1663. state->mode = ADV7842_MODE_COMP;
  1664. state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
  1665. break;
  1666. case ADV7842_SELECT_VGA_RGB:
  1667. state->mode = ADV7842_MODE_RGB;
  1668. state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
  1669. break;
  1670. case ADV7842_SELECT_SDP_CVBS:
  1671. state->mode = ADV7842_MODE_SDP;
  1672. state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1;
  1673. break;
  1674. case ADV7842_SELECT_SDP_YC:
  1675. state->mode = ADV7842_MODE_SDP;
  1676. state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1;
  1677. break;
  1678. default:
  1679. return -EINVAL;
  1680. }
  1681. disable_input(sd);
  1682. select_input(sd, state->vid_std_select);
  1683. enable_input(sd);
  1684. v4l2_subdev_notify_event(sd, &adv7842_ev_fmt);
  1685. return 0;
  1686. }
  1687. static int adv7842_enum_mbus_code(struct v4l2_subdev *sd,
  1688. struct v4l2_subdev_pad_config *cfg,
  1689. struct v4l2_subdev_mbus_code_enum *code)
  1690. {
  1691. if (code->index >= ARRAY_SIZE(adv7842_formats))
  1692. return -EINVAL;
  1693. code->code = adv7842_formats[code->index].code;
  1694. return 0;
  1695. }
  1696. static void adv7842_fill_format(struct adv7842_state *state,
  1697. struct v4l2_mbus_framefmt *format)
  1698. {
  1699. memset(format, 0, sizeof(*format));
  1700. format->width = state->timings.bt.width;
  1701. format->height = state->timings.bt.height;
  1702. format->field = V4L2_FIELD_NONE;
  1703. format->colorspace = V4L2_COLORSPACE_SRGB;
  1704. if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
  1705. format->colorspace = (state->timings.bt.height <= 576) ?
  1706. V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
  1707. }
  1708. /*
  1709. * Compute the op_ch_sel value required to obtain on the bus the component order
  1710. * corresponding to the selected format taking into account bus reordering
  1711. * applied by the board at the output of the device.
  1712. *
  1713. * The following table gives the op_ch_value from the format component order
  1714. * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
  1715. * adv7842_bus_order value in row).
  1716. *
  1717. * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
  1718. * ----------+-------------------------------------------------
  1719. * RGB (NOP) | GBR GRB BGR RGB BRG RBG
  1720. * GRB (1-2) | BGR RGB GBR GRB RBG BRG
  1721. * RBG (2-3) | GRB GBR BRG RBG BGR RGB
  1722. * BGR (1-3) | RBG BRG RGB BGR GRB GBR
  1723. * BRG (ROR) | BRG RBG GRB GBR RGB BGR
  1724. * GBR (ROL) | RGB BGR RBG BRG GBR GRB
  1725. */
  1726. static unsigned int adv7842_op_ch_sel(struct adv7842_state *state)
  1727. {
  1728. #define _SEL(a, b, c, d, e, f) { \
  1729. ADV7842_OP_CH_SEL_##a, ADV7842_OP_CH_SEL_##b, ADV7842_OP_CH_SEL_##c, \
  1730. ADV7842_OP_CH_SEL_##d, ADV7842_OP_CH_SEL_##e, ADV7842_OP_CH_SEL_##f }
  1731. #define _BUS(x) [ADV7842_BUS_ORDER_##x]
  1732. static const unsigned int op_ch_sel[6][6] = {
  1733. _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
  1734. _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
  1735. _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
  1736. _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
  1737. _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
  1738. _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
  1739. };
  1740. return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
  1741. }
  1742. static void adv7842_setup_format(struct adv7842_state *state)
  1743. {
  1744. struct v4l2_subdev *sd = &state->sd;
  1745. io_write_clr_set(sd, 0x02, 0x02,
  1746. state->format->rgb_out ? ADV7842_RGB_OUT : 0);
  1747. io_write(sd, 0x03, state->format->op_format_sel |
  1748. state->pdata.op_format_mode_sel);
  1749. io_write_clr_set(sd, 0x04, 0xe0, adv7842_op_ch_sel(state));
  1750. io_write_clr_set(sd, 0x05, 0x01,
  1751. state->format->swap_cb_cr ? ADV7842_OP_SWAP_CB_CR : 0);
  1752. }
  1753. static int adv7842_get_format(struct v4l2_subdev *sd,
  1754. struct v4l2_subdev_pad_config *cfg,
  1755. struct v4l2_subdev_format *format)
  1756. {
  1757. struct adv7842_state *state = to_state(sd);
  1758. if (format->pad != ADV7842_PAD_SOURCE)
  1759. return -EINVAL;
  1760. if (state->mode == ADV7842_MODE_SDP) {
  1761. /* SPD block */
  1762. if (!(sdp_read(sd, 0x5a) & 0x01))
  1763. return -EINVAL;
  1764. format->format.code = MEDIA_BUS_FMT_YUYV8_2X8;
  1765. format->format.width = 720;
  1766. /* valid signal */
  1767. if (state->norm & V4L2_STD_525_60)
  1768. format->format.height = 480;
  1769. else
  1770. format->format.height = 576;
  1771. format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
  1772. return 0;
  1773. }
  1774. adv7842_fill_format(state, &format->format);
  1775. if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
  1776. struct v4l2_mbus_framefmt *fmt;
  1777. fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
  1778. format->format.code = fmt->code;
  1779. } else {
  1780. format->format.code = state->format->code;
  1781. }
  1782. return 0;
  1783. }
  1784. static int adv7842_set_format(struct v4l2_subdev *sd,
  1785. struct v4l2_subdev_pad_config *cfg,
  1786. struct v4l2_subdev_format *format)
  1787. {
  1788. struct adv7842_state *state = to_state(sd);
  1789. const struct adv7842_format_info *info;
  1790. if (format->pad != ADV7842_PAD_SOURCE)
  1791. return -EINVAL;
  1792. if (state->mode == ADV7842_MODE_SDP)
  1793. return adv7842_get_format(sd, cfg, format);
  1794. info = adv7842_format_info(state, format->format.code);
  1795. if (info == NULL)
  1796. info = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
  1797. adv7842_fill_format(state, &format->format);
  1798. format->format.code = info->code;
  1799. if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
  1800. struct v4l2_mbus_framefmt *fmt;
  1801. fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
  1802. fmt->code = format->format.code;
  1803. } else {
  1804. state->format = info;
  1805. adv7842_setup_format(state);
  1806. }
  1807. return 0;
  1808. }
  1809. static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)
  1810. {
  1811. if (enable) {
  1812. /* Enable SSPD, STDI and CP locked/unlocked interrupts */
  1813. io_write(sd, 0x46, 0x9c);
  1814. /* ESDP_50HZ_DET interrupt */
  1815. io_write(sd, 0x5a, 0x10);
  1816. /* Enable CABLE_DET_A/B_ST (+5v) interrupt */
  1817. io_write(sd, 0x73, 0x03);
  1818. /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
  1819. io_write(sd, 0x78, 0x03);
  1820. /* Enable SDP Standard Detection Change and SDP Video Detected */
  1821. io_write(sd, 0xa0, 0x09);
  1822. /* Enable HDMI_MODE interrupt */
  1823. io_write(sd, 0x69, 0x08);
  1824. } else {
  1825. io_write(sd, 0x46, 0x0);
  1826. io_write(sd, 0x5a, 0x0);
  1827. io_write(sd, 0x73, 0x0);
  1828. io_write(sd, 0x78, 0x0);
  1829. io_write(sd, 0xa0, 0x0);
  1830. io_write(sd, 0x69, 0x0);
  1831. }
  1832. }
  1833. static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
  1834. {
  1835. struct adv7842_state *state = to_state(sd);
  1836. u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp;
  1837. u8 irq_status[6];
  1838. adv7842_irq_enable(sd, false);
  1839. /* read status */
  1840. irq_status[0] = io_read(sd, 0x43);
  1841. irq_status[1] = io_read(sd, 0x57);
  1842. irq_status[2] = io_read(sd, 0x70);
  1843. irq_status[3] = io_read(sd, 0x75);
  1844. irq_status[4] = io_read(sd, 0x9d);
  1845. irq_status[5] = io_read(sd, 0x66);
  1846. /* and clear */
  1847. if (irq_status[0])
  1848. io_write(sd, 0x44, irq_status[0]);
  1849. if (irq_status[1])
  1850. io_write(sd, 0x58, irq_status[1]);
  1851. if (irq_status[2])
  1852. io_write(sd, 0x71, irq_status[2]);
  1853. if (irq_status[3])
  1854. io_write(sd, 0x76, irq_status[3]);
  1855. if (irq_status[4])
  1856. io_write(sd, 0x9e, irq_status[4]);
  1857. if (irq_status[5])
  1858. io_write(sd, 0x67, irq_status[5]);
  1859. adv7842_irq_enable(sd, true);
  1860. v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__,
  1861. irq_status[0], irq_status[1], irq_status[2],
  1862. irq_status[3], irq_status[4], irq_status[5]);
  1863. /* format change CP */
  1864. fmt_change_cp = irq_status[0] & 0x9c;
  1865. /* format change SDP */
  1866. if (state->mode == ADV7842_MODE_SDP)
  1867. fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09);
  1868. else
  1869. fmt_change_sdp = 0;
  1870. /* digital format CP */
  1871. if (is_digital_input(sd))
  1872. fmt_change_digital = irq_status[3] & 0x03;
  1873. else
  1874. fmt_change_digital = 0;
  1875. /* format change */
  1876. if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) {
  1877. v4l2_dbg(1, debug, sd,
  1878. "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n",
  1879. __func__, fmt_change_cp, fmt_change_digital,
  1880. fmt_change_sdp);
  1881. v4l2_subdev_notify_event(sd, &adv7842_ev_fmt);
  1882. if (handled)
  1883. *handled = true;
  1884. }
  1885. /* HDMI/DVI mode */
  1886. if (irq_status[5] & 0x08) {
  1887. v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
  1888. (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI");
  1889. set_rgb_quantization_range(sd);
  1890. if (handled)
  1891. *handled = true;
  1892. }
  1893. /* tx 5v detect */
  1894. if (irq_status[2] & 0x3) {
  1895. v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__);
  1896. adv7842_s_detect_tx_5v_ctrl(sd);
  1897. if (handled)
  1898. *handled = true;
  1899. }
  1900. return 0;
  1901. }
  1902. static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
  1903. {
  1904. struct adv7842_state *state = to_state(sd);
  1905. u8 *data = NULL;
  1906. memset(edid->reserved, 0, sizeof(edid->reserved));
  1907. switch (edid->pad) {
  1908. case ADV7842_EDID_PORT_A:
  1909. case ADV7842_EDID_PORT_B:
  1910. if (state->hdmi_edid.present & (0x04 << edid->pad))
  1911. data = state->hdmi_edid.edid;
  1912. break;
  1913. case ADV7842_EDID_PORT_VGA:
  1914. if (state->vga_edid.present)
  1915. data = state->vga_edid.edid;
  1916. break;
  1917. default:
  1918. return -EINVAL;
  1919. }
  1920. if (edid->start_block == 0 && edid->blocks == 0) {
  1921. edid->blocks = data ? 2 : 0;
  1922. return 0;
  1923. }
  1924. if (!data)
  1925. return -ENODATA;
  1926. if (edid->start_block >= 2)
  1927. return -EINVAL;
  1928. if (edid->start_block + edid->blocks > 2)
  1929. edid->blocks = 2 - edid->start_block;
  1930. memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
  1931. return 0;
  1932. }
  1933. static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e)
  1934. {
  1935. struct adv7842_state *state = to_state(sd);
  1936. int err = 0;
  1937. memset(e->reserved, 0, sizeof(e->reserved));
  1938. if (e->pad > ADV7842_EDID_PORT_VGA)
  1939. return -EINVAL;
  1940. if (e->start_block != 0)
  1941. return -EINVAL;
  1942. if (e->blocks > 2) {
  1943. e->blocks = 2;
  1944. return -E2BIG;
  1945. }
  1946. /* todo, per edid */
  1947. state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15],
  1948. e->edid[0x16]);
  1949. switch (e->pad) {
  1950. case ADV7842_EDID_PORT_VGA:
  1951. memset(&state->vga_edid.edid, 0, 256);
  1952. state->vga_edid.present = e->blocks ? 0x1 : 0x0;
  1953. memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks);
  1954. err = edid_write_vga_segment(sd);
  1955. break;
  1956. case ADV7842_EDID_PORT_A:
  1957. case ADV7842_EDID_PORT_B:
  1958. memset(&state->hdmi_edid.edid, 0, 256);
  1959. if (e->blocks)
  1960. state->hdmi_edid.present |= 0x04 << e->pad;
  1961. else
  1962. state->hdmi_edid.present &= ~(0x04 << e->pad);
  1963. memcpy(&state->hdmi_edid.edid, e->edid, 128 * e->blocks);
  1964. err = edid_write_hdmi_segment(sd, e->pad);
  1965. break;
  1966. default:
  1967. return -EINVAL;
  1968. }
  1969. if (err < 0)
  1970. v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad);
  1971. return err;
  1972. }
  1973. struct adv7842_cfg_read_infoframe {
  1974. const char *desc;
  1975. u8 present_mask;
  1976. u8 head_addr;
  1977. u8 payload_addr;
  1978. };
  1979. static void log_infoframe(struct v4l2_subdev *sd, struct adv7842_cfg_read_infoframe *cri)
  1980. {
  1981. int i;
  1982. u8 buffer[32];
  1983. union hdmi_infoframe frame;
  1984. u8 len;
  1985. struct i2c_client *client = v4l2_get_subdevdata(sd);
  1986. struct device *dev = &client->dev;
  1987. if (!(io_read(sd, 0x60) & cri->present_mask)) {
  1988. v4l2_info(sd, "%s infoframe not received\n", cri->desc);
  1989. return;
  1990. }
  1991. for (i = 0; i < 3; i++)
  1992. buffer[i] = infoframe_read(sd, cri->head_addr + i);
  1993. len = buffer[2] + 1;
  1994. if (len + 3 > sizeof(buffer)) {
  1995. v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len);
  1996. return;
  1997. }
  1998. for (i = 0; i < len; i++)
  1999. buffer[i + 3] = infoframe_read(sd, cri->payload_addr + i);
  2000. if (hdmi_infoframe_unpack(&frame, buffer) < 0) {
  2001. v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc);
  2002. return;
  2003. }
  2004. hdmi_infoframe_log(KERN_INFO, dev, &frame);
  2005. }
  2006. static void adv7842_log_infoframes(struct v4l2_subdev *sd)
  2007. {
  2008. int i;
  2009. struct adv7842_cfg_read_infoframe cri[] = {
  2010. { "AVI", 0x01, 0xe0, 0x00 },
  2011. { "Audio", 0x02, 0xe3, 0x1c },
  2012. { "SDP", 0x04, 0xe6, 0x2a },
  2013. { "Vendor", 0x10, 0xec, 0x54 }
  2014. };
  2015. if (!(hdmi_read(sd, 0x05) & 0x80)) {
  2016. v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
  2017. return;
  2018. }
  2019. for (i = 0; i < ARRAY_SIZE(cri); i++)
  2020. log_infoframe(sd, &cri[i]);
  2021. }
  2022. static const char * const prim_mode_txt[] = {
  2023. "SDP",
  2024. "Component",
  2025. "Graphics",
  2026. "Reserved",
  2027. "CVBS & HDMI AUDIO",
  2028. "HDMI-Comp",
  2029. "HDMI-GR",
  2030. "Reserved",
  2031. "Reserved",
  2032. "Reserved",
  2033. "Reserved",
  2034. "Reserved",
  2035. "Reserved",
  2036. "Reserved",
  2037. "Reserved",
  2038. "Reserved",
  2039. };
  2040. static int adv7842_sdp_log_status(struct v4l2_subdev *sd)
  2041. {
  2042. /* SDP (Standard definition processor) block */
  2043. u8 sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;
  2044. v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on");
  2045. v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n",
  2046. io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);
  2047. v4l2_info(sd, "SDP: free run: %s\n",
  2048. (sdp_read(sd, 0x56) & 0x01) ? "on" : "off");
  2049. v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ?
  2050. "valid SD/PR signal detected" : "invalid/no signal");
  2051. if (sdp_signal_detected) {
  2052. static const char * const sdp_std_txt[] = {
  2053. "NTSC-M/J",
  2054. "1?",
  2055. "NTSC-443",
  2056. "60HzSECAM",
  2057. "PAL-M",
  2058. "5?",
  2059. "PAL-60",
  2060. "7?", "8?", "9?", "a?", "b?",
  2061. "PAL-CombN",
  2062. "d?",
  2063. "PAL-BGHID",
  2064. "SECAM"
  2065. };
  2066. v4l2_info(sd, "SDP: standard %s\n",
  2067. sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);
  2068. v4l2_info(sd, "SDP: %s\n",
  2069. (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz");
  2070. v4l2_info(sd, "SDP: %s\n",
  2071. (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive");
  2072. v4l2_info(sd, "SDP: deinterlacer %s\n",
  2073. (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled");
  2074. v4l2_info(sd, "SDP: csc %s mode\n",
  2075. (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual");
  2076. }
  2077. return 0;
  2078. }
  2079. static int adv7842_cp_log_status(struct v4l2_subdev *sd)
  2080. {
  2081. /* CP block */
  2082. struct adv7842_state *state = to_state(sd);
  2083. struct v4l2_dv_timings timings;
  2084. u8 reg_io_0x02 = io_read(sd, 0x02);
  2085. u8 reg_io_0x21 = io_read(sd, 0x21);
  2086. u8 reg_rep_0x77 = rep_read(sd, 0x77);
  2087. u8 reg_rep_0x7d = rep_read(sd, 0x7d);
  2088. bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
  2089. bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
  2090. bool audio_mute = io_read(sd, 0x65) & 0x40;
  2091. static const char * const csc_coeff_sel_rb[16] = {
  2092. "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
  2093. "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
  2094. "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
  2095. "reserved", "reserved", "reserved", "reserved", "manual"
  2096. };
  2097. static const char * const input_color_space_txt[16] = {
  2098. "RGB limited range (16-235)", "RGB full range (0-255)",
  2099. "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
  2100. "xvYCC Bt.601", "xvYCC Bt.709",
  2101. "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
  2102. "invalid", "invalid", "invalid", "invalid", "invalid",
  2103. "invalid", "invalid", "automatic"
  2104. };
  2105. static const char * const rgb_quantization_range_txt[] = {
  2106. "Automatic",
  2107. "RGB limited range (16-235)",
  2108. "RGB full range (0-255)",
  2109. };
  2110. static const char * const deep_color_mode_txt[4] = {
  2111. "8-bits per channel",
  2112. "10-bits per channel",
  2113. "12-bits per channel",
  2114. "16-bits per channel (not supported)"
  2115. };
  2116. v4l2_info(sd, "-----Chip status-----\n");
  2117. v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
  2118. v4l2_info(sd, "HDMI/DVI-D port selected: %s\n",
  2119. state->hdmi_port_a ? "A" : "B");
  2120. v4l2_info(sd, "EDID A %s, B %s\n",
  2121. ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ?
  2122. "enabled" : "disabled",
  2123. ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ?
  2124. "enabled" : "disabled");
  2125. v4l2_info(sd, "HPD A %s, B %s\n",
  2126. reg_io_0x21 & 0x02 ? "enabled" : "disabled",
  2127. reg_io_0x21 & 0x01 ? "enabled" : "disabled");
  2128. v4l2_info(sd, "CEC %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
  2129. "enabled" : "disabled");
  2130. v4l2_info(sd, "-----Signal status-----\n");
  2131. if (state->hdmi_port_a) {
  2132. v4l2_info(sd, "Cable detected (+5V power): %s\n",
  2133. io_read(sd, 0x6f) & 0x02 ? "true" : "false");
  2134. v4l2_info(sd, "TMDS signal detected: %s\n",
  2135. (io_read(sd, 0x6a) & 0x02) ? "true" : "false");
  2136. v4l2_info(sd, "TMDS signal locked: %s\n",
  2137. (io_read(sd, 0x6a) & 0x20) ? "true" : "false");
  2138. } else {
  2139. v4l2_info(sd, "Cable detected (+5V power):%s\n",
  2140. io_read(sd, 0x6f) & 0x01 ? "true" : "false");
  2141. v4l2_info(sd, "TMDS signal detected: %s\n",
  2142. (io_read(sd, 0x6a) & 0x01) ? "true" : "false");
  2143. v4l2_info(sd, "TMDS signal locked: %s\n",
  2144. (io_read(sd, 0x6a) & 0x10) ? "true" : "false");
  2145. }
  2146. v4l2_info(sd, "CP free run: %s\n",
  2147. (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
  2148. v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
  2149. io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
  2150. (io_read(sd, 0x01) & 0x70) >> 4);
  2151. v4l2_info(sd, "-----Video Timings-----\n");
  2152. if (no_cp_signal(sd)) {
  2153. v4l2_info(sd, "STDI: not locked\n");
  2154. } else {
  2155. u32 bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
  2156. u32 lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
  2157. u32 lcvs = cp_read(sd, 0xb3) >> 3;
  2158. u32 fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9);
  2159. char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
  2160. ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
  2161. char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
  2162. ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
  2163. v4l2_info(sd,
  2164. "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n",
  2165. lcf, bl, lcvs, fcl,
  2166. (cp_read(sd, 0xb1) & 0x40) ?
  2167. "interlaced" : "progressive",
  2168. hs_pol, vs_pol);
  2169. }
  2170. if (adv7842_query_dv_timings(sd, &timings))
  2171. v4l2_info(sd, "No video detected\n");
  2172. else
  2173. v4l2_print_dv_timings(sd->name, "Detected format: ",
  2174. &timings, true);
  2175. v4l2_print_dv_timings(sd->name, "Configured format: ",
  2176. &state->timings, true);
  2177. if (no_cp_signal(sd))
  2178. return 0;
  2179. v4l2_info(sd, "-----Color space-----\n");
  2180. v4l2_info(sd, "RGB quantization range ctrl: %s\n",
  2181. rgb_quantization_range_txt[state->rgb_quantization_range]);
  2182. v4l2_info(sd, "Input color space: %s\n",
  2183. input_color_space_txt[reg_io_0x02 >> 4]);
  2184. v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
  2185. (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
  2186. (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
  2187. ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
  2188. "enabled" : "disabled");
  2189. v4l2_info(sd, "Color space conversion: %s\n",
  2190. csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]);
  2191. if (!is_digital_input(sd))
  2192. return 0;
  2193. v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
  2194. v4l2_info(sd, "HDCP encrypted content: %s\n",
  2195. (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
  2196. v4l2_info(sd, "HDCP keys read: %s%s\n",
  2197. (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
  2198. (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
  2199. if (!is_hdmi(sd))
  2200. return 0;
  2201. v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
  2202. audio_pll_locked ? "locked" : "not locked",
  2203. audio_sample_packet_detect ? "detected" : "not detected",
  2204. audio_mute ? "muted" : "enabled");
  2205. if (audio_pll_locked && audio_sample_packet_detect) {
  2206. v4l2_info(sd, "Audio format: %s\n",
  2207. (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo");
  2208. }
  2209. v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
  2210. (hdmi_read(sd, 0x5c) << 8) +
  2211. (hdmi_read(sd, 0x5d) & 0xf0));
  2212. v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
  2213. (hdmi_read(sd, 0x5e) << 8) +
  2214. hdmi_read(sd, 0x5f));
  2215. v4l2_info(sd, "AV Mute: %s\n",
  2216. (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
  2217. v4l2_info(sd, "Deep color mode: %s\n",
  2218. deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]);
  2219. adv7842_log_infoframes(sd);
  2220. return 0;
  2221. }
  2222. static int adv7842_log_status(struct v4l2_subdev *sd)
  2223. {
  2224. struct adv7842_state *state = to_state(sd);
  2225. if (state->mode == ADV7842_MODE_SDP)
  2226. return adv7842_sdp_log_status(sd);
  2227. return adv7842_cp_log_status(sd);
  2228. }
  2229. static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
  2230. {
  2231. struct adv7842_state *state = to_state(sd);
  2232. v4l2_dbg(1, debug, sd, "%s:\n", __func__);
  2233. if (state->mode != ADV7842_MODE_SDP)
  2234. return -ENODATA;
  2235. if (!(sdp_read(sd, 0x5A) & 0x01)) {
  2236. *std = 0;
  2237. v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
  2238. return 0;
  2239. }
  2240. switch (sdp_read(sd, 0x52) & 0x0f) {
  2241. case 0:
  2242. /* NTSC-M/J */
  2243. *std &= V4L2_STD_NTSC;
  2244. break;
  2245. case 2:
  2246. /* NTSC-443 */
  2247. *std &= V4L2_STD_NTSC_443;
  2248. break;
  2249. case 3:
  2250. /* 60HzSECAM */
  2251. *std &= V4L2_STD_SECAM;
  2252. break;
  2253. case 4:
  2254. /* PAL-M */
  2255. *std &= V4L2_STD_PAL_M;
  2256. break;
  2257. case 6:
  2258. /* PAL-60 */
  2259. *std &= V4L2_STD_PAL_60;
  2260. break;
  2261. case 0xc:
  2262. /* PAL-CombN */
  2263. *std &= V4L2_STD_PAL_Nc;
  2264. break;
  2265. case 0xe:
  2266. /* PAL-BGHID */
  2267. *std &= V4L2_STD_PAL;
  2268. break;
  2269. case 0xf:
  2270. /* SECAM */
  2271. *std &= V4L2_STD_SECAM;
  2272. break;
  2273. default:
  2274. *std &= V4L2_STD_ALL;
  2275. break;
  2276. }
  2277. return 0;
  2278. }
  2279. static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s)
  2280. {
  2281. if (s && s->adjust) {
  2282. sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf);
  2283. sdp_io_write(sd, 0x95, s->hs_beg & 0xff);
  2284. sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf);
  2285. sdp_io_write(sd, 0x97, s->hs_width & 0xff);
  2286. sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf);
  2287. sdp_io_write(sd, 0x99, s->de_beg & 0xff);
  2288. sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf);
  2289. sdp_io_write(sd, 0x9b, s->de_end & 0xff);
  2290. sdp_io_write(sd, 0xa8, s->vs_beg_o);
  2291. sdp_io_write(sd, 0xa9, s->vs_beg_e);
  2292. sdp_io_write(sd, 0xaa, s->vs_end_o);
  2293. sdp_io_write(sd, 0xab, s->vs_end_e);
  2294. sdp_io_write(sd, 0xac, s->de_v_beg_o);
  2295. sdp_io_write(sd, 0xad, s->de_v_beg_e);
  2296. sdp_io_write(sd, 0xae, s->de_v_end_o);
  2297. sdp_io_write(sd, 0xaf, s->de_v_end_e);
  2298. } else {
  2299. /* set to default */
  2300. sdp_io_write(sd, 0x94, 0x00);
  2301. sdp_io_write(sd, 0x95, 0x00);
  2302. sdp_io_write(sd, 0x96, 0x00);
  2303. sdp_io_write(sd, 0x97, 0x20);
  2304. sdp_io_write(sd, 0x98, 0x00);
  2305. sdp_io_write(sd, 0x99, 0x00);
  2306. sdp_io_write(sd, 0x9a, 0x00);
  2307. sdp_io_write(sd, 0x9b, 0x00);
  2308. sdp_io_write(sd, 0xa8, 0x04);
  2309. sdp_io_write(sd, 0xa9, 0x04);
  2310. sdp_io_write(sd, 0xaa, 0x04);
  2311. sdp_io_write(sd, 0xab, 0x04);
  2312. sdp_io_write(sd, 0xac, 0x04);
  2313. sdp_io_write(sd, 0xad, 0x04);
  2314. sdp_io_write(sd, 0xae, 0x04);
  2315. sdp_io_write(sd, 0xaf, 0x04);
  2316. }
  2317. }
  2318. static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
  2319. {
  2320. struct adv7842_state *state = to_state(sd);
  2321. struct adv7842_platform_data *pdata = &state->pdata;
  2322. v4l2_dbg(1, debug, sd, "%s:\n", __func__);
  2323. if (state->mode != ADV7842_MODE_SDP)
  2324. return -ENODATA;
  2325. if (norm & V4L2_STD_625_50)
  2326. adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625);
  2327. else if (norm & V4L2_STD_525_60)
  2328. adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525);
  2329. else
  2330. adv7842_s_sdp_io(sd, NULL);
  2331. if (norm & V4L2_STD_ALL) {
  2332. state->norm = norm;
  2333. return 0;
  2334. }
  2335. return -EINVAL;
  2336. }
  2337. static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
  2338. {
  2339. struct adv7842_state *state = to_state(sd);
  2340. v4l2_dbg(1, debug, sd, "%s:\n", __func__);
  2341. if (state->mode != ADV7842_MODE_SDP)
  2342. return -ENODATA;
  2343. *norm = state->norm;
  2344. return 0;
  2345. }
  2346. /* ----------------------------------------------------------------------- */
  2347. static int adv7842_core_init(struct v4l2_subdev *sd)
  2348. {
  2349. struct adv7842_state *state = to_state(sd);
  2350. struct adv7842_platform_data *pdata = &state->pdata;
  2351. hdmi_write(sd, 0x48,
  2352. (pdata->disable_pwrdnb ? 0x80 : 0) |
  2353. (pdata->disable_cable_det_rst ? 0x40 : 0));
  2354. disable_input(sd);
  2355. /*
  2356. * Disable I2C access to internal EDID ram from HDMI DDC ports
  2357. * Disable auto edid enable when leaving powerdown mode
  2358. */
  2359. rep_write_and_or(sd, 0x77, 0xd3, 0x20);
  2360. /* power */
  2361. io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
  2362. io_write(sd, 0x15, 0x80); /* Power up pads */
  2363. /* video format */
  2364. io_write(sd, 0x02,
  2365. 0xf0 |
  2366. pdata->alt_gamma << 3 |
  2367. pdata->op_656_range << 2 |
  2368. pdata->alt_data_sat << 0);
  2369. io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
  2370. pdata->insert_av_codes << 2 |
  2371. pdata->replicate_av_codes << 1);
  2372. adv7842_setup_format(state);
  2373. /* HDMI audio */
  2374. hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
  2375. /* Drive strength */
  2376. io_write_and_or(sd, 0x14, 0xc0,
  2377. pdata->dr_str_data << 4 |
  2378. pdata->dr_str_clk << 2 |
  2379. pdata->dr_str_sync);
  2380. /* HDMI free run */
  2381. cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable |
  2382. (pdata->hdmi_free_run_mode << 1));
  2383. /* SPD free run */
  2384. sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force |
  2385. (pdata->sdp_free_run_cbar_en << 1) |
  2386. (pdata->sdp_free_run_man_col_en << 2) |
  2387. (pdata->sdp_free_run_auto << 3));
  2388. /* TODO from platform data */
  2389. cp_write(sd, 0x69, 0x14); /* Enable CP CSC */
  2390. io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */
  2391. cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
  2392. afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
  2393. afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
  2394. io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
  2395. sdp_csc_coeff(sd, &pdata->sdp_csc_coeff);
  2396. /* todo, improve settings for sdram */
  2397. if (pdata->sd_ram_size >= 128) {
  2398. sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */
  2399. if (pdata->sd_ram_ddr) {
  2400. /* SDP setup for the AD eval board */
  2401. sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */
  2402. sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */
  2403. sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
  2404. sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
  2405. sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
  2406. } else {
  2407. sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/
  2408. sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */
  2409. sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3,
  2410. depends on memory */
  2411. sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */
  2412. sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
  2413. sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
  2414. sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
  2415. }
  2416. } else {
  2417. /*
  2418. * Manual UG-214, rev 0 is bit confusing on this bit
  2419. * but a '1' disables any signal if the Ram is active.
  2420. */
  2421. sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */
  2422. }
  2423. select_input(sd, pdata->vid_std_select);
  2424. enable_input(sd);
  2425. if (pdata->hpa_auto) {
  2426. /* HPA auto, HPA 0.5s after Edid set and Cable detect */
  2427. hdmi_write(sd, 0x69, 0x5c);
  2428. } else {
  2429. /* HPA manual */
  2430. hdmi_write(sd, 0x69, 0xa3);
  2431. /* HPA disable on port A and B */
  2432. io_write_and_or(sd, 0x20, 0xcf, 0x00);
  2433. }
  2434. /* LLC */
  2435. io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase);
  2436. io_write(sd, 0x33, 0x40);
  2437. /* interrupts */
  2438. io_write(sd, 0x40, 0xf2); /* Configure INT1 */
  2439. adv7842_irq_enable(sd, true);
  2440. return v4l2_ctrl_handler_setup(sd->ctrl_handler);
  2441. }
  2442. /* ----------------------------------------------------------------------- */
  2443. static int adv7842_ddr_ram_test(struct v4l2_subdev *sd)
  2444. {
  2445. /*
  2446. * From ADV784x external Memory test.pdf
  2447. *
  2448. * Reset must just been performed before running test.
  2449. * Recommended to reset after test.
  2450. */
  2451. int i;
  2452. int pass = 0;
  2453. int fail = 0;
  2454. int complete = 0;
  2455. io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */
  2456. io_write(sd, 0x01, 0x00); /* Program SDP mode */
  2457. afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */
  2458. afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */
  2459. afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */
  2460. afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */
  2461. afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */
  2462. afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */
  2463. io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */
  2464. io_write(sd, 0x15, 0xBA); /* Enable outputs */
  2465. sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */
  2466. io_write(sd, 0xFF, 0x04); /* Reset memory controller */
  2467. mdelay(5);
  2468. sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */
  2469. sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */
  2470. sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */
  2471. sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */
  2472. sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */
  2473. sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */
  2474. sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */
  2475. sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */
  2476. sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */
  2477. sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */
  2478. sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */
  2479. mdelay(5);
  2480. sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */
  2481. sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */
  2482. mdelay(20);
  2483. for (i = 0; i < 10; i++) {
  2484. u8 result = sdp_io_read(sd, 0xdb);
  2485. if (result & 0x10) {
  2486. complete++;
  2487. if (result & 0x20)
  2488. fail++;
  2489. else
  2490. pass++;
  2491. }
  2492. mdelay(20);
  2493. }
  2494. v4l2_dbg(1, debug, sd,
  2495. "Ram Test: completed %d of %d: pass %d, fail %d\n",
  2496. complete, i, pass, fail);
  2497. if (!complete || fail)
  2498. return -EIO;
  2499. return 0;
  2500. }
  2501. static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd,
  2502. struct adv7842_platform_data *pdata)
  2503. {
  2504. io_write(sd, 0xf1, pdata->i2c_sdp << 1);
  2505. io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);
  2506. io_write(sd, 0xf3, pdata->i2c_avlink << 1);
  2507. io_write(sd, 0xf4, pdata->i2c_cec << 1);
  2508. io_write(sd, 0xf5, pdata->i2c_infoframe << 1);
  2509. io_write(sd, 0xf8, pdata->i2c_afe << 1);
  2510. io_write(sd, 0xf9, pdata->i2c_repeater << 1);
  2511. io_write(sd, 0xfa, pdata->i2c_edid << 1);
  2512. io_write(sd, 0xfb, pdata->i2c_hdmi << 1);
  2513. io_write(sd, 0xfd, pdata->i2c_cp << 1);
  2514. io_write(sd, 0xfe, pdata->i2c_vdp << 1);
  2515. }
  2516. static int adv7842_command_ram_test(struct v4l2_subdev *sd)
  2517. {
  2518. struct i2c_client *client = v4l2_get_subdevdata(sd);
  2519. struct adv7842_state *state = to_state(sd);
  2520. struct adv7842_platform_data *pdata = client->dev.platform_data;
  2521. struct v4l2_dv_timings timings;
  2522. int ret = 0;
  2523. if (!pdata)
  2524. return -ENODEV;
  2525. if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) {
  2526. v4l2_info(sd, "no sdram or no ddr sdram\n");
  2527. return -EINVAL;
  2528. }
  2529. main_reset(sd);
  2530. adv7842_rewrite_i2c_addresses(sd, pdata);
  2531. /* run ram test */
  2532. ret = adv7842_ddr_ram_test(sd);
  2533. main_reset(sd);
  2534. adv7842_rewrite_i2c_addresses(sd, pdata);
  2535. /* and re-init chip and state */
  2536. adv7842_core_init(sd);
  2537. disable_input(sd);
  2538. select_input(sd, state->vid_std_select);
  2539. enable_input(sd);
  2540. edid_write_vga_segment(sd);
  2541. edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A);
  2542. edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B);
  2543. timings = state->timings;
  2544. memset(&state->timings, 0, sizeof(struct v4l2_dv_timings));
  2545. adv7842_s_dv_timings(sd, &timings);
  2546. return ret;
  2547. }
  2548. static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
  2549. {
  2550. switch (cmd) {
  2551. case ADV7842_CMD_RAM_TEST:
  2552. return adv7842_command_ram_test(sd);
  2553. }
  2554. return -ENOTTY;
  2555. }
  2556. static int adv7842_subscribe_event(struct v4l2_subdev *sd,
  2557. struct v4l2_fh *fh,
  2558. struct v4l2_event_subscription *sub)
  2559. {
  2560. switch (sub->type) {
  2561. case V4L2_EVENT_SOURCE_CHANGE:
  2562. return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
  2563. case V4L2_EVENT_CTRL:
  2564. return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
  2565. default:
  2566. return -EINVAL;
  2567. }
  2568. }
  2569. /* ----------------------------------------------------------------------- */
  2570. static const struct v4l2_ctrl_ops adv7842_ctrl_ops = {
  2571. .s_ctrl = adv7842_s_ctrl,
  2572. };
  2573. static const struct v4l2_subdev_core_ops adv7842_core_ops = {
  2574. .log_status = adv7842_log_status,
  2575. .ioctl = adv7842_ioctl,
  2576. .interrupt_service_routine = adv7842_isr,
  2577. .subscribe_event = adv7842_subscribe_event,
  2578. .unsubscribe_event = v4l2_event_subdev_unsubscribe,
  2579. #ifdef CONFIG_VIDEO_ADV_DEBUG
  2580. .g_register = adv7842_g_register,
  2581. .s_register = adv7842_s_register,
  2582. #endif
  2583. };
  2584. static const struct v4l2_subdev_video_ops adv7842_video_ops = {
  2585. .g_std = adv7842_g_std,
  2586. .s_std = adv7842_s_std,
  2587. .s_routing = adv7842_s_routing,
  2588. .querystd = adv7842_querystd,
  2589. .g_input_status = adv7842_g_input_status,
  2590. .s_dv_timings = adv7842_s_dv_timings,
  2591. .g_dv_timings = adv7842_g_dv_timings,
  2592. .query_dv_timings = adv7842_query_dv_timings,
  2593. };
  2594. static const struct v4l2_subdev_pad_ops adv7842_pad_ops = {
  2595. .enum_mbus_code = adv7842_enum_mbus_code,
  2596. .get_fmt = adv7842_get_format,
  2597. .set_fmt = adv7842_set_format,
  2598. .get_edid = adv7842_get_edid,
  2599. .set_edid = adv7842_set_edid,
  2600. .enum_dv_timings = adv7842_enum_dv_timings,
  2601. .dv_timings_cap = adv7842_dv_timings_cap,
  2602. };
  2603. static const struct v4l2_subdev_ops adv7842_ops = {
  2604. .core = &adv7842_core_ops,
  2605. .video = &adv7842_video_ops,
  2606. .pad = &adv7842_pad_ops,
  2607. };
  2608. /* -------------------------- custom ctrls ---------------------------------- */
  2609. static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = {
  2610. .ops = &adv7842_ctrl_ops,
  2611. .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
  2612. .name = "Analog Sampling Phase",
  2613. .type = V4L2_CTRL_TYPE_INTEGER,
  2614. .min = 0,
  2615. .max = 0x1f,
  2616. .step = 1,
  2617. .def = 0,
  2618. };
  2619. static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = {
  2620. .ops = &adv7842_ctrl_ops,
  2621. .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
  2622. .name = "Free Running Color, Manual",
  2623. .type = V4L2_CTRL_TYPE_BOOLEAN,
  2624. .max = 1,
  2625. .step = 1,
  2626. .def = 1,
  2627. };
  2628. static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = {
  2629. .ops = &adv7842_ctrl_ops,
  2630. .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
  2631. .name = "Free Running Color",
  2632. .type = V4L2_CTRL_TYPE_INTEGER,
  2633. .max = 0xffffff,
  2634. .step = 0x1,
  2635. };
  2636. static void adv7842_unregister_clients(struct v4l2_subdev *sd)
  2637. {
  2638. struct adv7842_state *state = to_state(sd);
  2639. if (state->i2c_avlink)
  2640. i2c_unregister_device(state->i2c_avlink);
  2641. if (state->i2c_cec)
  2642. i2c_unregister_device(state->i2c_cec);
  2643. if (state->i2c_infoframe)
  2644. i2c_unregister_device(state->i2c_infoframe);
  2645. if (state->i2c_sdp_io)
  2646. i2c_unregister_device(state->i2c_sdp_io);
  2647. if (state->i2c_sdp)
  2648. i2c_unregister_device(state->i2c_sdp);
  2649. if (state->i2c_afe)
  2650. i2c_unregister_device(state->i2c_afe);
  2651. if (state->i2c_repeater)
  2652. i2c_unregister_device(state->i2c_repeater);
  2653. if (state->i2c_edid)
  2654. i2c_unregister_device(state->i2c_edid);
  2655. if (state->i2c_hdmi)
  2656. i2c_unregister_device(state->i2c_hdmi);
  2657. if (state->i2c_cp)
  2658. i2c_unregister_device(state->i2c_cp);
  2659. if (state->i2c_vdp)
  2660. i2c_unregister_device(state->i2c_vdp);
  2661. state->i2c_avlink = NULL;
  2662. state->i2c_cec = NULL;
  2663. state->i2c_infoframe = NULL;
  2664. state->i2c_sdp_io = NULL;
  2665. state->i2c_sdp = NULL;
  2666. state->i2c_afe = NULL;
  2667. state->i2c_repeater = NULL;
  2668. state->i2c_edid = NULL;
  2669. state->i2c_hdmi = NULL;
  2670. state->i2c_cp = NULL;
  2671. state->i2c_vdp = NULL;
  2672. }
  2673. static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc,
  2674. u8 addr, u8 io_reg)
  2675. {
  2676. struct i2c_client *client = v4l2_get_subdevdata(sd);
  2677. struct i2c_client *cp;
  2678. io_write(sd, io_reg, addr << 1);
  2679. if (addr == 0) {
  2680. v4l2_err(sd, "no %s i2c addr configured\n", desc);
  2681. return NULL;
  2682. }
  2683. cp = i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
  2684. if (!cp)
  2685. v4l2_err(sd, "register %s on i2c addr 0x%x failed\n", desc, addr);
  2686. return cp;
  2687. }
  2688. static int adv7842_register_clients(struct v4l2_subdev *sd)
  2689. {
  2690. struct adv7842_state *state = to_state(sd);
  2691. struct adv7842_platform_data *pdata = &state->pdata;
  2692. state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3);
  2693. state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4);
  2694. state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5);
  2695. state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2);
  2696. state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1);
  2697. state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8);
  2698. state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9);
  2699. state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa);
  2700. state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb);
  2701. state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd);
  2702. state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe);
  2703. if (!state->i2c_avlink ||
  2704. !state->i2c_cec ||
  2705. !state->i2c_infoframe ||
  2706. !state->i2c_sdp_io ||
  2707. !state->i2c_sdp ||
  2708. !state->i2c_afe ||
  2709. !state->i2c_repeater ||
  2710. !state->i2c_edid ||
  2711. !state->i2c_hdmi ||
  2712. !state->i2c_cp ||
  2713. !state->i2c_vdp)
  2714. return -1;
  2715. return 0;
  2716. }
  2717. static int adv7842_probe(struct i2c_client *client,
  2718. const struct i2c_device_id *id)
  2719. {
  2720. struct adv7842_state *state;
  2721. static const struct v4l2_dv_timings cea640x480 =
  2722. V4L2_DV_BT_CEA_640X480P59_94;
  2723. struct adv7842_platform_data *pdata = client->dev.platform_data;
  2724. struct v4l2_ctrl_handler *hdl;
  2725. struct v4l2_subdev *sd;
  2726. u16 rev;
  2727. int err;
  2728. /* Check if the adapter supports the needed features */
  2729. if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
  2730. return -EIO;
  2731. v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n",
  2732. client->addr << 1);
  2733. if (!pdata) {
  2734. v4l_err(client, "No platform data!\n");
  2735. return -ENODEV;
  2736. }
  2737. state = devm_kzalloc(&client->dev, sizeof(struct adv7842_state), GFP_KERNEL);
  2738. if (!state) {
  2739. v4l_err(client, "Could not allocate adv7842_state memory!\n");
  2740. return -ENOMEM;
  2741. }
  2742. /* platform data */
  2743. state->pdata = *pdata;
  2744. state->timings = cea640x480;
  2745. state->format = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
  2746. sd = &state->sd;
  2747. v4l2_i2c_subdev_init(sd, client, &adv7842_ops);
  2748. sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
  2749. state->mode = pdata->mode;
  2750. state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A;
  2751. state->restart_stdi_once = true;
  2752. /* i2c access to adv7842? */
  2753. rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
  2754. adv_smbus_read_byte_data_check(client, 0xeb, false);
  2755. if (rev != 0x2012) {
  2756. v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev);
  2757. rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
  2758. adv_smbus_read_byte_data_check(client, 0xeb, false);
  2759. }
  2760. if (rev != 0x2012) {
  2761. v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n",
  2762. client->addr << 1, rev);
  2763. return -ENODEV;
  2764. }
  2765. if (pdata->chip_reset)
  2766. main_reset(sd);
  2767. /* control handlers */
  2768. hdl = &state->hdl;
  2769. v4l2_ctrl_handler_init(hdl, 6);
  2770. /* add in ascending ID order */
  2771. v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
  2772. V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
  2773. v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
  2774. V4L2_CID_CONTRAST, 0, 255, 1, 128);
  2775. v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
  2776. V4L2_CID_SATURATION, 0, 255, 1, 128);
  2777. v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
  2778. V4L2_CID_HUE, 0, 128, 1, 0);
  2779. /* custom controls */
  2780. state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
  2781. V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0);
  2782. state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl,
  2783. &adv7842_ctrl_analog_sampling_phase, NULL);
  2784. state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl,
  2785. &adv7842_ctrl_free_run_color_manual, NULL);
  2786. state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl,
  2787. &adv7842_ctrl_free_run_color, NULL);
  2788. state->rgb_quantization_range_ctrl =
  2789. v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
  2790. V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
  2791. 0, V4L2_DV_RGB_RANGE_AUTO);
  2792. sd->ctrl_handler = hdl;
  2793. if (hdl->error) {
  2794. err = hdl->error;
  2795. goto err_hdl;
  2796. }
  2797. state->detect_tx_5v_ctrl->is_private = true;
  2798. state->rgb_quantization_range_ctrl->is_private = true;
  2799. state->analog_sampling_phase_ctrl->is_private = true;
  2800. state->free_run_color_ctrl_manual->is_private = true;
  2801. state->free_run_color_ctrl->is_private = true;
  2802. if (adv7842_s_detect_tx_5v_ctrl(sd)) {
  2803. err = -ENODEV;
  2804. goto err_hdl;
  2805. }
  2806. if (adv7842_register_clients(sd) < 0) {
  2807. err = -ENOMEM;
  2808. v4l2_err(sd, "failed to create all i2c clients\n");
  2809. goto err_i2c;
  2810. }
  2811. /* work queues */
  2812. state->work_queues = create_singlethread_workqueue(client->name);
  2813. if (!state->work_queues) {
  2814. v4l2_err(sd, "Could not create work queue\n");
  2815. err = -ENOMEM;
  2816. goto err_i2c;
  2817. }
  2818. INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
  2819. adv7842_delayed_work_enable_hotplug);
  2820. state->pad.flags = MEDIA_PAD_FL_SOURCE;
  2821. err = media_entity_init(&sd->entity, 1, &state->pad, 0);
  2822. if (err)
  2823. goto err_work_queues;
  2824. err = adv7842_core_init(sd);
  2825. if (err)
  2826. goto err_entity;
  2827. v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
  2828. client->addr << 1, client->adapter->name);
  2829. return 0;
  2830. err_entity:
  2831. media_entity_cleanup(&sd->entity);
  2832. err_work_queues:
  2833. cancel_delayed_work(&state->delayed_work_enable_hotplug);
  2834. destroy_workqueue(state->work_queues);
  2835. err_i2c:
  2836. adv7842_unregister_clients(sd);
  2837. err_hdl:
  2838. v4l2_ctrl_handler_free(hdl);
  2839. return err;
  2840. }
  2841. /* ----------------------------------------------------------------------- */
  2842. static int adv7842_remove(struct i2c_client *client)
  2843. {
  2844. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  2845. struct adv7842_state *state = to_state(sd);
  2846. adv7842_irq_enable(sd, false);
  2847. cancel_delayed_work(&state->delayed_work_enable_hotplug);
  2848. destroy_workqueue(state->work_queues);
  2849. v4l2_device_unregister_subdev(sd);
  2850. media_entity_cleanup(&sd->entity);
  2851. adv7842_unregister_clients(sd);
  2852. v4l2_ctrl_handler_free(sd->ctrl_handler);
  2853. return 0;
  2854. }
  2855. /* ----------------------------------------------------------------------- */
  2856. static struct i2c_device_id adv7842_id[] = {
  2857. { "adv7842", 0 },
  2858. { }
  2859. };
  2860. MODULE_DEVICE_TABLE(i2c, adv7842_id);
  2861. /* ----------------------------------------------------------------------- */
  2862. static struct i2c_driver adv7842_driver = {
  2863. .driver = {
  2864. .name = "adv7842",
  2865. },
  2866. .probe = adv7842_probe,
  2867. .remove = adv7842_remove,
  2868. .id_table = adv7842_id,
  2869. };
  2870. module_i2c_driver(adv7842_driver);