cobalt-irq.c 7.9 KB

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  1. /*
  2. * cobalt interrupt handling
  3. *
  4. * Copyright 2012-2015 Cisco Systems, Inc. and/or its affiliates.
  5. * All rights reserved.
  6. *
  7. * This program is free software; you may redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; version 2 of the License.
  10. *
  11. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  12. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  13. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  14. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  15. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  16. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  17. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  18. * SOFTWARE.
  19. */
  20. #include <media/adv7604.h>
  21. #include "cobalt-driver.h"
  22. #include "cobalt-irq.h"
  23. #include "cobalt-omnitek.h"
  24. static void cobalt_dma_stream_queue_handler(struct cobalt_stream *s)
  25. {
  26. struct cobalt *cobalt = s->cobalt;
  27. int rx = s->video_channel;
  28. struct m00473_freewheel_regmap __iomem *fw =
  29. COBALT_CVI_FREEWHEEL(s->cobalt, rx);
  30. struct m00233_video_measure_regmap __iomem *vmr =
  31. COBALT_CVI_VMR(s->cobalt, rx);
  32. struct m00389_cvi_regmap __iomem *cvi =
  33. COBALT_CVI(s->cobalt, rx);
  34. struct m00479_clk_loss_detector_regmap __iomem *clkloss =
  35. COBALT_CVI_CLK_LOSS(s->cobalt, rx);
  36. struct cobalt_buffer *cb;
  37. bool skip = false;
  38. spin_lock(&s->irqlock);
  39. if (list_empty(&s->bufs)) {
  40. pr_err("no buffers!\n");
  41. spin_unlock(&s->irqlock);
  42. return;
  43. }
  44. /* Give the fresh filled up buffer to the user.
  45. * Note that the interrupt is only sent if the DMA can continue
  46. * with a new buffer, so it is always safe to return this buffer
  47. * to userspace. */
  48. cb = list_first_entry(&s->bufs, struct cobalt_buffer, list);
  49. list_del(&cb->list);
  50. spin_unlock(&s->irqlock);
  51. if (s->is_audio || s->is_output)
  52. goto done;
  53. if (s->unstable_frame) {
  54. uint32_t stat = ioread32(&vmr->irq_status);
  55. iowrite32(stat, &vmr->irq_status);
  56. if (!(ioread32(&vmr->status) &
  57. M00233_STATUS_BITMAP_INIT_DONE_MSK)) {
  58. cobalt_dbg(1, "!init_done\n");
  59. if (s->enable_freewheel)
  60. goto restart_fw;
  61. goto done;
  62. }
  63. if (ioread32(&clkloss->status) &
  64. M00479_STATUS_BITMAP_CLOCK_MISSING_MSK) {
  65. iowrite32(0, &clkloss->ctrl);
  66. iowrite32(M00479_CTRL_BITMAP_ENABLE_MSK, &clkloss->ctrl);
  67. cobalt_dbg(1, "no clock\n");
  68. if (s->enable_freewheel)
  69. goto restart_fw;
  70. goto done;
  71. }
  72. if ((stat & (M00233_IRQ_STATUS_BITMAP_VACTIVE_AREA_MSK |
  73. M00233_IRQ_STATUS_BITMAP_HACTIVE_AREA_MSK)) ||
  74. ioread32(&vmr->vactive_area) != s->timings.bt.height ||
  75. ioread32(&vmr->hactive_area) != s->timings.bt.width) {
  76. cobalt_dbg(1, "unstable\n");
  77. if (s->enable_freewheel)
  78. goto restart_fw;
  79. goto done;
  80. }
  81. if (!s->enable_cvi) {
  82. s->enable_cvi = true;
  83. iowrite32(M00389_CONTROL_BITMAP_ENABLE_MSK, &cvi->control);
  84. goto done;
  85. }
  86. if (!(ioread32(&cvi->status) & M00389_STATUS_BITMAP_LOCK_MSK)) {
  87. cobalt_dbg(1, "cvi no lock\n");
  88. if (s->enable_freewheel)
  89. goto restart_fw;
  90. goto done;
  91. }
  92. if (!s->enable_freewheel) {
  93. cobalt_dbg(1, "stable\n");
  94. s->enable_freewheel = true;
  95. iowrite32(0, &fw->ctrl);
  96. goto done;
  97. }
  98. cobalt_dbg(1, "enabled fw\n");
  99. iowrite32(M00233_CONTROL_BITMAP_ENABLE_MEASURE_MSK |
  100. M00233_CONTROL_BITMAP_ENABLE_INTERRUPT_MSK,
  101. &vmr->control);
  102. iowrite32(M00473_CTRL_BITMAP_ENABLE_MSK, &fw->ctrl);
  103. s->enable_freewheel = false;
  104. s->unstable_frame = false;
  105. s->skip_first_frames = 2;
  106. skip = true;
  107. goto done;
  108. }
  109. if (ioread32(&fw->status) & M00473_STATUS_BITMAP_FREEWHEEL_MODE_MSK) {
  110. restart_fw:
  111. cobalt_dbg(1, "lost lock\n");
  112. iowrite32(M00233_CONTROL_BITMAP_ENABLE_MEASURE_MSK,
  113. &vmr->control);
  114. iowrite32(M00473_CTRL_BITMAP_ENABLE_MSK |
  115. M00473_CTRL_BITMAP_FORCE_FREEWHEEL_MODE_MSK,
  116. &fw->ctrl);
  117. iowrite32(0, &cvi->control);
  118. s->unstable_frame = true;
  119. s->enable_freewheel = false;
  120. s->enable_cvi = false;
  121. }
  122. done:
  123. if (s->skip_first_frames) {
  124. skip = true;
  125. s->skip_first_frames--;
  126. }
  127. v4l2_get_timestamp(&cb->vb.timestamp);
  128. /* TODO: the sequence number should be read from the FPGA so we
  129. also know about dropped frames. */
  130. cb->vb.sequence = s->sequence++;
  131. vb2_buffer_done(&cb->vb.vb2_buf,
  132. (skip || s->unstable_frame) ?
  133. VB2_BUF_STATE_REQUEUEING : VB2_BUF_STATE_DONE);
  134. }
  135. irqreturn_t cobalt_irq_handler(int irq, void *dev_id)
  136. {
  137. struct cobalt *cobalt = (struct cobalt *)dev_id;
  138. u32 dma_interrupt =
  139. cobalt_read_bar0(cobalt, DMA_INTERRUPT_STATUS_REG) & 0xffff;
  140. u32 mask = cobalt_read_bar1(cobalt, COBALT_SYS_STAT_MASK);
  141. u32 edge = cobalt_read_bar1(cobalt, COBALT_SYS_STAT_EDGE);
  142. int i;
  143. /* Clear DMA interrupt */
  144. cobalt_write_bar0(cobalt, DMA_INTERRUPT_STATUS_REG, dma_interrupt);
  145. cobalt_write_bar1(cobalt, COBALT_SYS_STAT_MASK, mask & ~edge);
  146. cobalt_write_bar1(cobalt, COBALT_SYS_STAT_EDGE, edge);
  147. for (i = 0; i < COBALT_NUM_STREAMS; i++) {
  148. struct cobalt_stream *s = &cobalt->streams[i];
  149. unsigned dma_fifo_mask = s->dma_fifo_mask;
  150. if (dma_interrupt & (1 << s->dma_channel)) {
  151. cobalt->irq_dma[i]++;
  152. /* Give fresh buffer to user and chain newly
  153. * queued buffers */
  154. cobalt_dma_stream_queue_handler(s);
  155. if (!s->is_audio) {
  156. edge &= ~dma_fifo_mask;
  157. cobalt_write_bar1(cobalt, COBALT_SYS_STAT_MASK,
  158. mask & ~edge);
  159. }
  160. }
  161. if (s->is_audio)
  162. continue;
  163. if (edge & s->adv_irq_mask)
  164. set_bit(COBALT_STREAM_FL_ADV_IRQ, &s->flags);
  165. if ((edge & mask & dma_fifo_mask) && vb2_is_streaming(&s->q)) {
  166. cobalt_info("full rx FIFO %d\n", i);
  167. cobalt->irq_full_fifo++;
  168. }
  169. }
  170. queue_work(cobalt->irq_work_queues, &cobalt->irq_work_queue);
  171. if (edge & mask & (COBALT_SYSSTAT_VI0_INT1_MSK |
  172. COBALT_SYSSTAT_VI1_INT1_MSK |
  173. COBALT_SYSSTAT_VI2_INT1_MSK |
  174. COBALT_SYSSTAT_VI3_INT1_MSK |
  175. COBALT_SYSSTAT_VIHSMA_INT1_MSK |
  176. COBALT_SYSSTAT_VOHSMA_INT1_MSK))
  177. cobalt->irq_adv1++;
  178. if (edge & mask & (COBALT_SYSSTAT_VI0_INT2_MSK |
  179. COBALT_SYSSTAT_VI1_INT2_MSK |
  180. COBALT_SYSSTAT_VI2_INT2_MSK |
  181. COBALT_SYSSTAT_VI3_INT2_MSK |
  182. COBALT_SYSSTAT_VIHSMA_INT2_MSK))
  183. cobalt->irq_adv2++;
  184. if (edge & mask & COBALT_SYSSTAT_VOHSMA_INT1_MSK)
  185. cobalt->irq_advout++;
  186. if (dma_interrupt)
  187. cobalt->irq_dma_tot++;
  188. if (!(edge & mask) && !dma_interrupt)
  189. cobalt->irq_none++;
  190. dma_interrupt = cobalt_read_bar0(cobalt, DMA_INTERRUPT_STATUS_REG);
  191. return IRQ_HANDLED;
  192. }
  193. void cobalt_irq_work_handler(struct work_struct *work)
  194. {
  195. struct cobalt *cobalt =
  196. container_of(work, struct cobalt, irq_work_queue);
  197. int i;
  198. for (i = 0; i < COBALT_NUM_NODES; i++) {
  199. struct cobalt_stream *s = &cobalt->streams[i];
  200. if (test_and_clear_bit(COBALT_STREAM_FL_ADV_IRQ, &s->flags)) {
  201. u32 mask;
  202. v4l2_subdev_call(cobalt->streams[i].sd, core,
  203. interrupt_service_routine, 0, NULL);
  204. mask = cobalt_read_bar1(cobalt, COBALT_SYS_STAT_MASK);
  205. cobalt_write_bar1(cobalt, COBALT_SYS_STAT_MASK,
  206. mask | s->adv_irq_mask);
  207. }
  208. }
  209. }
  210. void cobalt_irq_log_status(struct cobalt *cobalt)
  211. {
  212. u32 mask;
  213. int i;
  214. cobalt_info("irq: adv1=%u adv2=%u advout=%u none=%u full=%u\n",
  215. cobalt->irq_adv1, cobalt->irq_adv2, cobalt->irq_advout,
  216. cobalt->irq_none, cobalt->irq_full_fifo);
  217. cobalt_info("irq: dma_tot=%u (", cobalt->irq_dma_tot);
  218. for (i = 0; i < COBALT_NUM_STREAMS; i++)
  219. pr_cont("%s%u", i ? "/" : "", cobalt->irq_dma[i]);
  220. pr_cont(")\n");
  221. cobalt->irq_dma_tot = cobalt->irq_adv1 = cobalt->irq_adv2 = 0;
  222. cobalt->irq_advout = cobalt->irq_none = cobalt->irq_full_fifo = 0;
  223. memset(cobalt->irq_dma, 0, sizeof(cobalt->irq_dma));
  224. mask = cobalt_read_bar1(cobalt, COBALT_SYS_STAT_MASK);
  225. cobalt_write_bar1(cobalt, COBALT_SYS_STAT_MASK,
  226. mask |
  227. COBALT_SYSSTAT_VI0_LOST_DATA_MSK |
  228. COBALT_SYSSTAT_VI1_LOST_DATA_MSK |
  229. COBALT_SYSSTAT_VI2_LOST_DATA_MSK |
  230. COBALT_SYSSTAT_VI3_LOST_DATA_MSK |
  231. COBALT_SYSSTAT_VIHSMA_LOST_DATA_MSK |
  232. COBALT_SYSSTAT_VOHSMA_LOST_DATA_MSK |
  233. COBALT_SYSSTAT_AUD_IN_LOST_DATA_MSK |
  234. COBALT_SYSSTAT_AUD_OUT_LOST_DATA_MSK);
  235. }