cx88-video.c 45 KB

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  1. /*
  2. *
  3. * device driver for Conexant 2388x based TV cards
  4. * video4linux video interface
  5. *
  6. * (c) 2003-04 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
  7. *
  8. * (c) 2005-2006 Mauro Carvalho Chehab <mchehab@infradead.org>
  9. * - Multituner support
  10. * - video_ioctl2 conversion
  11. * - PAL/M fixes
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License as published by
  15. * the Free Software Foundation; either version 2 of the License, or
  16. * (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26. */
  27. #include <linux/init.h>
  28. #include <linux/list.h>
  29. #include <linux/module.h>
  30. #include <linux/kmod.h>
  31. #include <linux/kernel.h>
  32. #include <linux/slab.h>
  33. #include <linux/interrupt.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/delay.h>
  36. #include <linux/kthread.h>
  37. #include <asm/div64.h>
  38. #include "cx88.h"
  39. #include <media/v4l2-common.h>
  40. #include <media/v4l2-ioctl.h>
  41. #include <media/v4l2-event.h>
  42. #include <media/wm8775.h>
  43. MODULE_DESCRIPTION("v4l2 driver module for cx2388x based TV cards");
  44. MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
  45. MODULE_LICENSE("GPL");
  46. MODULE_VERSION(CX88_VERSION);
  47. /* ------------------------------------------------------------------ */
  48. static unsigned int video_nr[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
  49. static unsigned int vbi_nr[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
  50. static unsigned int radio_nr[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
  51. module_param_array(video_nr, int, NULL, 0444);
  52. module_param_array(vbi_nr, int, NULL, 0444);
  53. module_param_array(radio_nr, int, NULL, 0444);
  54. MODULE_PARM_DESC(video_nr,"video device numbers");
  55. MODULE_PARM_DESC(vbi_nr,"vbi device numbers");
  56. MODULE_PARM_DESC(radio_nr,"radio device numbers");
  57. static unsigned int video_debug;
  58. module_param(video_debug,int,0644);
  59. MODULE_PARM_DESC(video_debug,"enable debug messages [video]");
  60. static unsigned int irq_debug;
  61. module_param(irq_debug,int,0644);
  62. MODULE_PARM_DESC(irq_debug,"enable debug messages [IRQ handler]");
  63. #define dprintk(level,fmt, arg...) if (video_debug >= level) \
  64. printk(KERN_DEBUG "%s/0: " fmt, core->name , ## arg)
  65. /* ------------------------------------------------------------------- */
  66. /* static data */
  67. static const struct cx8800_fmt formats[] = {
  68. {
  69. .name = "8 bpp, gray",
  70. .fourcc = V4L2_PIX_FMT_GREY,
  71. .cxformat = ColorFormatY8,
  72. .depth = 8,
  73. .flags = FORMAT_FLAGS_PACKED,
  74. },{
  75. .name = "15 bpp RGB, le",
  76. .fourcc = V4L2_PIX_FMT_RGB555,
  77. .cxformat = ColorFormatRGB15,
  78. .depth = 16,
  79. .flags = FORMAT_FLAGS_PACKED,
  80. },{
  81. .name = "15 bpp RGB, be",
  82. .fourcc = V4L2_PIX_FMT_RGB555X,
  83. .cxformat = ColorFormatRGB15 | ColorFormatBSWAP,
  84. .depth = 16,
  85. .flags = FORMAT_FLAGS_PACKED,
  86. },{
  87. .name = "16 bpp RGB, le",
  88. .fourcc = V4L2_PIX_FMT_RGB565,
  89. .cxformat = ColorFormatRGB16,
  90. .depth = 16,
  91. .flags = FORMAT_FLAGS_PACKED,
  92. },{
  93. .name = "16 bpp RGB, be",
  94. .fourcc = V4L2_PIX_FMT_RGB565X,
  95. .cxformat = ColorFormatRGB16 | ColorFormatBSWAP,
  96. .depth = 16,
  97. .flags = FORMAT_FLAGS_PACKED,
  98. },{
  99. .name = "24 bpp RGB, le",
  100. .fourcc = V4L2_PIX_FMT_BGR24,
  101. .cxformat = ColorFormatRGB24,
  102. .depth = 24,
  103. .flags = FORMAT_FLAGS_PACKED,
  104. },{
  105. .name = "32 bpp RGB, le",
  106. .fourcc = V4L2_PIX_FMT_BGR32,
  107. .cxformat = ColorFormatRGB32,
  108. .depth = 32,
  109. .flags = FORMAT_FLAGS_PACKED,
  110. },{
  111. .name = "32 bpp RGB, be",
  112. .fourcc = V4L2_PIX_FMT_RGB32,
  113. .cxformat = ColorFormatRGB32 | ColorFormatBSWAP | ColorFormatWSWAP,
  114. .depth = 32,
  115. .flags = FORMAT_FLAGS_PACKED,
  116. },{
  117. .name = "4:2:2, packed, YUYV",
  118. .fourcc = V4L2_PIX_FMT_YUYV,
  119. .cxformat = ColorFormatYUY2,
  120. .depth = 16,
  121. .flags = FORMAT_FLAGS_PACKED,
  122. },{
  123. .name = "4:2:2, packed, UYVY",
  124. .fourcc = V4L2_PIX_FMT_UYVY,
  125. .cxformat = ColorFormatYUY2 | ColorFormatBSWAP,
  126. .depth = 16,
  127. .flags = FORMAT_FLAGS_PACKED,
  128. },
  129. };
  130. static const struct cx8800_fmt* format_by_fourcc(unsigned int fourcc)
  131. {
  132. unsigned int i;
  133. for (i = 0; i < ARRAY_SIZE(formats); i++)
  134. if (formats[i].fourcc == fourcc)
  135. return formats+i;
  136. return NULL;
  137. }
  138. /* ------------------------------------------------------------------- */
  139. struct cx88_ctrl {
  140. /* control information */
  141. u32 id;
  142. s32 minimum;
  143. s32 maximum;
  144. u32 step;
  145. s32 default_value;
  146. /* control register information */
  147. u32 off;
  148. u32 reg;
  149. u32 sreg;
  150. u32 mask;
  151. u32 shift;
  152. };
  153. static const struct cx88_ctrl cx8800_vid_ctls[] = {
  154. /* --- video --- */
  155. {
  156. .id = V4L2_CID_BRIGHTNESS,
  157. .minimum = 0x00,
  158. .maximum = 0xff,
  159. .step = 1,
  160. .default_value = 0x7f,
  161. .off = 128,
  162. .reg = MO_CONTR_BRIGHT,
  163. .mask = 0x00ff,
  164. .shift = 0,
  165. },{
  166. .id = V4L2_CID_CONTRAST,
  167. .minimum = 0,
  168. .maximum = 0xff,
  169. .step = 1,
  170. .default_value = 0x3f,
  171. .off = 0,
  172. .reg = MO_CONTR_BRIGHT,
  173. .mask = 0xff00,
  174. .shift = 8,
  175. },{
  176. .id = V4L2_CID_HUE,
  177. .minimum = 0,
  178. .maximum = 0xff,
  179. .step = 1,
  180. .default_value = 0x7f,
  181. .off = 128,
  182. .reg = MO_HUE,
  183. .mask = 0x00ff,
  184. .shift = 0,
  185. },{
  186. /* strictly, this only describes only U saturation.
  187. * V saturation is handled specially through code.
  188. */
  189. .id = V4L2_CID_SATURATION,
  190. .minimum = 0,
  191. .maximum = 0xff,
  192. .step = 1,
  193. .default_value = 0x7f,
  194. .off = 0,
  195. .reg = MO_UV_SATURATION,
  196. .mask = 0x00ff,
  197. .shift = 0,
  198. }, {
  199. .id = V4L2_CID_SHARPNESS,
  200. .minimum = 0,
  201. .maximum = 4,
  202. .step = 1,
  203. .default_value = 0x0,
  204. .off = 0,
  205. /* NOTE: the value is converted and written to both even
  206. and odd registers in the code */
  207. .reg = MO_FILTER_ODD,
  208. .mask = 7 << 7,
  209. .shift = 7,
  210. }, {
  211. .id = V4L2_CID_CHROMA_AGC,
  212. .minimum = 0,
  213. .maximum = 1,
  214. .default_value = 0x1,
  215. .reg = MO_INPUT_FORMAT,
  216. .mask = 1 << 10,
  217. .shift = 10,
  218. }, {
  219. .id = V4L2_CID_COLOR_KILLER,
  220. .minimum = 0,
  221. .maximum = 1,
  222. .default_value = 0x1,
  223. .reg = MO_INPUT_FORMAT,
  224. .mask = 1 << 9,
  225. .shift = 9,
  226. }, {
  227. .id = V4L2_CID_BAND_STOP_FILTER,
  228. .minimum = 0,
  229. .maximum = 1,
  230. .step = 1,
  231. .default_value = 0x0,
  232. .off = 0,
  233. .reg = MO_HTOTAL,
  234. .mask = 3 << 11,
  235. .shift = 11,
  236. }
  237. };
  238. static const struct cx88_ctrl cx8800_aud_ctls[] = {
  239. {
  240. /* --- audio --- */
  241. .id = V4L2_CID_AUDIO_MUTE,
  242. .minimum = 0,
  243. .maximum = 1,
  244. .default_value = 1,
  245. .reg = AUD_VOL_CTL,
  246. .sreg = SHADOW_AUD_VOL_CTL,
  247. .mask = (1 << 6),
  248. .shift = 6,
  249. },{
  250. .id = V4L2_CID_AUDIO_VOLUME,
  251. .minimum = 0,
  252. .maximum = 0x3f,
  253. .step = 1,
  254. .default_value = 0x3f,
  255. .reg = AUD_VOL_CTL,
  256. .sreg = SHADOW_AUD_VOL_CTL,
  257. .mask = 0x3f,
  258. .shift = 0,
  259. },{
  260. .id = V4L2_CID_AUDIO_BALANCE,
  261. .minimum = 0,
  262. .maximum = 0x7f,
  263. .step = 1,
  264. .default_value = 0x40,
  265. .reg = AUD_BAL_CTL,
  266. .sreg = SHADOW_AUD_BAL_CTL,
  267. .mask = 0x7f,
  268. .shift = 0,
  269. }
  270. };
  271. enum {
  272. CX8800_VID_CTLS = ARRAY_SIZE(cx8800_vid_ctls),
  273. CX8800_AUD_CTLS = ARRAY_SIZE(cx8800_aud_ctls),
  274. };
  275. /* ------------------------------------------------------------------ */
  276. int cx88_video_mux(struct cx88_core *core, unsigned int input)
  277. {
  278. /* struct cx88_core *core = dev->core; */
  279. dprintk(1,"video_mux: %d [vmux=%d,gpio=0x%x,0x%x,0x%x,0x%x]\n",
  280. input, INPUT(input).vmux,
  281. INPUT(input).gpio0,INPUT(input).gpio1,
  282. INPUT(input).gpio2,INPUT(input).gpio3);
  283. core->input = input;
  284. cx_andor(MO_INPUT_FORMAT, 0x03 << 14, INPUT(input).vmux << 14);
  285. cx_write(MO_GP3_IO, INPUT(input).gpio3);
  286. cx_write(MO_GP0_IO, INPUT(input).gpio0);
  287. cx_write(MO_GP1_IO, INPUT(input).gpio1);
  288. cx_write(MO_GP2_IO, INPUT(input).gpio2);
  289. switch (INPUT(input).type) {
  290. case CX88_VMUX_SVIDEO:
  291. cx_set(MO_AFECFG_IO, 0x00000001);
  292. cx_set(MO_INPUT_FORMAT, 0x00010010);
  293. cx_set(MO_FILTER_EVEN, 0x00002020);
  294. cx_set(MO_FILTER_ODD, 0x00002020);
  295. break;
  296. default:
  297. cx_clear(MO_AFECFG_IO, 0x00000001);
  298. cx_clear(MO_INPUT_FORMAT, 0x00010010);
  299. cx_clear(MO_FILTER_EVEN, 0x00002020);
  300. cx_clear(MO_FILTER_ODD, 0x00002020);
  301. break;
  302. }
  303. /* if there are audioroutes defined, we have an external
  304. ADC to deal with audio */
  305. if (INPUT(input).audioroute) {
  306. /* The wm8775 module has the "2" route hardwired into
  307. the initialization. Some boards may use different
  308. routes for different inputs. HVR-1300 surely does */
  309. if (core->sd_wm8775) {
  310. call_all(core, audio, s_routing,
  311. INPUT(input).audioroute, 0, 0);
  312. }
  313. /* cx2388's C-ADC is connected to the tuner only.
  314. When used with S-Video, that ADC is busy dealing with
  315. chroma, so an external must be used for baseband audio */
  316. if (INPUT(input).type != CX88_VMUX_TELEVISION &&
  317. INPUT(input).type != CX88_VMUX_CABLE) {
  318. /* "I2S ADC mode" */
  319. core->tvaudio = WW_I2SADC;
  320. cx88_set_tvaudio(core);
  321. } else {
  322. /* Normal mode */
  323. cx_write(AUD_I2SCNTL, 0x0);
  324. cx_clear(AUD_CTL, EN_I2SIN_ENABLE);
  325. }
  326. }
  327. return 0;
  328. }
  329. EXPORT_SYMBOL(cx88_video_mux);
  330. /* ------------------------------------------------------------------ */
  331. static int start_video_dma(struct cx8800_dev *dev,
  332. struct cx88_dmaqueue *q,
  333. struct cx88_buffer *buf)
  334. {
  335. struct cx88_core *core = dev->core;
  336. /* setup fifo + format */
  337. cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH21],
  338. buf->bpl, buf->risc.dma);
  339. cx88_set_scale(core, core->width, core->height, core->field);
  340. cx_write(MO_COLOR_CTRL, dev->fmt->cxformat | ColorFormatGamma);
  341. /* reset counter */
  342. cx_write(MO_VIDY_GPCNTRL,GP_COUNT_CONTROL_RESET);
  343. q->count = 0;
  344. /* enable irqs */
  345. cx_set(MO_PCI_INTMSK, core->pci_irqmask | PCI_INT_VIDINT);
  346. /* Enables corresponding bits at PCI_INT_STAT:
  347. bits 0 to 4: video, audio, transport stream, VIP, Host
  348. bit 7: timer
  349. bits 8 and 9: DMA complete for: SRC, DST
  350. bits 10 and 11: BERR signal asserted for RISC: RD, WR
  351. bits 12 to 15: BERR signal asserted for: BRDG, SRC, DST, IPB
  352. */
  353. cx_set(MO_VID_INTMSK, 0x0f0011);
  354. /* enable capture */
  355. cx_set(VID_CAPTURE_CONTROL,0x06);
  356. /* start dma */
  357. cx_set(MO_DEV_CNTRL2, (1<<5));
  358. cx_set(MO_VID_DMACNTRL, 0x11); /* Planar Y and packed FIFO and RISC enable */
  359. return 0;
  360. }
  361. #ifdef CONFIG_PM
  362. static int stop_video_dma(struct cx8800_dev *dev)
  363. {
  364. struct cx88_core *core = dev->core;
  365. /* stop dma */
  366. cx_clear(MO_VID_DMACNTRL, 0x11);
  367. /* disable capture */
  368. cx_clear(VID_CAPTURE_CONTROL,0x06);
  369. /* disable irqs */
  370. cx_clear(MO_PCI_INTMSK, PCI_INT_VIDINT);
  371. cx_clear(MO_VID_INTMSK, 0x0f0011);
  372. return 0;
  373. }
  374. static int restart_video_queue(struct cx8800_dev *dev,
  375. struct cx88_dmaqueue *q)
  376. {
  377. struct cx88_core *core = dev->core;
  378. struct cx88_buffer *buf;
  379. if (!list_empty(&q->active)) {
  380. buf = list_entry(q->active.next, struct cx88_buffer, list);
  381. dprintk(2,"restart_queue [%p/%d]: restart dma\n",
  382. buf, buf->vb.vb2_buf.index);
  383. start_video_dma(dev, q, buf);
  384. }
  385. return 0;
  386. }
  387. #endif
  388. /* ------------------------------------------------------------------ */
  389. static int queue_setup(struct vb2_queue *q, const void *parg,
  390. unsigned int *num_buffers, unsigned int *num_planes,
  391. unsigned int sizes[], void *alloc_ctxs[])
  392. {
  393. struct cx8800_dev *dev = q->drv_priv;
  394. struct cx88_core *core = dev->core;
  395. *num_planes = 1;
  396. sizes[0] = (dev->fmt->depth * core->width * core->height) >> 3;
  397. alloc_ctxs[0] = dev->alloc_ctx;
  398. return 0;
  399. }
  400. static int buffer_prepare(struct vb2_buffer *vb)
  401. {
  402. struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
  403. struct cx8800_dev *dev = vb->vb2_queue->drv_priv;
  404. struct cx88_core *core = dev->core;
  405. struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
  406. struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
  407. buf->bpl = core->width * dev->fmt->depth >> 3;
  408. if (vb2_plane_size(vb, 0) < core->height * buf->bpl)
  409. return -EINVAL;
  410. vb2_set_plane_payload(vb, 0, core->height * buf->bpl);
  411. switch (core->field) {
  412. case V4L2_FIELD_TOP:
  413. cx88_risc_buffer(dev->pci, &buf->risc,
  414. sgt->sgl, 0, UNSET,
  415. buf->bpl, 0, core->height);
  416. break;
  417. case V4L2_FIELD_BOTTOM:
  418. cx88_risc_buffer(dev->pci, &buf->risc,
  419. sgt->sgl, UNSET, 0,
  420. buf->bpl, 0, core->height);
  421. break;
  422. case V4L2_FIELD_SEQ_TB:
  423. cx88_risc_buffer(dev->pci, &buf->risc,
  424. sgt->sgl,
  425. 0, buf->bpl * (core->height >> 1),
  426. buf->bpl, 0,
  427. core->height >> 1);
  428. break;
  429. case V4L2_FIELD_SEQ_BT:
  430. cx88_risc_buffer(dev->pci, &buf->risc,
  431. sgt->sgl,
  432. buf->bpl * (core->height >> 1), 0,
  433. buf->bpl, 0,
  434. core->height >> 1);
  435. break;
  436. case V4L2_FIELD_INTERLACED:
  437. default:
  438. cx88_risc_buffer(dev->pci, &buf->risc,
  439. sgt->sgl, 0, buf->bpl,
  440. buf->bpl, buf->bpl,
  441. core->height >> 1);
  442. break;
  443. }
  444. dprintk(2,"[%p/%d] buffer_prepare - %dx%d %dbpp \"%s\" - dma=0x%08lx\n",
  445. buf, buf->vb.vb2_buf.index,
  446. core->width, core->height, dev->fmt->depth, dev->fmt->name,
  447. (unsigned long)buf->risc.dma);
  448. return 0;
  449. }
  450. static void buffer_finish(struct vb2_buffer *vb)
  451. {
  452. struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
  453. struct cx8800_dev *dev = vb->vb2_queue->drv_priv;
  454. struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
  455. struct cx88_riscmem *risc = &buf->risc;
  456. if (risc->cpu)
  457. pci_free_consistent(dev->pci, risc->size, risc->cpu, risc->dma);
  458. memset(risc, 0, sizeof(*risc));
  459. }
  460. static void buffer_queue(struct vb2_buffer *vb)
  461. {
  462. struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
  463. struct cx8800_dev *dev = vb->vb2_queue->drv_priv;
  464. struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
  465. struct cx88_buffer *prev;
  466. struct cx88_core *core = dev->core;
  467. struct cx88_dmaqueue *q = &dev->vidq;
  468. /* add jump to start */
  469. buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 8);
  470. buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC);
  471. buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 8);
  472. if (list_empty(&q->active)) {
  473. list_add_tail(&buf->list, &q->active);
  474. dprintk(2,"[%p/%d] buffer_queue - first active\n",
  475. buf, buf->vb.vb2_buf.index);
  476. } else {
  477. buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1);
  478. prev = list_entry(q->active.prev, struct cx88_buffer, list);
  479. list_add_tail(&buf->list, &q->active);
  480. prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
  481. dprintk(2, "[%p/%d] buffer_queue - append to active\n",
  482. buf, buf->vb.vb2_buf.index);
  483. }
  484. }
  485. static int start_streaming(struct vb2_queue *q, unsigned int count)
  486. {
  487. struct cx8800_dev *dev = q->drv_priv;
  488. struct cx88_dmaqueue *dmaq = &dev->vidq;
  489. struct cx88_buffer *buf = list_entry(dmaq->active.next,
  490. struct cx88_buffer, list);
  491. start_video_dma(dev, dmaq, buf);
  492. return 0;
  493. }
  494. static void stop_streaming(struct vb2_queue *q)
  495. {
  496. struct cx8800_dev *dev = q->drv_priv;
  497. struct cx88_core *core = dev->core;
  498. struct cx88_dmaqueue *dmaq = &dev->vidq;
  499. unsigned long flags;
  500. cx_clear(MO_VID_DMACNTRL, 0x11);
  501. cx_clear(VID_CAPTURE_CONTROL, 0x06);
  502. spin_lock_irqsave(&dev->slock, flags);
  503. while (!list_empty(&dmaq->active)) {
  504. struct cx88_buffer *buf = list_entry(dmaq->active.next,
  505. struct cx88_buffer, list);
  506. list_del(&buf->list);
  507. vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
  508. }
  509. spin_unlock_irqrestore(&dev->slock, flags);
  510. }
  511. static struct vb2_ops cx8800_video_qops = {
  512. .queue_setup = queue_setup,
  513. .buf_prepare = buffer_prepare,
  514. .buf_finish = buffer_finish,
  515. .buf_queue = buffer_queue,
  516. .wait_prepare = vb2_ops_wait_prepare,
  517. .wait_finish = vb2_ops_wait_finish,
  518. .start_streaming = start_streaming,
  519. .stop_streaming = stop_streaming,
  520. };
  521. /* ------------------------------------------------------------------ */
  522. static int radio_open(struct file *file)
  523. {
  524. struct cx8800_dev *dev = video_drvdata(file);
  525. struct cx88_core *core = dev->core;
  526. int ret = v4l2_fh_open(file);
  527. if (ret)
  528. return ret;
  529. cx_write(MO_GP3_IO, core->board.radio.gpio3);
  530. cx_write(MO_GP0_IO, core->board.radio.gpio0);
  531. cx_write(MO_GP1_IO, core->board.radio.gpio1);
  532. cx_write(MO_GP2_IO, core->board.radio.gpio2);
  533. if (core->board.radio.audioroute) {
  534. if (core->sd_wm8775) {
  535. call_all(core, audio, s_routing,
  536. core->board.radio.audioroute, 0, 0);
  537. }
  538. /* "I2S ADC mode" */
  539. core->tvaudio = WW_I2SADC;
  540. cx88_set_tvaudio(core);
  541. } else {
  542. /* FM Mode */
  543. core->tvaudio = WW_FM;
  544. cx88_set_tvaudio(core);
  545. cx88_set_stereo(core, V4L2_TUNER_MODE_STEREO, 1);
  546. }
  547. call_all(core, tuner, s_radio);
  548. return 0;
  549. }
  550. /* ------------------------------------------------------------------ */
  551. /* VIDEO CTRL IOCTLS */
  552. static int cx8800_s_vid_ctrl(struct v4l2_ctrl *ctrl)
  553. {
  554. struct cx88_core *core =
  555. container_of(ctrl->handler, struct cx88_core, video_hdl);
  556. const struct cx88_ctrl *cc = ctrl->priv;
  557. u32 value, mask;
  558. mask = cc->mask;
  559. switch (ctrl->id) {
  560. case V4L2_CID_SATURATION:
  561. /* special v_sat handling */
  562. value = ((ctrl->val - cc->off) << cc->shift) & cc->mask;
  563. if (core->tvnorm & V4L2_STD_SECAM) {
  564. /* For SECAM, both U and V sat should be equal */
  565. value = value << 8 | value;
  566. } else {
  567. /* Keeps U Saturation proportional to V Sat */
  568. value = (value * 0x5a) / 0x7f << 8 | value;
  569. }
  570. mask = 0xffff;
  571. break;
  572. case V4L2_CID_SHARPNESS:
  573. /* 0b000, 0b100, 0b101, 0b110, or 0b111 */
  574. value = (ctrl->val < 1 ? 0 : ((ctrl->val + 3) << 7));
  575. /* needs to be set for both fields */
  576. cx_andor(MO_FILTER_EVEN, mask, value);
  577. break;
  578. case V4L2_CID_CHROMA_AGC:
  579. value = ((ctrl->val - cc->off) << cc->shift) & cc->mask;
  580. break;
  581. default:
  582. value = ((ctrl->val - cc->off) << cc->shift) & cc->mask;
  583. break;
  584. }
  585. dprintk(1, "set_control id=0x%X(%s) ctrl=0x%02x, reg=0x%02x val=0x%02x (mask 0x%02x)%s\n",
  586. ctrl->id, ctrl->name, ctrl->val, cc->reg, value,
  587. mask, cc->sreg ? " [shadowed]" : "");
  588. if (cc->sreg)
  589. cx_sandor(cc->sreg, cc->reg, mask, value);
  590. else
  591. cx_andor(cc->reg, mask, value);
  592. return 0;
  593. }
  594. static int cx8800_s_aud_ctrl(struct v4l2_ctrl *ctrl)
  595. {
  596. struct cx88_core *core =
  597. container_of(ctrl->handler, struct cx88_core, audio_hdl);
  598. const struct cx88_ctrl *cc = ctrl->priv;
  599. u32 value,mask;
  600. /* Pass changes onto any WM8775 */
  601. if (core->sd_wm8775) {
  602. switch (ctrl->id) {
  603. case V4L2_CID_AUDIO_MUTE:
  604. wm8775_s_ctrl(core, ctrl->id, ctrl->val);
  605. break;
  606. case V4L2_CID_AUDIO_VOLUME:
  607. wm8775_s_ctrl(core, ctrl->id, (ctrl->val) ?
  608. (0x90 + ctrl->val) << 8 : 0);
  609. break;
  610. case V4L2_CID_AUDIO_BALANCE:
  611. wm8775_s_ctrl(core, ctrl->id, ctrl->val << 9);
  612. break;
  613. default:
  614. break;
  615. }
  616. }
  617. mask = cc->mask;
  618. switch (ctrl->id) {
  619. case V4L2_CID_AUDIO_BALANCE:
  620. value = (ctrl->val < 0x40) ? (0x7f - ctrl->val) : (ctrl->val - 0x40);
  621. break;
  622. case V4L2_CID_AUDIO_VOLUME:
  623. value = 0x3f - (ctrl->val & 0x3f);
  624. break;
  625. default:
  626. value = ((ctrl->val - cc->off) << cc->shift) & cc->mask;
  627. break;
  628. }
  629. dprintk(1,"set_control id=0x%X(%s) ctrl=0x%02x, reg=0x%02x val=0x%02x (mask 0x%02x)%s\n",
  630. ctrl->id, ctrl->name, ctrl->val, cc->reg, value,
  631. mask, cc->sreg ? " [shadowed]" : "");
  632. if (cc->sreg)
  633. cx_sandor(cc->sreg, cc->reg, mask, value);
  634. else
  635. cx_andor(cc->reg, mask, value);
  636. return 0;
  637. }
  638. /* ------------------------------------------------------------------ */
  639. /* VIDEO IOCTLS */
  640. static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
  641. struct v4l2_format *f)
  642. {
  643. struct cx8800_dev *dev = video_drvdata(file);
  644. struct cx88_core *core = dev->core;
  645. f->fmt.pix.width = core->width;
  646. f->fmt.pix.height = core->height;
  647. f->fmt.pix.field = core->field;
  648. f->fmt.pix.pixelformat = dev->fmt->fourcc;
  649. f->fmt.pix.bytesperline =
  650. (f->fmt.pix.width * dev->fmt->depth) >> 3;
  651. f->fmt.pix.sizeimage =
  652. f->fmt.pix.height * f->fmt.pix.bytesperline;
  653. f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
  654. return 0;
  655. }
  656. static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
  657. struct v4l2_format *f)
  658. {
  659. struct cx8800_dev *dev = video_drvdata(file);
  660. struct cx88_core *core = dev->core;
  661. const struct cx8800_fmt *fmt;
  662. enum v4l2_field field;
  663. unsigned int maxw, maxh;
  664. fmt = format_by_fourcc(f->fmt.pix.pixelformat);
  665. if (NULL == fmt)
  666. return -EINVAL;
  667. maxw = norm_maxw(core->tvnorm);
  668. maxh = norm_maxh(core->tvnorm);
  669. field = f->fmt.pix.field;
  670. switch (field) {
  671. case V4L2_FIELD_TOP:
  672. case V4L2_FIELD_BOTTOM:
  673. case V4L2_FIELD_INTERLACED:
  674. case V4L2_FIELD_SEQ_BT:
  675. case V4L2_FIELD_SEQ_TB:
  676. break;
  677. default:
  678. field = (f->fmt.pix.height > maxh / 2)
  679. ? V4L2_FIELD_INTERLACED
  680. : V4L2_FIELD_BOTTOM;
  681. break;
  682. }
  683. if (V4L2_FIELD_HAS_T_OR_B(field))
  684. maxh /= 2;
  685. v4l_bound_align_image(&f->fmt.pix.width, 48, maxw, 2,
  686. &f->fmt.pix.height, 32, maxh, 0, 0);
  687. f->fmt.pix.field = field;
  688. f->fmt.pix.bytesperline =
  689. (f->fmt.pix.width * fmt->depth) >> 3;
  690. f->fmt.pix.sizeimage =
  691. f->fmt.pix.height * f->fmt.pix.bytesperline;
  692. f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
  693. return 0;
  694. }
  695. static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
  696. struct v4l2_format *f)
  697. {
  698. struct cx8800_dev *dev = video_drvdata(file);
  699. struct cx88_core *core = dev->core;
  700. int err = vidioc_try_fmt_vid_cap (file,priv,f);
  701. if (0 != err)
  702. return err;
  703. if (vb2_is_busy(&dev->vb2_vidq) || vb2_is_busy(&dev->vb2_vbiq))
  704. return -EBUSY;
  705. if (core->dvbdev && vb2_is_busy(&core->dvbdev->vb2_mpegq))
  706. return -EBUSY;
  707. dev->fmt = format_by_fourcc(f->fmt.pix.pixelformat);
  708. core->width = f->fmt.pix.width;
  709. core->height = f->fmt.pix.height;
  710. core->field = f->fmt.pix.field;
  711. return 0;
  712. }
  713. void cx88_querycap(struct file *file, struct cx88_core *core,
  714. struct v4l2_capability *cap)
  715. {
  716. struct video_device *vdev = video_devdata(file);
  717. strlcpy(cap->card, core->board.name, sizeof(cap->card));
  718. cap->device_caps = V4L2_CAP_READWRITE | V4L2_CAP_STREAMING;
  719. if (UNSET != core->board.tuner_type)
  720. cap->device_caps |= V4L2_CAP_TUNER;
  721. switch (vdev->vfl_type) {
  722. case VFL_TYPE_RADIO:
  723. cap->device_caps = V4L2_CAP_RADIO | V4L2_CAP_TUNER;
  724. break;
  725. case VFL_TYPE_GRABBER:
  726. cap->device_caps |= V4L2_CAP_VIDEO_CAPTURE;
  727. break;
  728. case VFL_TYPE_VBI:
  729. cap->device_caps |= V4L2_CAP_VBI_CAPTURE;
  730. break;
  731. }
  732. cap->capabilities = cap->device_caps | V4L2_CAP_VIDEO_CAPTURE |
  733. V4L2_CAP_VBI_CAPTURE | V4L2_CAP_DEVICE_CAPS;
  734. if (core->board.radio.type == CX88_RADIO)
  735. cap->capabilities |= V4L2_CAP_RADIO;
  736. }
  737. EXPORT_SYMBOL(cx88_querycap);
  738. static int vidioc_querycap(struct file *file, void *priv,
  739. struct v4l2_capability *cap)
  740. {
  741. struct cx8800_dev *dev = video_drvdata(file);
  742. struct cx88_core *core = dev->core;
  743. strcpy(cap->driver, "cx8800");
  744. sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci));
  745. cx88_querycap(file, core, cap);
  746. return 0;
  747. }
  748. static int vidioc_enum_fmt_vid_cap (struct file *file, void *priv,
  749. struct v4l2_fmtdesc *f)
  750. {
  751. if (unlikely(f->index >= ARRAY_SIZE(formats)))
  752. return -EINVAL;
  753. strlcpy(f->description,formats[f->index].name,sizeof(f->description));
  754. f->pixelformat = formats[f->index].fourcc;
  755. return 0;
  756. }
  757. static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *tvnorm)
  758. {
  759. struct cx8800_dev *dev = video_drvdata(file);
  760. struct cx88_core *core = dev->core;
  761. *tvnorm = core->tvnorm;
  762. return 0;
  763. }
  764. static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id tvnorms)
  765. {
  766. struct cx8800_dev *dev = video_drvdata(file);
  767. struct cx88_core *core = dev->core;
  768. return cx88_set_tvnorm(core, tvnorms);
  769. }
  770. /* only one input in this sample driver */
  771. int cx88_enum_input (struct cx88_core *core,struct v4l2_input *i)
  772. {
  773. static const char * const iname[] = {
  774. [ CX88_VMUX_COMPOSITE1 ] = "Composite1",
  775. [ CX88_VMUX_COMPOSITE2 ] = "Composite2",
  776. [ CX88_VMUX_COMPOSITE3 ] = "Composite3",
  777. [ CX88_VMUX_COMPOSITE4 ] = "Composite4",
  778. [ CX88_VMUX_SVIDEO ] = "S-Video",
  779. [ CX88_VMUX_TELEVISION ] = "Television",
  780. [ CX88_VMUX_CABLE ] = "Cable TV",
  781. [ CX88_VMUX_DVB ] = "DVB",
  782. [ CX88_VMUX_DEBUG ] = "for debug only",
  783. };
  784. unsigned int n = i->index;
  785. if (n >= 4)
  786. return -EINVAL;
  787. if (0 == INPUT(n).type)
  788. return -EINVAL;
  789. i->type = V4L2_INPUT_TYPE_CAMERA;
  790. strcpy(i->name,iname[INPUT(n).type]);
  791. if ((CX88_VMUX_TELEVISION == INPUT(n).type) ||
  792. (CX88_VMUX_CABLE == INPUT(n).type)) {
  793. i->type = V4L2_INPUT_TYPE_TUNER;
  794. }
  795. i->std = CX88_NORMS;
  796. return 0;
  797. }
  798. EXPORT_SYMBOL(cx88_enum_input);
  799. static int vidioc_enum_input (struct file *file, void *priv,
  800. struct v4l2_input *i)
  801. {
  802. struct cx8800_dev *dev = video_drvdata(file);
  803. struct cx88_core *core = dev->core;
  804. return cx88_enum_input (core,i);
  805. }
  806. static int vidioc_g_input (struct file *file, void *priv, unsigned int *i)
  807. {
  808. struct cx8800_dev *dev = video_drvdata(file);
  809. struct cx88_core *core = dev->core;
  810. *i = core->input;
  811. return 0;
  812. }
  813. static int vidioc_s_input (struct file *file, void *priv, unsigned int i)
  814. {
  815. struct cx8800_dev *dev = video_drvdata(file);
  816. struct cx88_core *core = dev->core;
  817. if (i >= 4)
  818. return -EINVAL;
  819. if (0 == INPUT(i).type)
  820. return -EINVAL;
  821. cx88_newstation(core);
  822. cx88_video_mux(core,i);
  823. return 0;
  824. }
  825. static int vidioc_g_tuner (struct file *file, void *priv,
  826. struct v4l2_tuner *t)
  827. {
  828. struct cx8800_dev *dev = video_drvdata(file);
  829. struct cx88_core *core = dev->core;
  830. u32 reg;
  831. if (unlikely(UNSET == core->board.tuner_type))
  832. return -EINVAL;
  833. if (0 != t->index)
  834. return -EINVAL;
  835. strcpy(t->name, "Television");
  836. t->capability = V4L2_TUNER_CAP_NORM;
  837. t->rangehigh = 0xffffffffUL;
  838. call_all(core, tuner, g_tuner, t);
  839. cx88_get_stereo(core ,t);
  840. reg = cx_read(MO_DEVICE_STATUS);
  841. t->signal = (reg & (1<<5)) ? 0xffff : 0x0000;
  842. return 0;
  843. }
  844. static int vidioc_s_tuner (struct file *file, void *priv,
  845. const struct v4l2_tuner *t)
  846. {
  847. struct cx8800_dev *dev = video_drvdata(file);
  848. struct cx88_core *core = dev->core;
  849. if (UNSET == core->board.tuner_type)
  850. return -EINVAL;
  851. if (0 != t->index)
  852. return -EINVAL;
  853. cx88_set_stereo(core, t->audmode, 1);
  854. return 0;
  855. }
  856. static int vidioc_g_frequency (struct file *file, void *priv,
  857. struct v4l2_frequency *f)
  858. {
  859. struct cx8800_dev *dev = video_drvdata(file);
  860. struct cx88_core *core = dev->core;
  861. if (unlikely(UNSET == core->board.tuner_type))
  862. return -EINVAL;
  863. if (f->tuner)
  864. return -EINVAL;
  865. f->frequency = core->freq;
  866. call_all(core, tuner, g_frequency, f);
  867. return 0;
  868. }
  869. int cx88_set_freq (struct cx88_core *core,
  870. const struct v4l2_frequency *f)
  871. {
  872. struct v4l2_frequency new_freq = *f;
  873. if (unlikely(UNSET == core->board.tuner_type))
  874. return -EINVAL;
  875. if (unlikely(f->tuner != 0))
  876. return -EINVAL;
  877. cx88_newstation(core);
  878. call_all(core, tuner, s_frequency, f);
  879. call_all(core, tuner, g_frequency, &new_freq);
  880. core->freq = new_freq.frequency;
  881. /* When changing channels it is required to reset TVAUDIO */
  882. msleep (10);
  883. cx88_set_tvaudio(core);
  884. return 0;
  885. }
  886. EXPORT_SYMBOL(cx88_set_freq);
  887. static int vidioc_s_frequency (struct file *file, void *priv,
  888. const struct v4l2_frequency *f)
  889. {
  890. struct cx8800_dev *dev = video_drvdata(file);
  891. struct cx88_core *core = dev->core;
  892. return cx88_set_freq(core, f);
  893. }
  894. #ifdef CONFIG_VIDEO_ADV_DEBUG
  895. static int vidioc_g_register (struct file *file, void *fh,
  896. struct v4l2_dbg_register *reg)
  897. {
  898. struct cx8800_dev *dev = video_drvdata(file);
  899. struct cx88_core *core = dev->core;
  900. /* cx2388x has a 24-bit register space */
  901. reg->val = cx_read(reg->reg & 0xfffffc);
  902. reg->size = 4;
  903. return 0;
  904. }
  905. static int vidioc_s_register (struct file *file, void *fh,
  906. const struct v4l2_dbg_register *reg)
  907. {
  908. struct cx8800_dev *dev = video_drvdata(file);
  909. struct cx88_core *core = dev->core;
  910. cx_write(reg->reg & 0xfffffc, reg->val);
  911. return 0;
  912. }
  913. #endif
  914. /* ----------------------------------------------------------- */
  915. /* RADIO ESPECIFIC IOCTLS */
  916. /* ----------------------------------------------------------- */
  917. static int radio_g_tuner (struct file *file, void *priv,
  918. struct v4l2_tuner *t)
  919. {
  920. struct cx8800_dev *dev = video_drvdata(file);
  921. struct cx88_core *core = dev->core;
  922. if (unlikely(t->index > 0))
  923. return -EINVAL;
  924. strcpy(t->name, "Radio");
  925. call_all(core, tuner, g_tuner, t);
  926. return 0;
  927. }
  928. static int radio_s_tuner (struct file *file, void *priv,
  929. const struct v4l2_tuner *t)
  930. {
  931. struct cx8800_dev *dev = video_drvdata(file);
  932. struct cx88_core *core = dev->core;
  933. if (0 != t->index)
  934. return -EINVAL;
  935. call_all(core, tuner, s_tuner, t);
  936. return 0;
  937. }
  938. /* ----------------------------------------------------------- */
  939. static const char *cx88_vid_irqs[32] = {
  940. "y_risci1", "u_risci1", "v_risci1", "vbi_risc1",
  941. "y_risci2", "u_risci2", "v_risci2", "vbi_risc2",
  942. "y_oflow", "u_oflow", "v_oflow", "vbi_oflow",
  943. "y_sync", "u_sync", "v_sync", "vbi_sync",
  944. "opc_err", "par_err", "rip_err", "pci_abort",
  945. };
  946. static void cx8800_vid_irq(struct cx8800_dev *dev)
  947. {
  948. struct cx88_core *core = dev->core;
  949. u32 status, mask, count;
  950. status = cx_read(MO_VID_INTSTAT);
  951. mask = cx_read(MO_VID_INTMSK);
  952. if (0 == (status & mask))
  953. return;
  954. cx_write(MO_VID_INTSTAT, status);
  955. if (irq_debug || (status & mask & ~0xff))
  956. cx88_print_irqbits(core->name, "irq vid",
  957. cx88_vid_irqs, ARRAY_SIZE(cx88_vid_irqs),
  958. status, mask);
  959. /* risc op code error */
  960. if (status & (1 << 16)) {
  961. printk(KERN_WARNING "%s/0: video risc op code error\n",core->name);
  962. cx_clear(MO_VID_DMACNTRL, 0x11);
  963. cx_clear(VID_CAPTURE_CONTROL, 0x06);
  964. cx88_sram_channel_dump(core, &cx88_sram_channels[SRAM_CH21]);
  965. }
  966. /* risc1 y */
  967. if (status & 0x01) {
  968. spin_lock(&dev->slock);
  969. count = cx_read(MO_VIDY_GPCNT);
  970. cx88_wakeup(core, &dev->vidq, count);
  971. spin_unlock(&dev->slock);
  972. }
  973. /* risc1 vbi */
  974. if (status & 0x08) {
  975. spin_lock(&dev->slock);
  976. count = cx_read(MO_VBI_GPCNT);
  977. cx88_wakeup(core, &dev->vbiq, count);
  978. spin_unlock(&dev->slock);
  979. }
  980. }
  981. static irqreturn_t cx8800_irq(int irq, void *dev_id)
  982. {
  983. struct cx8800_dev *dev = dev_id;
  984. struct cx88_core *core = dev->core;
  985. u32 status;
  986. int loop, handled = 0;
  987. for (loop = 0; loop < 10; loop++) {
  988. status = cx_read(MO_PCI_INTSTAT) &
  989. (core->pci_irqmask | PCI_INT_VIDINT);
  990. if (0 == status)
  991. goto out;
  992. cx_write(MO_PCI_INTSTAT, status);
  993. handled = 1;
  994. if (status & core->pci_irqmask)
  995. cx88_core_irq(core,status);
  996. if (status & PCI_INT_VIDINT)
  997. cx8800_vid_irq(dev);
  998. }
  999. if (10 == loop) {
  1000. printk(KERN_WARNING "%s/0: irq loop -- clearing mask\n",
  1001. core->name);
  1002. cx_write(MO_PCI_INTMSK,0);
  1003. }
  1004. out:
  1005. return IRQ_RETVAL(handled);
  1006. }
  1007. /* ----------------------------------------------------------- */
  1008. /* exported stuff */
  1009. static const struct v4l2_file_operations video_fops =
  1010. {
  1011. .owner = THIS_MODULE,
  1012. .open = v4l2_fh_open,
  1013. .release = vb2_fop_release,
  1014. .read = vb2_fop_read,
  1015. .poll = vb2_fop_poll,
  1016. .mmap = vb2_fop_mmap,
  1017. .unlocked_ioctl = video_ioctl2,
  1018. };
  1019. static const struct v4l2_ioctl_ops video_ioctl_ops = {
  1020. .vidioc_querycap = vidioc_querycap,
  1021. .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
  1022. .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
  1023. .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
  1024. .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
  1025. .vidioc_reqbufs = vb2_ioctl_reqbufs,
  1026. .vidioc_querybuf = vb2_ioctl_querybuf,
  1027. .vidioc_qbuf = vb2_ioctl_qbuf,
  1028. .vidioc_dqbuf = vb2_ioctl_dqbuf,
  1029. .vidioc_g_std = vidioc_g_std,
  1030. .vidioc_s_std = vidioc_s_std,
  1031. .vidioc_enum_input = vidioc_enum_input,
  1032. .vidioc_g_input = vidioc_g_input,
  1033. .vidioc_s_input = vidioc_s_input,
  1034. .vidioc_streamon = vb2_ioctl_streamon,
  1035. .vidioc_streamoff = vb2_ioctl_streamoff,
  1036. .vidioc_g_tuner = vidioc_g_tuner,
  1037. .vidioc_s_tuner = vidioc_s_tuner,
  1038. .vidioc_g_frequency = vidioc_g_frequency,
  1039. .vidioc_s_frequency = vidioc_s_frequency,
  1040. .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
  1041. .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
  1042. #ifdef CONFIG_VIDEO_ADV_DEBUG
  1043. .vidioc_g_register = vidioc_g_register,
  1044. .vidioc_s_register = vidioc_s_register,
  1045. #endif
  1046. };
  1047. static const struct video_device cx8800_video_template = {
  1048. .name = "cx8800-video",
  1049. .fops = &video_fops,
  1050. .ioctl_ops = &video_ioctl_ops,
  1051. .tvnorms = CX88_NORMS,
  1052. };
  1053. static const struct v4l2_ioctl_ops vbi_ioctl_ops = {
  1054. .vidioc_querycap = vidioc_querycap,
  1055. .vidioc_g_fmt_vbi_cap = cx8800_vbi_fmt,
  1056. .vidioc_try_fmt_vbi_cap = cx8800_vbi_fmt,
  1057. .vidioc_s_fmt_vbi_cap = cx8800_vbi_fmt,
  1058. .vidioc_reqbufs = vb2_ioctl_reqbufs,
  1059. .vidioc_querybuf = vb2_ioctl_querybuf,
  1060. .vidioc_qbuf = vb2_ioctl_qbuf,
  1061. .vidioc_dqbuf = vb2_ioctl_dqbuf,
  1062. .vidioc_g_std = vidioc_g_std,
  1063. .vidioc_s_std = vidioc_s_std,
  1064. .vidioc_enum_input = vidioc_enum_input,
  1065. .vidioc_g_input = vidioc_g_input,
  1066. .vidioc_s_input = vidioc_s_input,
  1067. .vidioc_streamon = vb2_ioctl_streamon,
  1068. .vidioc_streamoff = vb2_ioctl_streamoff,
  1069. .vidioc_g_tuner = vidioc_g_tuner,
  1070. .vidioc_s_tuner = vidioc_s_tuner,
  1071. .vidioc_g_frequency = vidioc_g_frequency,
  1072. .vidioc_s_frequency = vidioc_s_frequency,
  1073. #ifdef CONFIG_VIDEO_ADV_DEBUG
  1074. .vidioc_g_register = vidioc_g_register,
  1075. .vidioc_s_register = vidioc_s_register,
  1076. #endif
  1077. };
  1078. static const struct video_device cx8800_vbi_template = {
  1079. .name = "cx8800-vbi",
  1080. .fops = &video_fops,
  1081. .ioctl_ops = &vbi_ioctl_ops,
  1082. .tvnorms = CX88_NORMS,
  1083. };
  1084. static const struct v4l2_file_operations radio_fops =
  1085. {
  1086. .owner = THIS_MODULE,
  1087. .open = radio_open,
  1088. .poll = v4l2_ctrl_poll,
  1089. .release = v4l2_fh_release,
  1090. .unlocked_ioctl = video_ioctl2,
  1091. };
  1092. static const struct v4l2_ioctl_ops radio_ioctl_ops = {
  1093. .vidioc_querycap = vidioc_querycap,
  1094. .vidioc_g_tuner = radio_g_tuner,
  1095. .vidioc_s_tuner = radio_s_tuner,
  1096. .vidioc_g_frequency = vidioc_g_frequency,
  1097. .vidioc_s_frequency = vidioc_s_frequency,
  1098. .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
  1099. .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
  1100. #ifdef CONFIG_VIDEO_ADV_DEBUG
  1101. .vidioc_g_register = vidioc_g_register,
  1102. .vidioc_s_register = vidioc_s_register,
  1103. #endif
  1104. };
  1105. static const struct video_device cx8800_radio_template = {
  1106. .name = "cx8800-radio",
  1107. .fops = &radio_fops,
  1108. .ioctl_ops = &radio_ioctl_ops,
  1109. };
  1110. static const struct v4l2_ctrl_ops cx8800_ctrl_vid_ops = {
  1111. .s_ctrl = cx8800_s_vid_ctrl,
  1112. };
  1113. static const struct v4l2_ctrl_ops cx8800_ctrl_aud_ops = {
  1114. .s_ctrl = cx8800_s_aud_ctrl,
  1115. };
  1116. /* ----------------------------------------------------------- */
  1117. static void cx8800_unregister_video(struct cx8800_dev *dev)
  1118. {
  1119. video_unregister_device(&dev->radio_dev);
  1120. video_unregister_device(&dev->vbi_dev);
  1121. video_unregister_device(&dev->video_dev);
  1122. }
  1123. static int cx8800_initdev(struct pci_dev *pci_dev,
  1124. const struct pci_device_id *pci_id)
  1125. {
  1126. struct cx8800_dev *dev;
  1127. struct cx88_core *core;
  1128. struct vb2_queue *q;
  1129. int err;
  1130. int i;
  1131. dev = kzalloc(sizeof(*dev),GFP_KERNEL);
  1132. if (NULL == dev)
  1133. return -ENOMEM;
  1134. /* pci init */
  1135. dev->pci = pci_dev;
  1136. if (pci_enable_device(pci_dev)) {
  1137. err = -EIO;
  1138. goto fail_free;
  1139. }
  1140. core = cx88_core_get(dev->pci);
  1141. if (NULL == core) {
  1142. err = -EINVAL;
  1143. goto fail_free;
  1144. }
  1145. dev->core = core;
  1146. /* print pci info */
  1147. dev->pci_rev = pci_dev->revision;
  1148. pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
  1149. printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
  1150. "latency: %d, mmio: 0x%llx\n", core->name,
  1151. pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
  1152. dev->pci_lat,(unsigned long long)pci_resource_start(pci_dev,0));
  1153. pci_set_master(pci_dev);
  1154. err = pci_set_dma_mask(pci_dev,DMA_BIT_MASK(32));
  1155. if (err) {
  1156. printk("%s/0: Oops: no 32bit PCI DMA ???\n",core->name);
  1157. goto fail_core;
  1158. }
  1159. dev->alloc_ctx = vb2_dma_sg_init_ctx(&pci_dev->dev);
  1160. if (IS_ERR(dev->alloc_ctx)) {
  1161. err = PTR_ERR(dev->alloc_ctx);
  1162. goto fail_core;
  1163. }
  1164. /* initialize driver struct */
  1165. spin_lock_init(&dev->slock);
  1166. /* init video dma queues */
  1167. INIT_LIST_HEAD(&dev->vidq.active);
  1168. /* init vbi dma queues */
  1169. INIT_LIST_HEAD(&dev->vbiq.active);
  1170. /* get irq */
  1171. err = request_irq(pci_dev->irq, cx8800_irq,
  1172. IRQF_SHARED, core->name, dev);
  1173. if (err < 0) {
  1174. printk(KERN_ERR "%s/0: can't get IRQ %d\n",
  1175. core->name,pci_dev->irq);
  1176. goto fail_core;
  1177. }
  1178. cx_set(MO_PCI_INTMSK, core->pci_irqmask);
  1179. for (i = 0; i < CX8800_AUD_CTLS; i++) {
  1180. const struct cx88_ctrl *cc = &cx8800_aud_ctls[i];
  1181. struct v4l2_ctrl *vc;
  1182. vc = v4l2_ctrl_new_std(&core->audio_hdl, &cx8800_ctrl_aud_ops,
  1183. cc->id, cc->minimum, cc->maximum, cc->step, cc->default_value);
  1184. if (vc == NULL) {
  1185. err = core->audio_hdl.error;
  1186. goto fail_core;
  1187. }
  1188. vc->priv = (void *)cc;
  1189. }
  1190. for (i = 0; i < CX8800_VID_CTLS; i++) {
  1191. const struct cx88_ctrl *cc = &cx8800_vid_ctls[i];
  1192. struct v4l2_ctrl *vc;
  1193. vc = v4l2_ctrl_new_std(&core->video_hdl, &cx8800_ctrl_vid_ops,
  1194. cc->id, cc->minimum, cc->maximum, cc->step, cc->default_value);
  1195. if (vc == NULL) {
  1196. err = core->video_hdl.error;
  1197. goto fail_core;
  1198. }
  1199. vc->priv = (void *)cc;
  1200. if (vc->id == V4L2_CID_CHROMA_AGC)
  1201. core->chroma_agc = vc;
  1202. }
  1203. v4l2_ctrl_add_handler(&core->video_hdl, &core->audio_hdl, NULL);
  1204. /* load and configure helper modules */
  1205. if (core->board.audio_chip == CX88_AUDIO_WM8775) {
  1206. struct i2c_board_info wm8775_info = {
  1207. .type = "wm8775",
  1208. .addr = 0x36 >> 1,
  1209. .platform_data = &core->wm8775_data,
  1210. };
  1211. struct v4l2_subdev *sd;
  1212. if (core->boardnr == CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1)
  1213. core->wm8775_data.is_nova_s = true;
  1214. else
  1215. core->wm8775_data.is_nova_s = false;
  1216. sd = v4l2_i2c_new_subdev_board(&core->v4l2_dev, &core->i2c_adap,
  1217. &wm8775_info, NULL);
  1218. if (sd != NULL) {
  1219. core->sd_wm8775 = sd;
  1220. sd->grp_id = WM8775_GID;
  1221. }
  1222. }
  1223. if (core->board.audio_chip == CX88_AUDIO_TVAUDIO) {
  1224. /* This probes for a tda9874 as is used on some
  1225. Pixelview Ultra boards. */
  1226. v4l2_i2c_new_subdev(&core->v4l2_dev, &core->i2c_adap,
  1227. "tvaudio", 0, I2C_ADDRS(0xb0 >> 1));
  1228. }
  1229. switch (core->boardnr) {
  1230. case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD:
  1231. case CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD: {
  1232. static const struct i2c_board_info rtc_info = {
  1233. I2C_BOARD_INFO("isl1208", 0x6f)
  1234. };
  1235. request_module("rtc-isl1208");
  1236. core->i2c_rtc = i2c_new_device(&core->i2c_adap, &rtc_info);
  1237. }
  1238. /* break intentionally omitted */
  1239. case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO:
  1240. request_module("ir-kbd-i2c");
  1241. }
  1242. /* Sets device info at pci_dev */
  1243. pci_set_drvdata(pci_dev, dev);
  1244. dev->fmt = format_by_fourcc(V4L2_PIX_FMT_BGR24);
  1245. /* Maintain a reference so cx88-blackbird can query the 8800 device. */
  1246. core->v4ldev = dev;
  1247. /* initial device configuration */
  1248. mutex_lock(&core->lock);
  1249. cx88_set_tvnorm(core, V4L2_STD_NTSC_M);
  1250. v4l2_ctrl_handler_setup(&core->video_hdl);
  1251. v4l2_ctrl_handler_setup(&core->audio_hdl);
  1252. cx88_video_mux(core, 0);
  1253. q = &dev->vb2_vidq;
  1254. q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  1255. q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
  1256. q->gfp_flags = GFP_DMA32;
  1257. q->min_buffers_needed = 2;
  1258. q->drv_priv = dev;
  1259. q->buf_struct_size = sizeof(struct cx88_buffer);
  1260. q->ops = &cx8800_video_qops;
  1261. q->mem_ops = &vb2_dma_sg_memops;
  1262. q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
  1263. q->lock = &core->lock;
  1264. err = vb2_queue_init(q);
  1265. if (err < 0)
  1266. goto fail_unreg;
  1267. q = &dev->vb2_vbiq;
  1268. q->type = V4L2_BUF_TYPE_VBI_CAPTURE;
  1269. q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
  1270. q->gfp_flags = GFP_DMA32;
  1271. q->min_buffers_needed = 2;
  1272. q->drv_priv = dev;
  1273. q->buf_struct_size = sizeof(struct cx88_buffer);
  1274. q->ops = &cx8800_vbi_qops;
  1275. q->mem_ops = &vb2_dma_sg_memops;
  1276. q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
  1277. q->lock = &core->lock;
  1278. err = vb2_queue_init(q);
  1279. if (err < 0)
  1280. goto fail_unreg;
  1281. /* register v4l devices */
  1282. cx88_vdev_init(core, dev->pci, &dev->video_dev,
  1283. &cx8800_video_template, "video");
  1284. video_set_drvdata(&dev->video_dev, dev);
  1285. dev->video_dev.ctrl_handler = &core->video_hdl;
  1286. dev->video_dev.queue = &dev->vb2_vidq;
  1287. err = video_register_device(&dev->video_dev, VFL_TYPE_GRABBER,
  1288. video_nr[core->nr]);
  1289. if (err < 0) {
  1290. printk(KERN_ERR "%s/0: can't register video device\n",
  1291. core->name);
  1292. goto fail_unreg;
  1293. }
  1294. printk(KERN_INFO "%s/0: registered device %s [v4l2]\n",
  1295. core->name, video_device_node_name(&dev->video_dev));
  1296. cx88_vdev_init(core, dev->pci, &dev->vbi_dev,
  1297. &cx8800_vbi_template, "vbi");
  1298. video_set_drvdata(&dev->vbi_dev, dev);
  1299. dev->vbi_dev.queue = &dev->vb2_vbiq;
  1300. err = video_register_device(&dev->vbi_dev, VFL_TYPE_VBI,
  1301. vbi_nr[core->nr]);
  1302. if (err < 0) {
  1303. printk(KERN_ERR "%s/0: can't register vbi device\n",
  1304. core->name);
  1305. goto fail_unreg;
  1306. }
  1307. printk(KERN_INFO "%s/0: registered device %s\n",
  1308. core->name, video_device_node_name(&dev->vbi_dev));
  1309. if (core->board.radio.type == CX88_RADIO) {
  1310. cx88_vdev_init(core, dev->pci, &dev->radio_dev,
  1311. &cx8800_radio_template, "radio");
  1312. video_set_drvdata(&dev->radio_dev, dev);
  1313. dev->radio_dev.ctrl_handler = &core->audio_hdl;
  1314. err = video_register_device(&dev->radio_dev, VFL_TYPE_RADIO,
  1315. radio_nr[core->nr]);
  1316. if (err < 0) {
  1317. printk(KERN_ERR "%s/0: can't register radio device\n",
  1318. core->name);
  1319. goto fail_unreg;
  1320. }
  1321. printk(KERN_INFO "%s/0: registered device %s\n",
  1322. core->name, video_device_node_name(&dev->radio_dev));
  1323. }
  1324. /* start tvaudio thread */
  1325. if (core->board.tuner_type != UNSET) {
  1326. core->kthread = kthread_run(cx88_audio_thread, core, "cx88 tvaudio");
  1327. if (IS_ERR(core->kthread)) {
  1328. err = PTR_ERR(core->kthread);
  1329. printk(KERN_ERR "%s/0: failed to create cx88 audio thread, err=%d\n",
  1330. core->name, err);
  1331. }
  1332. }
  1333. mutex_unlock(&core->lock);
  1334. return 0;
  1335. fail_unreg:
  1336. cx8800_unregister_video(dev);
  1337. free_irq(pci_dev->irq, dev);
  1338. mutex_unlock(&core->lock);
  1339. fail_core:
  1340. vb2_dma_sg_cleanup_ctx(dev->alloc_ctx);
  1341. core->v4ldev = NULL;
  1342. cx88_core_put(core,dev->pci);
  1343. fail_free:
  1344. kfree(dev);
  1345. return err;
  1346. }
  1347. static void cx8800_finidev(struct pci_dev *pci_dev)
  1348. {
  1349. struct cx8800_dev *dev = pci_get_drvdata(pci_dev);
  1350. struct cx88_core *core = dev->core;
  1351. /* stop thread */
  1352. if (core->kthread) {
  1353. kthread_stop(core->kthread);
  1354. core->kthread = NULL;
  1355. }
  1356. if (core->ir)
  1357. cx88_ir_stop(core);
  1358. cx88_shutdown(core); /* FIXME */
  1359. /* unregister stuff */
  1360. free_irq(pci_dev->irq, dev);
  1361. cx8800_unregister_video(dev);
  1362. pci_disable_device(pci_dev);
  1363. core->v4ldev = NULL;
  1364. /* free memory */
  1365. cx88_core_put(core,dev->pci);
  1366. vb2_dma_sg_cleanup_ctx(dev->alloc_ctx);
  1367. kfree(dev);
  1368. }
  1369. #ifdef CONFIG_PM
  1370. static int cx8800_suspend(struct pci_dev *pci_dev, pm_message_t state)
  1371. {
  1372. struct cx8800_dev *dev = pci_get_drvdata(pci_dev);
  1373. struct cx88_core *core = dev->core;
  1374. unsigned long flags;
  1375. /* stop video+vbi capture */
  1376. spin_lock_irqsave(&dev->slock, flags);
  1377. if (!list_empty(&dev->vidq.active)) {
  1378. printk("%s/0: suspend video\n", core->name);
  1379. stop_video_dma(dev);
  1380. }
  1381. if (!list_empty(&dev->vbiq.active)) {
  1382. printk("%s/0: suspend vbi\n", core->name);
  1383. cx8800_stop_vbi_dma(dev);
  1384. }
  1385. spin_unlock_irqrestore(&dev->slock, flags);
  1386. if (core->ir)
  1387. cx88_ir_stop(core);
  1388. /* FIXME -- shutdown device */
  1389. cx88_shutdown(core);
  1390. pci_save_state(pci_dev);
  1391. if (0 != pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state))) {
  1392. pci_disable_device(pci_dev);
  1393. dev->state.disabled = 1;
  1394. }
  1395. return 0;
  1396. }
  1397. static int cx8800_resume(struct pci_dev *pci_dev)
  1398. {
  1399. struct cx8800_dev *dev = pci_get_drvdata(pci_dev);
  1400. struct cx88_core *core = dev->core;
  1401. unsigned long flags;
  1402. int err;
  1403. if (dev->state.disabled) {
  1404. err=pci_enable_device(pci_dev);
  1405. if (err) {
  1406. printk(KERN_ERR "%s/0: can't enable device\n",
  1407. core->name);
  1408. return err;
  1409. }
  1410. dev->state.disabled = 0;
  1411. }
  1412. err= pci_set_power_state(pci_dev, PCI_D0);
  1413. if (err) {
  1414. printk(KERN_ERR "%s/0: can't set power state\n", core->name);
  1415. pci_disable_device(pci_dev);
  1416. dev->state.disabled = 1;
  1417. return err;
  1418. }
  1419. pci_restore_state(pci_dev);
  1420. /* FIXME: re-initialize hardware */
  1421. cx88_reset(core);
  1422. if (core->ir)
  1423. cx88_ir_start(core);
  1424. cx_set(MO_PCI_INTMSK, core->pci_irqmask);
  1425. /* restart video+vbi capture */
  1426. spin_lock_irqsave(&dev->slock, flags);
  1427. if (!list_empty(&dev->vidq.active)) {
  1428. printk("%s/0: resume video\n", core->name);
  1429. restart_video_queue(dev,&dev->vidq);
  1430. }
  1431. if (!list_empty(&dev->vbiq.active)) {
  1432. printk("%s/0: resume vbi\n", core->name);
  1433. cx8800_restart_vbi_queue(dev,&dev->vbiq);
  1434. }
  1435. spin_unlock_irqrestore(&dev->slock, flags);
  1436. return 0;
  1437. }
  1438. #endif
  1439. /* ----------------------------------------------------------- */
  1440. static const struct pci_device_id cx8800_pci_tbl[] = {
  1441. {
  1442. .vendor = 0x14f1,
  1443. .device = 0x8800,
  1444. .subvendor = PCI_ANY_ID,
  1445. .subdevice = PCI_ANY_ID,
  1446. },{
  1447. /* --- end of list --- */
  1448. }
  1449. };
  1450. MODULE_DEVICE_TABLE(pci, cx8800_pci_tbl);
  1451. static struct pci_driver cx8800_pci_driver = {
  1452. .name = "cx8800",
  1453. .id_table = cx8800_pci_tbl,
  1454. .probe = cx8800_initdev,
  1455. .remove = cx8800_finidev,
  1456. #ifdef CONFIG_PM
  1457. .suspend = cx8800_suspend,
  1458. .resume = cx8800_resume,
  1459. #endif
  1460. };
  1461. module_pci_driver(cx8800_pci_driver);