netup_unidvb_i2c.c 10 KB

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  1. /*
  2. * netup_unidvb_i2c.c
  3. *
  4. * Internal I2C bus driver for NetUP Universal Dual DVB-CI
  5. *
  6. * Copyright (C) 2014 NetUP Inc.
  7. * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
  8. * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. */
  20. #include <linux/module.h>
  21. #include <linux/moduleparam.h>
  22. #include <linux/init.h>
  23. #include <linux/delay.h>
  24. #include "netup_unidvb.h"
  25. #define NETUP_I2C_BUS0_ADDR 0x4800
  26. #define NETUP_I2C_BUS1_ADDR 0x4840
  27. #define NETUP_I2C_TIMEOUT 1000
  28. /* twi_ctrl0_stat reg bits */
  29. #define TWI_IRQEN_COMPL 0x1
  30. #define TWI_IRQEN_ANACK 0x2
  31. #define TWI_IRQEN_DNACK 0x4
  32. #define TWI_IRQ_COMPL (TWI_IRQEN_COMPL << 8)
  33. #define TWI_IRQ_ANACK (TWI_IRQEN_ANACK << 8)
  34. #define TWI_IRQ_DNACK (TWI_IRQEN_DNACK << 8)
  35. #define TWI_IRQ_TX 0x800
  36. #define TWI_IRQ_RX 0x1000
  37. #define TWI_IRQEN (TWI_IRQEN_COMPL | TWI_IRQEN_ANACK | TWI_IRQEN_DNACK)
  38. /* twi_addr_ctrl1 reg bits*/
  39. #define TWI_TRANSFER 0x100
  40. #define TWI_NOSTOP 0x200
  41. #define TWI_SOFT_RESET 0x2000
  42. /* twi_clkdiv reg value */
  43. #define TWI_CLKDIV 156
  44. /* fifo_stat_ctrl reg bits */
  45. #define FIFO_IRQEN 0x8000
  46. #define FIFO_RESET 0x4000
  47. /* FIFO size */
  48. #define FIFO_SIZE 16
  49. struct netup_i2c_fifo_regs {
  50. union {
  51. __u8 data8;
  52. __le16 data16;
  53. __le32 data32;
  54. };
  55. __u8 padding[4];
  56. __le16 stat_ctrl;
  57. } __packed __aligned(1);
  58. struct netup_i2c_regs {
  59. __le16 clkdiv;
  60. __le16 twi_ctrl0_stat;
  61. __le16 twi_addr_ctrl1;
  62. __le16 length;
  63. __u8 padding1[8];
  64. struct netup_i2c_fifo_regs tx_fifo;
  65. __u8 padding2[6];
  66. struct netup_i2c_fifo_regs rx_fifo;
  67. } __packed __aligned(1);
  68. irqreturn_t netup_i2c_interrupt(struct netup_i2c *i2c)
  69. {
  70. u16 reg, tmp;
  71. unsigned long flags;
  72. irqreturn_t iret = IRQ_HANDLED;
  73. spin_lock_irqsave(&i2c->lock, flags);
  74. reg = readw(&i2c->regs->twi_ctrl0_stat);
  75. writew(reg & ~TWI_IRQEN, &i2c->regs->twi_ctrl0_stat);
  76. dev_dbg(i2c->adap.dev.parent,
  77. "%s(): twi_ctrl0_state 0x%x\n", __func__, reg);
  78. if ((reg & TWI_IRQEN_COMPL) != 0 && (reg & TWI_IRQ_COMPL)) {
  79. dev_dbg(i2c->adap.dev.parent,
  80. "%s(): TWI_IRQEN_COMPL\n", __func__);
  81. i2c->state = STATE_DONE;
  82. goto irq_ok;
  83. }
  84. if ((reg & TWI_IRQEN_ANACK) != 0 && (reg & TWI_IRQ_ANACK)) {
  85. dev_dbg(i2c->adap.dev.parent,
  86. "%s(): TWI_IRQEN_ANACK\n", __func__);
  87. i2c->state = STATE_ERROR;
  88. goto irq_ok;
  89. }
  90. if ((reg & TWI_IRQEN_DNACK) != 0 && (reg & TWI_IRQ_DNACK)) {
  91. dev_dbg(i2c->adap.dev.parent,
  92. "%s(): TWI_IRQEN_DNACK\n", __func__);
  93. i2c->state = STATE_ERROR;
  94. goto irq_ok;
  95. }
  96. if ((reg & TWI_IRQ_RX) != 0) {
  97. tmp = readw(&i2c->regs->rx_fifo.stat_ctrl);
  98. writew(tmp & ~FIFO_IRQEN, &i2c->regs->rx_fifo.stat_ctrl);
  99. i2c->state = STATE_WANT_READ;
  100. dev_dbg(i2c->adap.dev.parent,
  101. "%s(): want read\n", __func__);
  102. goto irq_ok;
  103. }
  104. if ((reg & TWI_IRQ_TX) != 0) {
  105. tmp = readw(&i2c->regs->tx_fifo.stat_ctrl);
  106. writew(tmp & ~FIFO_IRQEN, &i2c->regs->tx_fifo.stat_ctrl);
  107. i2c->state = STATE_WANT_WRITE;
  108. dev_dbg(i2c->adap.dev.parent,
  109. "%s(): want write\n", __func__);
  110. goto irq_ok;
  111. }
  112. dev_warn(&i2c->adap.dev, "%s(): not mine interrupt\n", __func__);
  113. iret = IRQ_NONE;
  114. irq_ok:
  115. spin_unlock_irqrestore(&i2c->lock, flags);
  116. if (iret == IRQ_HANDLED)
  117. wake_up(&i2c->wq);
  118. return iret;
  119. }
  120. static void netup_i2c_reset(struct netup_i2c *i2c)
  121. {
  122. dev_dbg(i2c->adap.dev.parent, "%s()\n", __func__);
  123. i2c->state = STATE_DONE;
  124. writew(TWI_SOFT_RESET, &i2c->regs->twi_addr_ctrl1);
  125. writew(TWI_CLKDIV, &i2c->regs->clkdiv);
  126. writew(FIFO_RESET, &i2c->regs->tx_fifo.stat_ctrl);
  127. writew(FIFO_RESET, &i2c->regs->rx_fifo.stat_ctrl);
  128. writew(0x800, &i2c->regs->tx_fifo.stat_ctrl);
  129. writew(0x800, &i2c->regs->rx_fifo.stat_ctrl);
  130. }
  131. static void netup_i2c_fifo_tx(struct netup_i2c *i2c)
  132. {
  133. u8 data;
  134. u32 fifo_space = FIFO_SIZE -
  135. (readw(&i2c->regs->tx_fifo.stat_ctrl) & 0x3f);
  136. u32 msg_length = i2c->msg->len - i2c->xmit_size;
  137. msg_length = (msg_length < fifo_space ? msg_length : fifo_space);
  138. while (msg_length--) {
  139. data = i2c->msg->buf[i2c->xmit_size++];
  140. writeb(data, &i2c->regs->tx_fifo.data8);
  141. dev_dbg(i2c->adap.dev.parent,
  142. "%s(): write 0x%02x\n", __func__, data);
  143. }
  144. if (i2c->xmit_size < i2c->msg->len) {
  145. dev_dbg(i2c->adap.dev.parent,
  146. "%s(): TX IRQ enabled\n", __func__);
  147. writew(readw(&i2c->regs->tx_fifo.stat_ctrl) | FIFO_IRQEN,
  148. &i2c->regs->tx_fifo.stat_ctrl);
  149. }
  150. }
  151. static void netup_i2c_fifo_rx(struct netup_i2c *i2c)
  152. {
  153. u8 data;
  154. u32 fifo_size = readw(&i2c->regs->rx_fifo.stat_ctrl) & 0x3f;
  155. dev_dbg(i2c->adap.dev.parent,
  156. "%s(): RX fifo size %d\n", __func__, fifo_size);
  157. while (fifo_size--) {
  158. data = readb(&i2c->regs->rx_fifo.data8);
  159. if ((i2c->msg->flags & I2C_M_RD) != 0 &&
  160. i2c->xmit_size < i2c->msg->len) {
  161. i2c->msg->buf[i2c->xmit_size++] = data;
  162. dev_dbg(i2c->adap.dev.parent,
  163. "%s(): read 0x%02x\n", __func__, data);
  164. }
  165. }
  166. if (i2c->xmit_size < i2c->msg->len) {
  167. dev_dbg(i2c->adap.dev.parent,
  168. "%s(): RX IRQ enabled\n", __func__);
  169. writew(readw(&i2c->regs->rx_fifo.stat_ctrl) | FIFO_IRQEN,
  170. &i2c->regs->rx_fifo.stat_ctrl);
  171. }
  172. }
  173. static void netup_i2c_start_xfer(struct netup_i2c *i2c)
  174. {
  175. u16 rdflag = ((i2c->msg->flags & I2C_M_RD) ? 1 : 0);
  176. u16 reg = readw(&i2c->regs->twi_ctrl0_stat);
  177. writew(TWI_IRQEN | reg, &i2c->regs->twi_ctrl0_stat);
  178. writew(i2c->msg->len, &i2c->regs->length);
  179. writew(TWI_TRANSFER | (i2c->msg->addr << 1) | rdflag,
  180. &i2c->regs->twi_addr_ctrl1);
  181. dev_dbg(i2c->adap.dev.parent,
  182. "%s(): length %d twi_addr_ctrl1 0x%x twi_ctrl0_stat 0x%x\n",
  183. __func__, readw(&i2c->regs->length),
  184. readw(&i2c->regs->twi_addr_ctrl1),
  185. readw(&i2c->regs->twi_ctrl0_stat));
  186. i2c->state = STATE_WAIT;
  187. i2c->xmit_size = 0;
  188. if (!rdflag)
  189. netup_i2c_fifo_tx(i2c);
  190. else
  191. writew(FIFO_IRQEN | readw(&i2c->regs->rx_fifo.stat_ctrl),
  192. &i2c->regs->rx_fifo.stat_ctrl);
  193. }
  194. static int netup_i2c_xfer(struct i2c_adapter *adap,
  195. struct i2c_msg *msgs, int num)
  196. {
  197. unsigned long flags;
  198. int i, trans_done, res = num;
  199. struct netup_i2c *i2c = i2c_get_adapdata(adap);
  200. u16 reg;
  201. if (num <= 0) {
  202. dev_dbg(i2c->adap.dev.parent,
  203. "%s(): num == %d\n", __func__, num);
  204. return -EINVAL;
  205. }
  206. spin_lock_irqsave(&i2c->lock, flags);
  207. if (i2c->state != STATE_DONE) {
  208. dev_dbg(i2c->adap.dev.parent,
  209. "%s(): i2c->state == %d, resetting I2C\n",
  210. __func__, i2c->state);
  211. netup_i2c_reset(i2c);
  212. }
  213. dev_dbg(i2c->adap.dev.parent, "%s() num %d\n", __func__, num);
  214. for (i = 0; i < num; i++) {
  215. i2c->msg = &msgs[i];
  216. netup_i2c_start_xfer(i2c);
  217. trans_done = 0;
  218. while (!trans_done) {
  219. spin_unlock_irqrestore(&i2c->lock, flags);
  220. if (wait_event_timeout(i2c->wq,
  221. i2c->state != STATE_WAIT,
  222. msecs_to_jiffies(NETUP_I2C_TIMEOUT))) {
  223. spin_lock_irqsave(&i2c->lock, flags);
  224. switch (i2c->state) {
  225. case STATE_WANT_READ:
  226. netup_i2c_fifo_rx(i2c);
  227. break;
  228. case STATE_WANT_WRITE:
  229. netup_i2c_fifo_tx(i2c);
  230. break;
  231. case STATE_DONE:
  232. if ((i2c->msg->flags & I2C_M_RD) != 0 &&
  233. i2c->xmit_size != i2c->msg->len)
  234. netup_i2c_fifo_rx(i2c);
  235. dev_dbg(i2c->adap.dev.parent,
  236. "%s(): msg %d OK\n",
  237. __func__, i);
  238. trans_done = 1;
  239. break;
  240. case STATE_ERROR:
  241. res = -EIO;
  242. dev_dbg(i2c->adap.dev.parent,
  243. "%s(): error state\n",
  244. __func__);
  245. goto done;
  246. default:
  247. dev_dbg(i2c->adap.dev.parent,
  248. "%s(): invalid state %d\n",
  249. __func__, i2c->state);
  250. res = -EINVAL;
  251. goto done;
  252. }
  253. if (!trans_done) {
  254. i2c->state = STATE_WAIT;
  255. reg = readw(
  256. &i2c->regs->twi_ctrl0_stat);
  257. writew(TWI_IRQEN | reg,
  258. &i2c->regs->twi_ctrl0_stat);
  259. }
  260. spin_unlock_irqrestore(&i2c->lock, flags);
  261. } else {
  262. spin_lock_irqsave(&i2c->lock, flags);
  263. dev_dbg(i2c->adap.dev.parent,
  264. "%s(): wait timeout\n", __func__);
  265. res = -ETIMEDOUT;
  266. goto done;
  267. }
  268. spin_lock_irqsave(&i2c->lock, flags);
  269. }
  270. }
  271. done:
  272. spin_unlock_irqrestore(&i2c->lock, flags);
  273. dev_dbg(i2c->adap.dev.parent, "%s(): result %d\n", __func__, res);
  274. return res;
  275. }
  276. static u32 netup_i2c_func(struct i2c_adapter *adap)
  277. {
  278. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  279. }
  280. static const struct i2c_algorithm netup_i2c_algorithm = {
  281. .master_xfer = netup_i2c_xfer,
  282. .functionality = netup_i2c_func,
  283. };
  284. static struct i2c_adapter netup_i2c_adapter = {
  285. .owner = THIS_MODULE,
  286. .name = NETUP_UNIDVB_NAME,
  287. .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
  288. .algo = &netup_i2c_algorithm,
  289. };
  290. static int netup_i2c_init(struct netup_unidvb_dev *ndev, int bus_num)
  291. {
  292. int ret;
  293. struct netup_i2c *i2c;
  294. if (bus_num < 0 || bus_num > 1) {
  295. dev_err(&ndev->pci_dev->dev,
  296. "%s(): invalid bus_num %d\n", __func__, bus_num);
  297. return -EINVAL;
  298. }
  299. i2c = &ndev->i2c[bus_num];
  300. spin_lock_init(&i2c->lock);
  301. init_waitqueue_head(&i2c->wq);
  302. i2c->regs = (struct netup_i2c_regs __iomem *)(ndev->bmmio0 +
  303. (bus_num == 0 ? NETUP_I2C_BUS0_ADDR : NETUP_I2C_BUS1_ADDR));
  304. netup_i2c_reset(i2c);
  305. i2c->adap = netup_i2c_adapter;
  306. i2c->adap.dev.parent = &ndev->pci_dev->dev;
  307. i2c_set_adapdata(&i2c->adap, i2c);
  308. ret = i2c_add_adapter(&i2c->adap);
  309. if (ret) {
  310. dev_err(&ndev->pci_dev->dev,
  311. "%s(): failed to add I2C adapter\n", __func__);
  312. return ret;
  313. }
  314. dev_info(&ndev->pci_dev->dev,
  315. "%s(): registered I2C bus %d at 0x%x\n",
  316. __func__,
  317. bus_num, (bus_num == 0 ?
  318. NETUP_I2C_BUS0_ADDR :
  319. NETUP_I2C_BUS1_ADDR));
  320. return 0;
  321. }
  322. static void netup_i2c_remove(struct netup_unidvb_dev *ndev, int bus_num)
  323. {
  324. struct netup_i2c *i2c;
  325. if (bus_num < 0 || bus_num > 1) {
  326. dev_err(&ndev->pci_dev->dev,
  327. "%s(): invalid bus number %d\n", __func__, bus_num);
  328. return;
  329. }
  330. i2c = &ndev->i2c[bus_num];
  331. netup_i2c_reset(i2c);
  332. /* remove adapter */
  333. i2c_del_adapter(&i2c->adap);
  334. dev_info(&ndev->pci_dev->dev,
  335. "netup_i2c_remove: unregistered I2C bus %d\n", bus_num);
  336. }
  337. int netup_i2c_register(struct netup_unidvb_dev *ndev)
  338. {
  339. int ret;
  340. ret = netup_i2c_init(ndev, 0);
  341. if (ret)
  342. return ret;
  343. ret = netup_i2c_init(ndev, 1);
  344. if (ret) {
  345. netup_i2c_remove(ndev, 0);
  346. return ret;
  347. }
  348. return 0;
  349. }
  350. void netup_i2c_unregister(struct netup_unidvb_dev *ndev)
  351. {
  352. netup_i2c_remove(ndev, 0);
  353. netup_i2c_remove(ndev, 1);
  354. }