smipcie-main.c 29 KB

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  1. /*
  2. * SMI PCIe driver for DVBSky cards.
  3. *
  4. * Copyright (C) 2014 Max nibble <nibble.max@gmail.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include "smipcie.h"
  17. #include "m88ds3103.h"
  18. #include "ts2020.h"
  19. #include "m88rs6000t.h"
  20. #include "si2168.h"
  21. #include "si2157.h"
  22. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  23. static int smi_hw_init(struct smi_dev *dev)
  24. {
  25. u32 port_mux, port_ctrl, int_stat;
  26. /* set port mux.*/
  27. port_mux = smi_read(MUX_MODE_CTRL);
  28. port_mux &= ~(rbPaMSMask);
  29. port_mux |= rbPaMSDtvNoGpio;
  30. port_mux &= ~(rbPbMSMask);
  31. port_mux |= rbPbMSDtvNoGpio;
  32. port_mux &= ~(0x0f0000);
  33. port_mux |= 0x50000;
  34. smi_write(MUX_MODE_CTRL, port_mux);
  35. /* set DTV register.*/
  36. /* Port A */
  37. port_ctrl = smi_read(VIDEO_CTRL_STATUS_A);
  38. port_ctrl &= ~0x01;
  39. smi_write(VIDEO_CTRL_STATUS_A, port_ctrl);
  40. port_ctrl = smi_read(MPEG2_CTRL_A);
  41. port_ctrl &= ~0x40;
  42. port_ctrl |= 0x80;
  43. smi_write(MPEG2_CTRL_A, port_ctrl);
  44. /* Port B */
  45. port_ctrl = smi_read(VIDEO_CTRL_STATUS_B);
  46. port_ctrl &= ~0x01;
  47. smi_write(VIDEO_CTRL_STATUS_B, port_ctrl);
  48. port_ctrl = smi_read(MPEG2_CTRL_B);
  49. port_ctrl &= ~0x40;
  50. port_ctrl |= 0x80;
  51. smi_write(MPEG2_CTRL_B, port_ctrl);
  52. /* disable and clear interrupt.*/
  53. smi_write(MSI_INT_ENA_CLR, ALL_INT);
  54. int_stat = smi_read(MSI_INT_STATUS);
  55. smi_write(MSI_INT_STATUS_CLR, int_stat);
  56. /* reset demod.*/
  57. smi_clear(PERIPHERAL_CTRL, 0x0303);
  58. msleep(50);
  59. smi_set(PERIPHERAL_CTRL, 0x0101);
  60. return 0;
  61. }
  62. /* i2c bit bus.*/
  63. static void smi_i2c_cfg(struct smi_dev *dev, u32 sw_ctl)
  64. {
  65. u32 dwCtrl;
  66. dwCtrl = smi_read(sw_ctl);
  67. dwCtrl &= ~0x18; /* disable output.*/
  68. dwCtrl |= 0x21; /* reset and software mode.*/
  69. dwCtrl &= ~0xff00;
  70. dwCtrl |= 0x6400;
  71. smi_write(sw_ctl, dwCtrl);
  72. msleep(20);
  73. dwCtrl = smi_read(sw_ctl);
  74. dwCtrl &= ~0x20;
  75. smi_write(sw_ctl, dwCtrl);
  76. }
  77. static void smi_i2c_setsda(struct smi_dev *dev, int state, u32 sw_ctl)
  78. {
  79. if (state) {
  80. /* set as input.*/
  81. smi_clear(sw_ctl, SW_I2C_MSK_DAT_EN);
  82. } else {
  83. smi_clear(sw_ctl, SW_I2C_MSK_DAT_OUT);
  84. /* set as output.*/
  85. smi_set(sw_ctl, SW_I2C_MSK_DAT_EN);
  86. }
  87. }
  88. static void smi_i2c_setscl(void *data, int state, u32 sw_ctl)
  89. {
  90. struct smi_dev *dev = data;
  91. if (state) {
  92. /* set as input.*/
  93. smi_clear(sw_ctl, SW_I2C_MSK_CLK_EN);
  94. } else {
  95. smi_clear(sw_ctl, SW_I2C_MSK_CLK_OUT);
  96. /* set as output.*/
  97. smi_set(sw_ctl, SW_I2C_MSK_CLK_EN);
  98. }
  99. }
  100. static int smi_i2c_getsda(void *data, u32 sw_ctl)
  101. {
  102. struct smi_dev *dev = data;
  103. /* set as input.*/
  104. smi_clear(sw_ctl, SW_I2C_MSK_DAT_EN);
  105. udelay(1);
  106. return (smi_read(sw_ctl) & SW_I2C_MSK_DAT_IN) ? 1 : 0;
  107. }
  108. static int smi_i2c_getscl(void *data, u32 sw_ctl)
  109. {
  110. struct smi_dev *dev = data;
  111. /* set as input.*/
  112. smi_clear(sw_ctl, SW_I2C_MSK_CLK_EN);
  113. udelay(1);
  114. return (smi_read(sw_ctl) & SW_I2C_MSK_CLK_IN) ? 1 : 0;
  115. }
  116. /* i2c 0.*/
  117. static void smi_i2c0_setsda(void *data, int state)
  118. {
  119. struct smi_dev *dev = data;
  120. smi_i2c_setsda(dev, state, I2C_A_SW_CTL);
  121. }
  122. static void smi_i2c0_setscl(void *data, int state)
  123. {
  124. struct smi_dev *dev = data;
  125. smi_i2c_setscl(dev, state, I2C_A_SW_CTL);
  126. }
  127. static int smi_i2c0_getsda(void *data)
  128. {
  129. struct smi_dev *dev = data;
  130. return smi_i2c_getsda(dev, I2C_A_SW_CTL);
  131. }
  132. static int smi_i2c0_getscl(void *data)
  133. {
  134. struct smi_dev *dev = data;
  135. return smi_i2c_getscl(dev, I2C_A_SW_CTL);
  136. }
  137. /* i2c 1.*/
  138. static void smi_i2c1_setsda(void *data, int state)
  139. {
  140. struct smi_dev *dev = data;
  141. smi_i2c_setsda(dev, state, I2C_B_SW_CTL);
  142. }
  143. static void smi_i2c1_setscl(void *data, int state)
  144. {
  145. struct smi_dev *dev = data;
  146. smi_i2c_setscl(dev, state, I2C_B_SW_CTL);
  147. }
  148. static int smi_i2c1_getsda(void *data)
  149. {
  150. struct smi_dev *dev = data;
  151. return smi_i2c_getsda(dev, I2C_B_SW_CTL);
  152. }
  153. static int smi_i2c1_getscl(void *data)
  154. {
  155. struct smi_dev *dev = data;
  156. return smi_i2c_getscl(dev, I2C_B_SW_CTL);
  157. }
  158. static int smi_i2c_init(struct smi_dev *dev)
  159. {
  160. int ret;
  161. /* i2c bus 0 */
  162. smi_i2c_cfg(dev, I2C_A_SW_CTL);
  163. i2c_set_adapdata(&dev->i2c_bus[0], dev);
  164. strcpy(dev->i2c_bus[0].name, "SMI-I2C0");
  165. dev->i2c_bus[0].owner = THIS_MODULE;
  166. dev->i2c_bus[0].dev.parent = &dev->pci_dev->dev;
  167. dev->i2c_bus[0].algo_data = &dev->i2c_bit[0];
  168. dev->i2c_bit[0].data = dev;
  169. dev->i2c_bit[0].setsda = smi_i2c0_setsda;
  170. dev->i2c_bit[0].setscl = smi_i2c0_setscl;
  171. dev->i2c_bit[0].getsda = smi_i2c0_getsda;
  172. dev->i2c_bit[0].getscl = smi_i2c0_getscl;
  173. dev->i2c_bit[0].udelay = 12;
  174. dev->i2c_bit[0].timeout = 10;
  175. /* Raise SCL and SDA */
  176. smi_i2c0_setsda(dev, 1);
  177. smi_i2c0_setscl(dev, 1);
  178. ret = i2c_bit_add_bus(&dev->i2c_bus[0]);
  179. if (ret < 0)
  180. return ret;
  181. /* i2c bus 1 */
  182. smi_i2c_cfg(dev, I2C_B_SW_CTL);
  183. i2c_set_adapdata(&dev->i2c_bus[1], dev);
  184. strcpy(dev->i2c_bus[1].name, "SMI-I2C1");
  185. dev->i2c_bus[1].owner = THIS_MODULE;
  186. dev->i2c_bus[1].dev.parent = &dev->pci_dev->dev;
  187. dev->i2c_bus[1].algo_data = &dev->i2c_bit[1];
  188. dev->i2c_bit[1].data = dev;
  189. dev->i2c_bit[1].setsda = smi_i2c1_setsda;
  190. dev->i2c_bit[1].setscl = smi_i2c1_setscl;
  191. dev->i2c_bit[1].getsda = smi_i2c1_getsda;
  192. dev->i2c_bit[1].getscl = smi_i2c1_getscl;
  193. dev->i2c_bit[1].udelay = 12;
  194. dev->i2c_bit[1].timeout = 10;
  195. /* Raise SCL and SDA */
  196. smi_i2c1_setsda(dev, 1);
  197. smi_i2c1_setscl(dev, 1);
  198. ret = i2c_bit_add_bus(&dev->i2c_bus[1]);
  199. if (ret < 0)
  200. i2c_del_adapter(&dev->i2c_bus[0]);
  201. return ret;
  202. }
  203. static void smi_i2c_exit(struct smi_dev *dev)
  204. {
  205. i2c_del_adapter(&dev->i2c_bus[0]);
  206. i2c_del_adapter(&dev->i2c_bus[1]);
  207. }
  208. static int smi_read_eeprom(struct i2c_adapter *i2c, u16 reg, u8 *data, u16 size)
  209. {
  210. int ret;
  211. u8 b0[2] = { (reg >> 8) & 0xff, reg & 0xff };
  212. struct i2c_msg msg[] = {
  213. { .addr = 0x50, .flags = 0,
  214. .buf = b0, .len = 2 },
  215. { .addr = 0x50, .flags = I2C_M_RD,
  216. .buf = data, .len = size }
  217. };
  218. ret = i2c_transfer(i2c, msg, 2);
  219. if (ret != 2) {
  220. dev_err(&i2c->dev, "%s: reg=0x%x (error=%d)\n",
  221. __func__, reg, ret);
  222. return ret;
  223. }
  224. return ret;
  225. }
  226. /* ts port interrupt operations */
  227. static void smi_port_disableInterrupt(struct smi_port *port)
  228. {
  229. struct smi_dev *dev = port->dev;
  230. smi_write(MSI_INT_ENA_CLR,
  231. (port->_dmaInterruptCH0 | port->_dmaInterruptCH1));
  232. }
  233. static void smi_port_enableInterrupt(struct smi_port *port)
  234. {
  235. struct smi_dev *dev = port->dev;
  236. smi_write(MSI_INT_ENA_SET,
  237. (port->_dmaInterruptCH0 | port->_dmaInterruptCH1));
  238. }
  239. static void smi_port_clearInterrupt(struct smi_port *port)
  240. {
  241. struct smi_dev *dev = port->dev;
  242. smi_write(MSI_INT_STATUS_CLR,
  243. (port->_dmaInterruptCH0 | port->_dmaInterruptCH1));
  244. }
  245. /* tasklet handler: DMA data to dmx.*/
  246. static void smi_dma_xfer(unsigned long data)
  247. {
  248. struct smi_port *port = (struct smi_port *) data;
  249. struct smi_dev *dev = port->dev;
  250. u32 intr_status, finishedData, dmaManagement;
  251. u8 dmaChan0State, dmaChan1State;
  252. intr_status = port->_int_status;
  253. dmaManagement = smi_read(port->DMA_MANAGEMENT);
  254. dmaChan0State = (u8)((dmaManagement & 0x00000030) >> 4);
  255. dmaChan1State = (u8)((dmaManagement & 0x00300000) >> 20);
  256. /* CH-0 DMA interrupt.*/
  257. if ((intr_status & port->_dmaInterruptCH0) && (dmaChan0State == 0x01)) {
  258. dev_dbg(&dev->pci_dev->dev,
  259. "Port[%d]-DMA CH0 engine complete successful !\n",
  260. port->idx);
  261. finishedData = smi_read(port->DMA_CHAN0_TRANS_STATE);
  262. finishedData &= 0x003FFFFF;
  263. /* value of DMA_PORT0_CHAN0_TRANS_STATE register [21:0]
  264. * indicate dma total transfer length and
  265. * zero of [21:0] indicate dma total transfer length
  266. * equal to 0x400000 (4MB)*/
  267. if (finishedData == 0)
  268. finishedData = 0x00400000;
  269. if (finishedData != SMI_TS_DMA_BUF_SIZE) {
  270. dev_dbg(&dev->pci_dev->dev,
  271. "DMA CH0 engine complete length mismatched, finish data=%d !\n",
  272. finishedData);
  273. }
  274. dvb_dmx_swfilter_packets(&port->demux,
  275. port->cpu_addr[0], (finishedData / 188));
  276. /*dvb_dmx_swfilter(&port->demux,
  277. port->cpu_addr[0], finishedData);*/
  278. }
  279. /* CH-1 DMA interrupt.*/
  280. if ((intr_status & port->_dmaInterruptCH1) && (dmaChan1State == 0x01)) {
  281. dev_dbg(&dev->pci_dev->dev,
  282. "Port[%d]-DMA CH1 engine complete successful !\n",
  283. port->idx);
  284. finishedData = smi_read(port->DMA_CHAN1_TRANS_STATE);
  285. finishedData &= 0x003FFFFF;
  286. /* value of DMA_PORT0_CHAN0_TRANS_STATE register [21:0]
  287. * indicate dma total transfer length and
  288. * zero of [21:0] indicate dma total transfer length
  289. * equal to 0x400000 (4MB)*/
  290. if (finishedData == 0)
  291. finishedData = 0x00400000;
  292. if (finishedData != SMI_TS_DMA_BUF_SIZE) {
  293. dev_dbg(&dev->pci_dev->dev,
  294. "DMA CH1 engine complete length mismatched, finish data=%d !\n",
  295. finishedData);
  296. }
  297. dvb_dmx_swfilter_packets(&port->demux,
  298. port->cpu_addr[1], (finishedData / 188));
  299. /*dvb_dmx_swfilter(&port->demux,
  300. port->cpu_addr[1], finishedData);*/
  301. }
  302. /* restart DMA.*/
  303. if (intr_status & port->_dmaInterruptCH0)
  304. dmaManagement |= 0x00000002;
  305. if (intr_status & port->_dmaInterruptCH1)
  306. dmaManagement |= 0x00020000;
  307. smi_write(port->DMA_MANAGEMENT, dmaManagement);
  308. /* Re-enable interrupts */
  309. smi_port_enableInterrupt(port);
  310. }
  311. static void smi_port_dma_free(struct smi_port *port)
  312. {
  313. if (port->cpu_addr[0]) {
  314. pci_free_consistent(port->dev->pci_dev, SMI_TS_DMA_BUF_SIZE,
  315. port->cpu_addr[0], port->dma_addr[0]);
  316. port->cpu_addr[0] = NULL;
  317. }
  318. if (port->cpu_addr[1]) {
  319. pci_free_consistent(port->dev->pci_dev, SMI_TS_DMA_BUF_SIZE,
  320. port->cpu_addr[1], port->dma_addr[1]);
  321. port->cpu_addr[1] = NULL;
  322. }
  323. }
  324. static int smi_port_init(struct smi_port *port, int dmaChanUsed)
  325. {
  326. dev_dbg(&port->dev->pci_dev->dev,
  327. "%s, port %d, dmaused %d\n", __func__, port->idx, dmaChanUsed);
  328. port->enable = 0;
  329. if (port->idx == 0) {
  330. /* Port A */
  331. port->_dmaInterruptCH0 = dmaChanUsed & 0x01;
  332. port->_dmaInterruptCH1 = dmaChanUsed & 0x02;
  333. port->DMA_CHAN0_ADDR_LOW = DMA_PORTA_CHAN0_ADDR_LOW;
  334. port->DMA_CHAN0_ADDR_HI = DMA_PORTA_CHAN0_ADDR_HI;
  335. port->DMA_CHAN0_TRANS_STATE = DMA_PORTA_CHAN0_TRANS_STATE;
  336. port->DMA_CHAN0_CONTROL = DMA_PORTA_CHAN0_CONTROL;
  337. port->DMA_CHAN1_ADDR_LOW = DMA_PORTA_CHAN1_ADDR_LOW;
  338. port->DMA_CHAN1_ADDR_HI = DMA_PORTA_CHAN1_ADDR_HI;
  339. port->DMA_CHAN1_TRANS_STATE = DMA_PORTA_CHAN1_TRANS_STATE;
  340. port->DMA_CHAN1_CONTROL = DMA_PORTA_CHAN1_CONTROL;
  341. port->DMA_MANAGEMENT = DMA_PORTA_MANAGEMENT;
  342. } else {
  343. /* Port B */
  344. port->_dmaInterruptCH0 = (dmaChanUsed << 2) & 0x04;
  345. port->_dmaInterruptCH1 = (dmaChanUsed << 2) & 0x08;
  346. port->DMA_CHAN0_ADDR_LOW = DMA_PORTB_CHAN0_ADDR_LOW;
  347. port->DMA_CHAN0_ADDR_HI = DMA_PORTB_CHAN0_ADDR_HI;
  348. port->DMA_CHAN0_TRANS_STATE = DMA_PORTB_CHAN0_TRANS_STATE;
  349. port->DMA_CHAN0_CONTROL = DMA_PORTB_CHAN0_CONTROL;
  350. port->DMA_CHAN1_ADDR_LOW = DMA_PORTB_CHAN1_ADDR_LOW;
  351. port->DMA_CHAN1_ADDR_HI = DMA_PORTB_CHAN1_ADDR_HI;
  352. port->DMA_CHAN1_TRANS_STATE = DMA_PORTB_CHAN1_TRANS_STATE;
  353. port->DMA_CHAN1_CONTROL = DMA_PORTB_CHAN1_CONTROL;
  354. port->DMA_MANAGEMENT = DMA_PORTB_MANAGEMENT;
  355. }
  356. if (port->_dmaInterruptCH0) {
  357. port->cpu_addr[0] = pci_alloc_consistent(port->dev->pci_dev,
  358. SMI_TS_DMA_BUF_SIZE,
  359. &port->dma_addr[0]);
  360. if (!port->cpu_addr[0]) {
  361. dev_err(&port->dev->pci_dev->dev,
  362. "Port[%d] DMA CH0 memory allocation failed!\n",
  363. port->idx);
  364. goto err;
  365. }
  366. }
  367. if (port->_dmaInterruptCH1) {
  368. port->cpu_addr[1] = pci_alloc_consistent(port->dev->pci_dev,
  369. SMI_TS_DMA_BUF_SIZE,
  370. &port->dma_addr[1]);
  371. if (!port->cpu_addr[1]) {
  372. dev_err(&port->dev->pci_dev->dev,
  373. "Port[%d] DMA CH1 memory allocation failed!\n",
  374. port->idx);
  375. goto err;
  376. }
  377. }
  378. smi_port_disableInterrupt(port);
  379. tasklet_init(&port->tasklet, smi_dma_xfer, (unsigned long)port);
  380. tasklet_disable(&port->tasklet);
  381. port->enable = 1;
  382. return 0;
  383. err:
  384. smi_port_dma_free(port);
  385. return -ENOMEM;
  386. }
  387. static void smi_port_exit(struct smi_port *port)
  388. {
  389. smi_port_disableInterrupt(port);
  390. tasklet_kill(&port->tasklet);
  391. smi_port_dma_free(port);
  392. port->enable = 0;
  393. }
  394. static int smi_port_irq(struct smi_port *port, u32 int_status)
  395. {
  396. u32 port_req_irq = port->_dmaInterruptCH0 | port->_dmaInterruptCH1;
  397. int handled = 0;
  398. if (int_status & port_req_irq) {
  399. smi_port_disableInterrupt(port);
  400. port->_int_status = int_status;
  401. smi_port_clearInterrupt(port);
  402. tasklet_schedule(&port->tasklet);
  403. handled = 1;
  404. }
  405. return handled;
  406. }
  407. static irqreturn_t smi_irq_handler(int irq, void *dev_id)
  408. {
  409. struct smi_dev *dev = dev_id;
  410. struct smi_port *port0 = &dev->ts_port[0];
  411. struct smi_port *port1 = &dev->ts_port[1];
  412. struct smi_rc *ir = &dev->ir;
  413. int handled = 0;
  414. u32 intr_status = smi_read(MSI_INT_STATUS);
  415. /* ts0 interrupt.*/
  416. if (dev->info->ts_0)
  417. handled += smi_port_irq(port0, intr_status);
  418. /* ts1 interrupt.*/
  419. if (dev->info->ts_1)
  420. handled += smi_port_irq(port1, intr_status);
  421. /* ir interrupt.*/
  422. handled += smi_ir_irq(ir, intr_status);
  423. return IRQ_RETVAL(handled);
  424. }
  425. static struct i2c_client *smi_add_i2c_client(struct i2c_adapter *adapter,
  426. struct i2c_board_info *info)
  427. {
  428. struct i2c_client *client;
  429. request_module(info->type);
  430. client = i2c_new_device(adapter, info);
  431. if (client == NULL || client->dev.driver == NULL)
  432. goto err_add_i2c_client;
  433. if (!try_module_get(client->dev.driver->owner)) {
  434. i2c_unregister_device(client);
  435. goto err_add_i2c_client;
  436. }
  437. return client;
  438. err_add_i2c_client:
  439. client = NULL;
  440. return client;
  441. }
  442. static void smi_del_i2c_client(struct i2c_client *client)
  443. {
  444. module_put(client->dev.driver->owner);
  445. i2c_unregister_device(client);
  446. }
  447. static const struct m88ds3103_config smi_dvbsky_m88ds3103_cfg = {
  448. .i2c_addr = 0x68,
  449. .clock = 27000000,
  450. .i2c_wr_max = 33,
  451. .clock_out = 0,
  452. .ts_mode = M88DS3103_TS_PARALLEL,
  453. .ts_clk = 16000,
  454. .ts_clk_pol = 1,
  455. .agc = 0x99,
  456. .lnb_hv_pol = 0,
  457. .lnb_en_pol = 1,
  458. };
  459. static int smi_dvbsky_m88ds3103_fe_attach(struct smi_port *port)
  460. {
  461. int ret = 0;
  462. struct smi_dev *dev = port->dev;
  463. struct i2c_adapter *i2c;
  464. /* tuner I2C module */
  465. struct i2c_adapter *tuner_i2c_adapter;
  466. struct i2c_client *tuner_client;
  467. struct i2c_board_info tuner_info;
  468. struct ts2020_config ts2020_config = {};
  469. memset(&tuner_info, 0, sizeof(struct i2c_board_info));
  470. i2c = (port->idx == 0) ? &dev->i2c_bus[0] : &dev->i2c_bus[1];
  471. /* attach demod */
  472. port->fe = dvb_attach(m88ds3103_attach,
  473. &smi_dvbsky_m88ds3103_cfg, i2c, &tuner_i2c_adapter);
  474. if (!port->fe) {
  475. ret = -ENODEV;
  476. return ret;
  477. }
  478. /* attach tuner */
  479. ts2020_config.fe = port->fe;
  480. strlcpy(tuner_info.type, "ts2020", I2C_NAME_SIZE);
  481. tuner_info.addr = 0x60;
  482. tuner_info.platform_data = &ts2020_config;
  483. tuner_client = smi_add_i2c_client(tuner_i2c_adapter, &tuner_info);
  484. if (!tuner_client) {
  485. ret = -ENODEV;
  486. goto err_tuner_i2c_device;
  487. }
  488. /* delegate signal strength measurement to tuner */
  489. port->fe->ops.read_signal_strength =
  490. port->fe->ops.tuner_ops.get_rf_strength;
  491. port->i2c_client_tuner = tuner_client;
  492. return ret;
  493. err_tuner_i2c_device:
  494. dvb_frontend_detach(port->fe);
  495. return ret;
  496. }
  497. static const struct m88ds3103_config smi_dvbsky_m88rs6000_cfg = {
  498. .i2c_addr = 0x69,
  499. .clock = 27000000,
  500. .i2c_wr_max = 33,
  501. .ts_mode = M88DS3103_TS_PARALLEL,
  502. .ts_clk = 16000,
  503. .ts_clk_pol = 1,
  504. .agc = 0x99,
  505. .lnb_hv_pol = 0,
  506. .lnb_en_pol = 1,
  507. };
  508. static int smi_dvbsky_m88rs6000_fe_attach(struct smi_port *port)
  509. {
  510. int ret = 0;
  511. struct smi_dev *dev = port->dev;
  512. struct i2c_adapter *i2c;
  513. /* tuner I2C module */
  514. struct i2c_adapter *tuner_i2c_adapter;
  515. struct i2c_client *tuner_client;
  516. struct i2c_board_info tuner_info;
  517. struct m88rs6000t_config m88rs6000t_config;
  518. memset(&tuner_info, 0, sizeof(struct i2c_board_info));
  519. i2c = (port->idx == 0) ? &dev->i2c_bus[0] : &dev->i2c_bus[1];
  520. /* attach demod */
  521. port->fe = dvb_attach(m88ds3103_attach,
  522. &smi_dvbsky_m88rs6000_cfg, i2c, &tuner_i2c_adapter);
  523. if (!port->fe) {
  524. ret = -ENODEV;
  525. return ret;
  526. }
  527. /* attach tuner */
  528. m88rs6000t_config.fe = port->fe;
  529. strlcpy(tuner_info.type, "m88rs6000t", I2C_NAME_SIZE);
  530. tuner_info.addr = 0x21;
  531. tuner_info.platform_data = &m88rs6000t_config;
  532. tuner_client = smi_add_i2c_client(tuner_i2c_adapter, &tuner_info);
  533. if (!tuner_client) {
  534. ret = -ENODEV;
  535. goto err_tuner_i2c_device;
  536. }
  537. /* delegate signal strength measurement to tuner */
  538. port->fe->ops.read_signal_strength =
  539. port->fe->ops.tuner_ops.get_rf_strength;
  540. port->i2c_client_tuner = tuner_client;
  541. return ret;
  542. err_tuner_i2c_device:
  543. dvb_frontend_detach(port->fe);
  544. return ret;
  545. }
  546. static int smi_dvbsky_sit2_fe_attach(struct smi_port *port)
  547. {
  548. int ret = 0;
  549. struct smi_dev *dev = port->dev;
  550. struct i2c_adapter *i2c;
  551. struct i2c_adapter *tuner_i2c_adapter;
  552. struct i2c_client *client_tuner, *client_demod;
  553. struct i2c_board_info client_info;
  554. struct si2168_config si2168_config;
  555. struct si2157_config si2157_config;
  556. /* select i2c bus */
  557. i2c = (port->idx == 0) ? &dev->i2c_bus[0] : &dev->i2c_bus[1];
  558. /* attach demod */
  559. memset(&si2168_config, 0, sizeof(si2168_config));
  560. si2168_config.i2c_adapter = &tuner_i2c_adapter;
  561. si2168_config.fe = &port->fe;
  562. si2168_config.ts_mode = SI2168_TS_PARALLEL;
  563. memset(&client_info, 0, sizeof(struct i2c_board_info));
  564. strlcpy(client_info.type, "si2168", I2C_NAME_SIZE);
  565. client_info.addr = 0x64;
  566. client_info.platform_data = &si2168_config;
  567. client_demod = smi_add_i2c_client(i2c, &client_info);
  568. if (!client_demod) {
  569. ret = -ENODEV;
  570. return ret;
  571. }
  572. port->i2c_client_demod = client_demod;
  573. /* attach tuner */
  574. memset(&si2157_config, 0, sizeof(si2157_config));
  575. si2157_config.fe = port->fe;
  576. si2157_config.if_port = 1;
  577. memset(&client_info, 0, sizeof(struct i2c_board_info));
  578. strlcpy(client_info.type, "si2157", I2C_NAME_SIZE);
  579. client_info.addr = 0x60;
  580. client_info.platform_data = &si2157_config;
  581. client_tuner = smi_add_i2c_client(tuner_i2c_adapter, &client_info);
  582. if (!client_tuner) {
  583. smi_del_i2c_client(port->i2c_client_demod);
  584. port->i2c_client_demod = NULL;
  585. ret = -ENODEV;
  586. return ret;
  587. }
  588. port->i2c_client_tuner = client_tuner;
  589. return ret;
  590. }
  591. static int smi_fe_init(struct smi_port *port)
  592. {
  593. int ret = 0;
  594. struct smi_dev *dev = port->dev;
  595. struct dvb_adapter *adap = &port->dvb_adapter;
  596. u8 mac_ee[16];
  597. dev_dbg(&port->dev->pci_dev->dev,
  598. "%s: port %d, fe_type = %d\n",
  599. __func__, port->idx, port->fe_type);
  600. switch (port->fe_type) {
  601. case DVBSKY_FE_M88DS3103:
  602. ret = smi_dvbsky_m88ds3103_fe_attach(port);
  603. break;
  604. case DVBSKY_FE_M88RS6000:
  605. ret = smi_dvbsky_m88rs6000_fe_attach(port);
  606. break;
  607. case DVBSKY_FE_SIT2:
  608. ret = smi_dvbsky_sit2_fe_attach(port);
  609. break;
  610. }
  611. if (ret < 0)
  612. return ret;
  613. /* register dvb frontend */
  614. ret = dvb_register_frontend(adap, port->fe);
  615. if (ret < 0) {
  616. if (port->i2c_client_tuner)
  617. smi_del_i2c_client(port->i2c_client_tuner);
  618. if (port->i2c_client_demod)
  619. smi_del_i2c_client(port->i2c_client_demod);
  620. dvb_frontend_detach(port->fe);
  621. return ret;
  622. }
  623. /* init MAC.*/
  624. ret = smi_read_eeprom(&dev->i2c_bus[0], 0xc0, mac_ee, 16);
  625. dev_info(&port->dev->pci_dev->dev,
  626. "DVBSky SMI PCIe MAC= %pM\n", mac_ee + (port->idx)*8);
  627. memcpy(adap->proposed_mac, mac_ee + (port->idx)*8, 6);
  628. return ret;
  629. }
  630. static void smi_fe_exit(struct smi_port *port)
  631. {
  632. dvb_unregister_frontend(port->fe);
  633. /* remove I2C demod and tuner */
  634. if (port->i2c_client_tuner)
  635. smi_del_i2c_client(port->i2c_client_tuner);
  636. if (port->i2c_client_demod)
  637. smi_del_i2c_client(port->i2c_client_demod);
  638. dvb_frontend_detach(port->fe);
  639. }
  640. static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
  641. int (*start_feed)(struct dvb_demux_feed *),
  642. int (*stop_feed)(struct dvb_demux_feed *),
  643. void *priv)
  644. {
  645. dvbdemux->priv = priv;
  646. dvbdemux->filternum = 256;
  647. dvbdemux->feednum = 256;
  648. dvbdemux->start_feed = start_feed;
  649. dvbdemux->stop_feed = stop_feed;
  650. dvbdemux->write_to_decoder = NULL;
  651. dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
  652. DMX_SECTION_FILTERING |
  653. DMX_MEMORY_BASED_FILTERING);
  654. return dvb_dmx_init(dvbdemux);
  655. }
  656. static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
  657. struct dvb_demux *dvbdemux,
  658. struct dmx_frontend *hw_frontend,
  659. struct dmx_frontend *mem_frontend,
  660. struct dvb_adapter *dvb_adapter)
  661. {
  662. int ret;
  663. dmxdev->filternum = 256;
  664. dmxdev->demux = &dvbdemux->dmx;
  665. dmxdev->capabilities = 0;
  666. ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
  667. if (ret < 0)
  668. return ret;
  669. hw_frontend->source = DMX_FRONTEND_0;
  670. dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
  671. mem_frontend->source = DMX_MEMORY_FE;
  672. dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
  673. return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
  674. }
  675. static u32 smi_config_DMA(struct smi_port *port)
  676. {
  677. struct smi_dev *dev = port->dev;
  678. u32 totalLength = 0, dmaMemPtrLow, dmaMemPtrHi, dmaCtlReg;
  679. u8 chanLatencyTimer = 0, dmaChanEnable = 1, dmaTransStart = 1;
  680. u32 dmaManagement = 0, tlpTransUnit = DMA_TRANS_UNIT_188;
  681. u8 tlpTc = 0, tlpTd = 1, tlpEp = 0, tlpAttr = 0;
  682. u64 mem;
  683. dmaManagement = smi_read(port->DMA_MANAGEMENT);
  684. /* Setup Channel-0 */
  685. if (port->_dmaInterruptCH0) {
  686. totalLength = SMI_TS_DMA_BUF_SIZE;
  687. mem = port->dma_addr[0];
  688. dmaMemPtrLow = mem & 0xffffffff;
  689. dmaMemPtrHi = mem >> 32;
  690. dmaCtlReg = (totalLength) | (tlpTransUnit << 22) | (tlpTc << 25)
  691. | (tlpTd << 28) | (tlpEp << 29) | (tlpAttr << 30);
  692. dmaManagement |= dmaChanEnable | (dmaTransStart << 1)
  693. | (chanLatencyTimer << 8);
  694. /* write DMA register, start DMA engine */
  695. smi_write(port->DMA_CHAN0_ADDR_LOW, dmaMemPtrLow);
  696. smi_write(port->DMA_CHAN0_ADDR_HI, dmaMemPtrHi);
  697. smi_write(port->DMA_CHAN0_CONTROL, dmaCtlReg);
  698. }
  699. /* Setup Channel-1 */
  700. if (port->_dmaInterruptCH1) {
  701. totalLength = SMI_TS_DMA_BUF_SIZE;
  702. mem = port->dma_addr[1];
  703. dmaMemPtrLow = mem & 0xffffffff;
  704. dmaMemPtrHi = mem >> 32;
  705. dmaCtlReg = (totalLength) | (tlpTransUnit << 22) | (tlpTc << 25)
  706. | (tlpTd << 28) | (tlpEp << 29) | (tlpAttr << 30);
  707. dmaManagement |= (dmaChanEnable << 16) | (dmaTransStart << 17)
  708. | (chanLatencyTimer << 24);
  709. /* write DMA register, start DMA engine */
  710. smi_write(port->DMA_CHAN1_ADDR_LOW, dmaMemPtrLow);
  711. smi_write(port->DMA_CHAN1_ADDR_HI, dmaMemPtrHi);
  712. smi_write(port->DMA_CHAN1_CONTROL, dmaCtlReg);
  713. }
  714. return dmaManagement;
  715. }
  716. static int smi_start_feed(struct dvb_demux_feed *dvbdmxfeed)
  717. {
  718. struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
  719. struct smi_port *port = dvbdmx->priv;
  720. struct smi_dev *dev = port->dev;
  721. u32 dmaManagement;
  722. if (port->users++ == 0) {
  723. dmaManagement = smi_config_DMA(port);
  724. smi_port_clearInterrupt(port);
  725. smi_port_enableInterrupt(port);
  726. smi_write(port->DMA_MANAGEMENT, dmaManagement);
  727. tasklet_enable(&port->tasklet);
  728. }
  729. return port->users;
  730. }
  731. static int smi_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
  732. {
  733. struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
  734. struct smi_port *port = dvbdmx->priv;
  735. struct smi_dev *dev = port->dev;
  736. if (--port->users)
  737. return port->users;
  738. tasklet_disable(&port->tasklet);
  739. smi_port_disableInterrupt(port);
  740. smi_clear(port->DMA_MANAGEMENT, 0x30003);
  741. return 0;
  742. }
  743. static int smi_dvb_init(struct smi_port *port)
  744. {
  745. int ret;
  746. struct dvb_adapter *adap = &port->dvb_adapter;
  747. struct dvb_demux *dvbdemux = &port->demux;
  748. dev_dbg(&port->dev->pci_dev->dev,
  749. "%s, port %d\n", __func__, port->idx);
  750. ret = dvb_register_adapter(adap, "SMI_DVB", THIS_MODULE,
  751. &port->dev->pci_dev->dev,
  752. adapter_nr);
  753. if (ret < 0) {
  754. dev_err(&port->dev->pci_dev->dev, "Fail to register DVB adapter.\n");
  755. return ret;
  756. }
  757. ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
  758. smi_start_feed,
  759. smi_stop_feed, port);
  760. if (ret < 0)
  761. goto err_del_dvb_register_adapter;
  762. ret = my_dvb_dmxdev_ts_card_init(&port->dmxdev, &port->demux,
  763. &port->hw_frontend,
  764. &port->mem_frontend, adap);
  765. if (ret < 0)
  766. goto err_del_dvb_dmx;
  767. ret = dvb_net_init(adap, &port->dvbnet, port->dmxdev.demux);
  768. if (ret < 0)
  769. goto err_del_dvb_dmxdev;
  770. return 0;
  771. err_del_dvb_dmxdev:
  772. dvbdemux->dmx.close(&dvbdemux->dmx);
  773. dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->hw_frontend);
  774. dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->mem_frontend);
  775. dvb_dmxdev_release(&port->dmxdev);
  776. err_del_dvb_dmx:
  777. dvb_dmx_release(&port->demux);
  778. err_del_dvb_register_adapter:
  779. dvb_unregister_adapter(&port->dvb_adapter);
  780. return ret;
  781. }
  782. static void smi_dvb_exit(struct smi_port *port)
  783. {
  784. struct dvb_demux *dvbdemux = &port->demux;
  785. dvb_net_release(&port->dvbnet);
  786. dvbdemux->dmx.close(&dvbdemux->dmx);
  787. dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->hw_frontend);
  788. dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->mem_frontend);
  789. dvb_dmxdev_release(&port->dmxdev);
  790. dvb_dmx_release(&port->demux);
  791. dvb_unregister_adapter(&port->dvb_adapter);
  792. }
  793. static int smi_port_attach(struct smi_dev *dev,
  794. struct smi_port *port, int index)
  795. {
  796. int ret, dmachs;
  797. port->dev = dev;
  798. port->idx = index;
  799. port->fe_type = (index == 0) ? dev->info->fe_0 : dev->info->fe_1;
  800. dmachs = (index == 0) ? dev->info->ts_0 : dev->info->ts_1;
  801. /* port init.*/
  802. ret = smi_port_init(port, dmachs);
  803. if (ret < 0)
  804. return ret;
  805. /* dvb init.*/
  806. ret = smi_dvb_init(port);
  807. if (ret < 0)
  808. goto err_del_port_init;
  809. /* fe init.*/
  810. ret = smi_fe_init(port);
  811. if (ret < 0)
  812. goto err_del_dvb_init;
  813. return 0;
  814. err_del_dvb_init:
  815. smi_dvb_exit(port);
  816. err_del_port_init:
  817. smi_port_exit(port);
  818. return ret;
  819. }
  820. static void smi_port_detach(struct smi_port *port)
  821. {
  822. smi_fe_exit(port);
  823. smi_dvb_exit(port);
  824. smi_port_exit(port);
  825. }
  826. static int smi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  827. {
  828. struct smi_dev *dev;
  829. int ret = -ENOMEM;
  830. if (pci_enable_device(pdev) < 0)
  831. return -ENODEV;
  832. dev = kzalloc(sizeof(struct smi_dev), GFP_KERNEL);
  833. if (!dev) {
  834. ret = -ENOMEM;
  835. goto err_pci_disable_device;
  836. }
  837. dev->pci_dev = pdev;
  838. pci_set_drvdata(pdev, dev);
  839. dev->info = (struct smi_cfg_info *) id->driver_data;
  840. dev_info(&dev->pci_dev->dev,
  841. "card detected: %s\n", dev->info->name);
  842. dev->nr = dev->info->type;
  843. dev->lmmio = ioremap(pci_resource_start(dev->pci_dev, 0),
  844. pci_resource_len(dev->pci_dev, 0));
  845. if (!dev->lmmio) {
  846. ret = -ENOMEM;
  847. goto err_kfree;
  848. }
  849. /* should we set to 32bit DMA? */
  850. ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  851. if (ret < 0)
  852. goto err_pci_iounmap;
  853. pci_set_master(pdev);
  854. ret = smi_hw_init(dev);
  855. if (ret < 0)
  856. goto err_pci_iounmap;
  857. ret = smi_i2c_init(dev);
  858. if (ret < 0)
  859. goto err_pci_iounmap;
  860. if (dev->info->ts_0) {
  861. ret = smi_port_attach(dev, &dev->ts_port[0], 0);
  862. if (ret < 0)
  863. goto err_del_i2c_adaptor;
  864. }
  865. if (dev->info->ts_1) {
  866. ret = smi_port_attach(dev, &dev->ts_port[1], 1);
  867. if (ret < 0)
  868. goto err_del_port0_attach;
  869. }
  870. ret = smi_ir_init(dev);
  871. if (ret < 0)
  872. goto err_del_port1_attach;
  873. #ifdef CONFIG_PCI_MSI /* to do msi interrupt.???*/
  874. if (pci_msi_enabled())
  875. ret = pci_enable_msi(dev->pci_dev);
  876. if (ret)
  877. dev_info(&dev->pci_dev->dev, "MSI not available.\n");
  878. #endif
  879. ret = request_irq(dev->pci_dev->irq, smi_irq_handler,
  880. IRQF_SHARED, "SMI_PCIE", dev);
  881. if (ret < 0)
  882. goto err_del_ir;
  883. smi_ir_start(&dev->ir);
  884. return 0;
  885. err_del_ir:
  886. smi_ir_exit(dev);
  887. err_del_port1_attach:
  888. if (dev->info->ts_1)
  889. smi_port_detach(&dev->ts_port[1]);
  890. err_del_port0_attach:
  891. if (dev->info->ts_0)
  892. smi_port_detach(&dev->ts_port[0]);
  893. err_del_i2c_adaptor:
  894. smi_i2c_exit(dev);
  895. err_pci_iounmap:
  896. iounmap(dev->lmmio);
  897. err_kfree:
  898. pci_set_drvdata(pdev, NULL);
  899. kfree(dev);
  900. err_pci_disable_device:
  901. pci_disable_device(pdev);
  902. return ret;
  903. }
  904. static void smi_remove(struct pci_dev *pdev)
  905. {
  906. struct smi_dev *dev = pci_get_drvdata(pdev);
  907. smi_write(MSI_INT_ENA_CLR, ALL_INT);
  908. free_irq(dev->pci_dev->irq, dev);
  909. #ifdef CONFIG_PCI_MSI
  910. pci_disable_msi(dev->pci_dev);
  911. #endif
  912. if (dev->info->ts_1)
  913. smi_port_detach(&dev->ts_port[1]);
  914. if (dev->info->ts_0)
  915. smi_port_detach(&dev->ts_port[0]);
  916. smi_ir_exit(dev);
  917. smi_i2c_exit(dev);
  918. iounmap(dev->lmmio);
  919. pci_set_drvdata(pdev, NULL);
  920. pci_disable_device(pdev);
  921. kfree(dev);
  922. }
  923. /* DVBSky cards */
  924. static struct smi_cfg_info dvbsky_s950_cfg = {
  925. .type = SMI_DVBSKY_S950,
  926. .name = "DVBSky S950 V3",
  927. .ts_0 = SMI_TS_NULL,
  928. .ts_1 = SMI_TS_DMA_BOTH,
  929. .fe_0 = DVBSKY_FE_NULL,
  930. .fe_1 = DVBSKY_FE_M88DS3103,
  931. };
  932. static struct smi_cfg_info dvbsky_s952_cfg = {
  933. .type = SMI_DVBSKY_S952,
  934. .name = "DVBSky S952 V3",
  935. .ts_0 = SMI_TS_DMA_BOTH,
  936. .ts_1 = SMI_TS_DMA_BOTH,
  937. .fe_0 = DVBSKY_FE_M88RS6000,
  938. .fe_1 = DVBSKY_FE_M88RS6000,
  939. };
  940. static struct smi_cfg_info dvbsky_t9580_cfg = {
  941. .type = SMI_DVBSKY_T9580,
  942. .name = "DVBSky T9580 V3",
  943. .ts_0 = SMI_TS_DMA_BOTH,
  944. .ts_1 = SMI_TS_DMA_BOTH,
  945. .fe_0 = DVBSKY_FE_SIT2,
  946. .fe_1 = DVBSKY_FE_M88DS3103,
  947. };
  948. /* PCI IDs */
  949. #define SMI_ID(_subvend, _subdev, _driverdata) { \
  950. .vendor = SMI_VID, .device = SMI_PID, \
  951. .subvendor = _subvend, .subdevice = _subdev, \
  952. .driver_data = (unsigned long)&_driverdata }
  953. static const struct pci_device_id smi_id_table[] = {
  954. SMI_ID(0x4254, 0x0550, dvbsky_s950_cfg),
  955. SMI_ID(0x4254, 0x0552, dvbsky_s952_cfg),
  956. SMI_ID(0x4254, 0x5580, dvbsky_t9580_cfg),
  957. {0}
  958. };
  959. MODULE_DEVICE_TABLE(pci, smi_id_table);
  960. static struct pci_driver smipcie_driver = {
  961. .name = "SMI PCIe driver",
  962. .id_table = smi_id_table,
  963. .probe = smi_probe,
  964. .remove = smi_remove,
  965. };
  966. module_pci_driver(smipcie_driver);
  967. MODULE_AUTHOR("Max nibble <nibble.max@gmail.com>");
  968. MODULE_DESCRIPTION("SMI PCIe driver");
  969. MODULE_LICENSE("GPL");