solo6x10-core.c 17 KB

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  1. /*
  2. * Copyright (C) 2010-2013 Bluecherry, LLC <http://www.bluecherrydvr.com>
  3. *
  4. * Original author:
  5. * Ben Collins <bcollins@ubuntu.com>
  6. *
  7. * Additional work by:
  8. * John Brooks <john.brooks@bluecherry.net>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/module.h>
  22. #include <linux/pci.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/videodev2.h>
  25. #include <linux/delay.h>
  26. #include <linux/sysfs.h>
  27. #include <linux/ktime.h>
  28. #include <linux/slab.h>
  29. #include "solo6x10.h"
  30. #include "solo6x10-tw28.h"
  31. MODULE_DESCRIPTION("Softlogic 6x10 MPEG4/H.264/G.723 CODEC V4L2/ALSA Driver");
  32. MODULE_AUTHOR("Bluecherry <maintainers@bluecherrydvr.com>");
  33. MODULE_VERSION(SOLO6X10_VERSION);
  34. MODULE_LICENSE("GPL");
  35. static unsigned video_nr = -1;
  36. module_param(video_nr, uint, 0644);
  37. MODULE_PARM_DESC(video_nr, "videoX start number, -1 is autodetect (default)");
  38. static int full_eeprom; /* default is only top 64B */
  39. module_param(full_eeprom, uint, 0644);
  40. MODULE_PARM_DESC(full_eeprom, "Allow access to full 128B EEPROM (dangerous)");
  41. static void solo_set_time(struct solo_dev *solo_dev)
  42. {
  43. struct timespec ts;
  44. ktime_get_ts(&ts);
  45. solo_reg_write(solo_dev, SOLO_TIMER_SEC, ts.tv_sec);
  46. solo_reg_write(solo_dev, SOLO_TIMER_USEC, ts.tv_nsec / NSEC_PER_USEC);
  47. }
  48. static void solo_timer_sync(struct solo_dev *solo_dev)
  49. {
  50. u32 sec, usec;
  51. struct timespec ts;
  52. long diff;
  53. if (solo_dev->type != SOLO_DEV_6110)
  54. return;
  55. if (++solo_dev->time_sync < 60)
  56. return;
  57. solo_dev->time_sync = 0;
  58. sec = solo_reg_read(solo_dev, SOLO_TIMER_SEC);
  59. usec = solo_reg_read(solo_dev, SOLO_TIMER_USEC);
  60. ktime_get_ts(&ts);
  61. diff = (long)ts.tv_sec - (long)sec;
  62. diff = (diff * 1000000)
  63. + ((long)(ts.tv_nsec / NSEC_PER_USEC) - (long)usec);
  64. if (diff > 1000 || diff < -1000) {
  65. solo_set_time(solo_dev);
  66. } else if (diff) {
  67. long usec_lsb = solo_dev->usec_lsb;
  68. usec_lsb -= diff / 4;
  69. if (usec_lsb < 0)
  70. usec_lsb = 0;
  71. else if (usec_lsb > 255)
  72. usec_lsb = 255;
  73. solo_dev->usec_lsb = usec_lsb;
  74. solo_reg_write(solo_dev, SOLO_TIMER_USEC_LSB,
  75. solo_dev->usec_lsb);
  76. }
  77. }
  78. static irqreturn_t solo_isr(int irq, void *data)
  79. {
  80. struct solo_dev *solo_dev = data;
  81. u32 status;
  82. int i;
  83. status = solo_reg_read(solo_dev, SOLO_IRQ_STAT);
  84. if (!status)
  85. return IRQ_NONE;
  86. /* Acknowledge all interrupts immediately */
  87. solo_reg_write(solo_dev, SOLO_IRQ_STAT, status);
  88. if (status & SOLO_IRQ_PCI_ERR)
  89. solo_p2m_error_isr(solo_dev);
  90. for (i = 0; i < SOLO_NR_P2M; i++)
  91. if (status & SOLO_IRQ_P2M(i))
  92. solo_p2m_isr(solo_dev, i);
  93. if (status & SOLO_IRQ_IIC)
  94. solo_i2c_isr(solo_dev);
  95. if (status & SOLO_IRQ_VIDEO_IN) {
  96. solo_video_in_isr(solo_dev);
  97. solo_timer_sync(solo_dev);
  98. }
  99. if (status & SOLO_IRQ_ENCODER)
  100. solo_enc_v4l2_isr(solo_dev);
  101. if (status & SOLO_IRQ_G723)
  102. solo_g723_isr(solo_dev);
  103. return IRQ_HANDLED;
  104. }
  105. static void free_solo_dev(struct solo_dev *solo_dev)
  106. {
  107. struct pci_dev *pdev = solo_dev->pdev;
  108. if (solo_dev->dev.parent)
  109. device_unregister(&solo_dev->dev);
  110. if (solo_dev->reg_base) {
  111. /* Bring down the sub-devices first */
  112. solo_g723_exit(solo_dev);
  113. solo_enc_v4l2_exit(solo_dev);
  114. solo_enc_exit(solo_dev);
  115. solo_v4l2_exit(solo_dev);
  116. solo_disp_exit(solo_dev);
  117. solo_gpio_exit(solo_dev);
  118. solo_p2m_exit(solo_dev);
  119. solo_i2c_exit(solo_dev);
  120. /* Now cleanup the PCI device */
  121. solo_irq_off(solo_dev, ~0);
  122. free_irq(pdev->irq, solo_dev);
  123. pci_iounmap(pdev, solo_dev->reg_base);
  124. }
  125. pci_release_regions(pdev);
  126. pci_disable_device(pdev);
  127. v4l2_device_unregister(&solo_dev->v4l2_dev);
  128. pci_set_drvdata(pdev, NULL);
  129. kfree(solo_dev);
  130. }
  131. static ssize_t eeprom_store(struct device *dev, struct device_attribute *attr,
  132. const char *buf, size_t count)
  133. {
  134. struct solo_dev *solo_dev =
  135. container_of(dev, struct solo_dev, dev);
  136. u16 *p = (u16 *)buf;
  137. int i;
  138. if (count & 0x1)
  139. dev_warn(dev, "EEPROM Write not aligned (truncating)\n");
  140. if (!full_eeprom && count > 64) {
  141. dev_warn(dev, "EEPROM Write truncated to 64 bytes\n");
  142. count = 64;
  143. } else if (full_eeprom && count > 128) {
  144. dev_warn(dev, "EEPROM Write truncated to 128 bytes\n");
  145. count = 128;
  146. }
  147. solo_eeprom_ewen(solo_dev, 1);
  148. for (i = full_eeprom ? 0 : 32; i < min((int)(full_eeprom ? 64 : 32),
  149. (int)(count / 2)); i++)
  150. solo_eeprom_write(solo_dev, i, cpu_to_be16(p[i]));
  151. solo_eeprom_ewen(solo_dev, 0);
  152. return count;
  153. }
  154. static ssize_t eeprom_show(struct device *dev, struct device_attribute *attr,
  155. char *buf)
  156. {
  157. struct solo_dev *solo_dev =
  158. container_of(dev, struct solo_dev, dev);
  159. u16 *p = (u16 *)buf;
  160. int count = (full_eeprom ? 128 : 64);
  161. int i;
  162. for (i = (full_eeprom ? 0 : 32); i < (count / 2); i++)
  163. p[i] = be16_to_cpu(solo_eeprom_read(solo_dev, i));
  164. return count;
  165. }
  166. static ssize_t p2m_timeouts_show(struct device *dev,
  167. struct device_attribute *attr,
  168. char *buf)
  169. {
  170. struct solo_dev *solo_dev =
  171. container_of(dev, struct solo_dev, dev);
  172. return sprintf(buf, "%d\n", solo_dev->p2m_timeouts);
  173. }
  174. static ssize_t sdram_size_show(struct device *dev,
  175. struct device_attribute *attr,
  176. char *buf)
  177. {
  178. struct solo_dev *solo_dev =
  179. container_of(dev, struct solo_dev, dev);
  180. return sprintf(buf, "%dMegs\n", solo_dev->sdram_size >> 20);
  181. }
  182. static ssize_t tw28xx_show(struct device *dev,
  183. struct device_attribute *attr,
  184. char *buf)
  185. {
  186. struct solo_dev *solo_dev =
  187. container_of(dev, struct solo_dev, dev);
  188. return sprintf(buf, "tw2815[%d] tw2864[%d] tw2865[%d]\n",
  189. hweight32(solo_dev->tw2815),
  190. hweight32(solo_dev->tw2864),
  191. hweight32(solo_dev->tw2865));
  192. }
  193. static ssize_t input_map_show(struct device *dev,
  194. struct device_attribute *attr,
  195. char *buf)
  196. {
  197. struct solo_dev *solo_dev =
  198. container_of(dev, struct solo_dev, dev);
  199. unsigned int val;
  200. char *out = buf;
  201. val = solo_reg_read(solo_dev, SOLO_VI_CH_SWITCH_0);
  202. out += sprintf(out, "Channel 0 => Input %d\n", val & 0x1f);
  203. out += sprintf(out, "Channel 1 => Input %d\n", (val >> 5) & 0x1f);
  204. out += sprintf(out, "Channel 2 => Input %d\n", (val >> 10) & 0x1f);
  205. out += sprintf(out, "Channel 3 => Input %d\n", (val >> 15) & 0x1f);
  206. out += sprintf(out, "Channel 4 => Input %d\n", (val >> 20) & 0x1f);
  207. out += sprintf(out, "Channel 5 => Input %d\n", (val >> 25) & 0x1f);
  208. val = solo_reg_read(solo_dev, SOLO_VI_CH_SWITCH_1);
  209. out += sprintf(out, "Channel 6 => Input %d\n", val & 0x1f);
  210. out += sprintf(out, "Channel 7 => Input %d\n", (val >> 5) & 0x1f);
  211. out += sprintf(out, "Channel 8 => Input %d\n", (val >> 10) & 0x1f);
  212. out += sprintf(out, "Channel 9 => Input %d\n", (val >> 15) & 0x1f);
  213. out += sprintf(out, "Channel 10 => Input %d\n", (val >> 20) & 0x1f);
  214. out += sprintf(out, "Channel 11 => Input %d\n", (val >> 25) & 0x1f);
  215. val = solo_reg_read(solo_dev, SOLO_VI_CH_SWITCH_2);
  216. out += sprintf(out, "Channel 12 => Input %d\n", val & 0x1f);
  217. out += sprintf(out, "Channel 13 => Input %d\n", (val >> 5) & 0x1f);
  218. out += sprintf(out, "Channel 14 => Input %d\n", (val >> 10) & 0x1f);
  219. out += sprintf(out, "Channel 15 => Input %d\n", (val >> 15) & 0x1f);
  220. out += sprintf(out, "Spot Output => Input %d\n", (val >> 20) & 0x1f);
  221. return out - buf;
  222. }
  223. static ssize_t p2m_timeout_store(struct device *dev,
  224. struct device_attribute *attr,
  225. const char *buf, size_t count)
  226. {
  227. struct solo_dev *solo_dev =
  228. container_of(dev, struct solo_dev, dev);
  229. unsigned long ms;
  230. int ret = kstrtoul(buf, 10, &ms);
  231. if (ret < 0 || ms > 200)
  232. return -EINVAL;
  233. solo_dev->p2m_jiffies = msecs_to_jiffies(ms);
  234. return count;
  235. }
  236. static ssize_t p2m_timeout_show(struct device *dev,
  237. struct device_attribute *attr,
  238. char *buf)
  239. {
  240. struct solo_dev *solo_dev =
  241. container_of(dev, struct solo_dev, dev);
  242. return sprintf(buf, "%ums\n", jiffies_to_msecs(solo_dev->p2m_jiffies));
  243. }
  244. static ssize_t intervals_show(struct device *dev,
  245. struct device_attribute *attr,
  246. char *buf)
  247. {
  248. struct solo_dev *solo_dev =
  249. container_of(dev, struct solo_dev, dev);
  250. char *out = buf;
  251. int fps = solo_dev->fps;
  252. int i;
  253. for (i = 0; i < solo_dev->nr_chans; i++) {
  254. out += sprintf(out, "Channel %d: %d/%d (0x%08x)\n",
  255. i, solo_dev->v4l2_enc[i]->interval, fps,
  256. solo_reg_read(solo_dev, SOLO_CAP_CH_INTV(i)));
  257. }
  258. return out - buf;
  259. }
  260. static ssize_t sdram_offsets_show(struct device *dev,
  261. struct device_attribute *attr,
  262. char *buf)
  263. {
  264. struct solo_dev *solo_dev =
  265. container_of(dev, struct solo_dev, dev);
  266. char *out = buf;
  267. out += sprintf(out, "DISP: 0x%08x @ 0x%08x\n",
  268. SOLO_DISP_EXT_ADDR,
  269. SOLO_DISP_EXT_SIZE);
  270. out += sprintf(out, "EOSD: 0x%08x @ 0x%08x (0x%08x * %d)\n",
  271. SOLO_EOSD_EXT_ADDR,
  272. SOLO_EOSD_EXT_AREA(solo_dev),
  273. SOLO_EOSD_EXT_SIZE(solo_dev),
  274. SOLO_EOSD_EXT_AREA(solo_dev) /
  275. SOLO_EOSD_EXT_SIZE(solo_dev));
  276. out += sprintf(out, "MOTI: 0x%08x @ 0x%08x\n",
  277. SOLO_MOTION_EXT_ADDR(solo_dev),
  278. SOLO_MOTION_EXT_SIZE);
  279. out += sprintf(out, "G723: 0x%08x @ 0x%08x\n",
  280. SOLO_G723_EXT_ADDR(solo_dev),
  281. SOLO_G723_EXT_SIZE);
  282. out += sprintf(out, "CAPT: 0x%08x @ 0x%08x (0x%08x * %d)\n",
  283. SOLO_CAP_EXT_ADDR(solo_dev),
  284. SOLO_CAP_EXT_SIZE(solo_dev),
  285. SOLO_CAP_PAGE_SIZE,
  286. SOLO_CAP_EXT_SIZE(solo_dev) / SOLO_CAP_PAGE_SIZE);
  287. out += sprintf(out, "EREF: 0x%08x @ 0x%08x (0x%08x * %d)\n",
  288. SOLO_EREF_EXT_ADDR(solo_dev),
  289. SOLO_EREF_EXT_AREA(solo_dev),
  290. SOLO_EREF_EXT_SIZE,
  291. SOLO_EREF_EXT_AREA(solo_dev) / SOLO_EREF_EXT_SIZE);
  292. out += sprintf(out, "MPEG: 0x%08x @ 0x%08x\n",
  293. SOLO_MP4E_EXT_ADDR(solo_dev),
  294. SOLO_MP4E_EXT_SIZE(solo_dev));
  295. out += sprintf(out, "JPEG: 0x%08x @ 0x%08x\n",
  296. SOLO_JPEG_EXT_ADDR(solo_dev),
  297. SOLO_JPEG_EXT_SIZE(solo_dev));
  298. return out - buf;
  299. }
  300. static ssize_t sdram_show(struct file *file, struct kobject *kobj,
  301. struct bin_attribute *a, char *buf,
  302. loff_t off, size_t count)
  303. {
  304. struct device *dev = container_of(kobj, struct device, kobj);
  305. struct solo_dev *solo_dev =
  306. container_of(dev, struct solo_dev, dev);
  307. const int size = solo_dev->sdram_size;
  308. if (off >= size)
  309. return 0;
  310. if (off + count > size)
  311. count = size - off;
  312. if (solo_p2m_dma(solo_dev, 0, buf, off, count, 0, 0))
  313. return -EIO;
  314. return count;
  315. }
  316. static const struct device_attribute solo_dev_attrs[] = {
  317. __ATTR(eeprom, 0640, eeprom_show, eeprom_store),
  318. __ATTR(p2m_timeout, 0644, p2m_timeout_show, p2m_timeout_store),
  319. __ATTR_RO(p2m_timeouts),
  320. __ATTR_RO(sdram_size),
  321. __ATTR_RO(tw28xx),
  322. __ATTR_RO(input_map),
  323. __ATTR_RO(intervals),
  324. __ATTR_RO(sdram_offsets),
  325. };
  326. static void solo_device_release(struct device *dev)
  327. {
  328. /* Do nothing */
  329. }
  330. static int solo_sysfs_init(struct solo_dev *solo_dev)
  331. {
  332. struct bin_attribute *sdram_attr = &solo_dev->sdram_attr;
  333. struct device *dev = &solo_dev->dev;
  334. const char *driver;
  335. int i;
  336. if (solo_dev->type == SOLO_DEV_6110)
  337. driver = "solo6110";
  338. else
  339. driver = "solo6010";
  340. dev->release = solo_device_release;
  341. dev->parent = &solo_dev->pdev->dev;
  342. set_dev_node(dev, dev_to_node(&solo_dev->pdev->dev));
  343. dev_set_name(dev, "%s-%d-%d", driver, solo_dev->vfd->num,
  344. solo_dev->nr_chans);
  345. if (device_register(dev)) {
  346. dev->parent = NULL;
  347. return -ENOMEM;
  348. }
  349. for (i = 0; i < ARRAY_SIZE(solo_dev_attrs); i++) {
  350. if (device_create_file(dev, &solo_dev_attrs[i])) {
  351. device_unregister(dev);
  352. return -ENOMEM;
  353. }
  354. }
  355. sysfs_attr_init(&sdram_attr->attr);
  356. sdram_attr->attr.name = "sdram";
  357. sdram_attr->attr.mode = 0440;
  358. sdram_attr->read = sdram_show;
  359. sdram_attr->size = solo_dev->sdram_size;
  360. if (device_create_bin_file(dev, sdram_attr)) {
  361. device_unregister(dev);
  362. return -ENOMEM;
  363. }
  364. return 0;
  365. }
  366. static int solo_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  367. {
  368. struct solo_dev *solo_dev;
  369. int ret;
  370. u8 chip_id;
  371. solo_dev = kzalloc(sizeof(*solo_dev), GFP_KERNEL);
  372. if (solo_dev == NULL)
  373. return -ENOMEM;
  374. if (id->driver_data == SOLO_DEV_6010)
  375. dev_info(&pdev->dev, "Probing Softlogic 6010\n");
  376. else
  377. dev_info(&pdev->dev, "Probing Softlogic 6110\n");
  378. solo_dev->type = id->driver_data;
  379. solo_dev->pdev = pdev;
  380. ret = v4l2_device_register(&pdev->dev, &solo_dev->v4l2_dev);
  381. if (ret)
  382. goto fail_probe;
  383. /* Only for during init */
  384. solo_dev->p2m_jiffies = msecs_to_jiffies(100);
  385. ret = pci_enable_device(pdev);
  386. if (ret)
  387. goto fail_probe;
  388. pci_set_master(pdev);
  389. /* RETRY/TRDY Timeout disabled */
  390. pci_write_config_byte(pdev, 0x40, 0x00);
  391. pci_write_config_byte(pdev, 0x41, 0x00);
  392. ret = pci_request_regions(pdev, SOLO6X10_NAME);
  393. if (ret)
  394. goto fail_probe;
  395. solo_dev->reg_base = pci_ioremap_bar(pdev, 0);
  396. if (solo_dev->reg_base == NULL) {
  397. ret = -ENOMEM;
  398. goto fail_probe;
  399. }
  400. chip_id = solo_reg_read(solo_dev, SOLO_CHIP_OPTION) &
  401. SOLO_CHIP_ID_MASK;
  402. switch (chip_id) {
  403. case 7:
  404. solo_dev->nr_chans = 16;
  405. solo_dev->nr_ext = 5;
  406. break;
  407. case 6:
  408. solo_dev->nr_chans = 8;
  409. solo_dev->nr_ext = 2;
  410. break;
  411. default:
  412. dev_warn(&pdev->dev, "Invalid chip_id 0x%02x, assuming 4 ch\n",
  413. chip_id);
  414. case 5:
  415. solo_dev->nr_chans = 4;
  416. solo_dev->nr_ext = 1;
  417. }
  418. /* Disable all interrupts to start */
  419. solo_irq_off(solo_dev, ~0);
  420. /* Initial global settings */
  421. if (solo_dev->type == SOLO_DEV_6010) {
  422. solo_dev->clock_mhz = 108;
  423. solo_dev->sys_config = SOLO_SYS_CFG_SDRAM64BIT
  424. | SOLO_SYS_CFG_INPUTDIV(25)
  425. | SOLO_SYS_CFG_FEEDBACKDIV(solo_dev->clock_mhz * 2 - 2)
  426. | SOLO_SYS_CFG_OUTDIV(3);
  427. solo_reg_write(solo_dev, SOLO_SYS_CFG, solo_dev->sys_config);
  428. } else {
  429. u32 divq, divf;
  430. solo_dev->clock_mhz = 135;
  431. if (solo_dev->clock_mhz < 125) {
  432. divq = 3;
  433. divf = (solo_dev->clock_mhz * 4) / 3 - 1;
  434. } else {
  435. divq = 2;
  436. divf = (solo_dev->clock_mhz * 2) / 3 - 1;
  437. }
  438. solo_reg_write(solo_dev, SOLO_PLL_CONFIG,
  439. (1 << 20) | /* PLL_RANGE */
  440. (8 << 15) | /* PLL_DIVR */
  441. (divq << 12) |
  442. (divf << 4) |
  443. (1 << 1) /* PLL_FSEN */);
  444. solo_dev->sys_config = SOLO_SYS_CFG_SDRAM64BIT;
  445. }
  446. solo_reg_write(solo_dev, SOLO_SYS_CFG, solo_dev->sys_config);
  447. solo_reg_write(solo_dev, SOLO_TIMER_CLOCK_NUM,
  448. solo_dev->clock_mhz - 1);
  449. /* PLL locking time of 1ms */
  450. mdelay(1);
  451. ret = request_irq(pdev->irq, solo_isr, IRQF_SHARED, SOLO6X10_NAME,
  452. solo_dev);
  453. if (ret)
  454. goto fail_probe;
  455. /* Handle this from the start */
  456. solo_irq_on(solo_dev, SOLO_IRQ_PCI_ERR);
  457. ret = solo_i2c_init(solo_dev);
  458. if (ret)
  459. goto fail_probe;
  460. /* Setup the DMA engine */
  461. solo_reg_write(solo_dev, SOLO_DMA_CTRL,
  462. SOLO_DMA_CTRL_REFRESH_CYCLE(1) |
  463. SOLO_DMA_CTRL_SDRAM_SIZE(2) |
  464. SOLO_DMA_CTRL_SDRAM_CLK_INVERT |
  465. SOLO_DMA_CTRL_READ_CLK_SELECT |
  466. SOLO_DMA_CTRL_LATENCY(1));
  467. /* Undocumented crap */
  468. solo_reg_write(solo_dev, SOLO_DMA_CTRL1,
  469. solo_dev->type == SOLO_DEV_6010 ? 0x100 : 0x300);
  470. if (solo_dev->type != SOLO_DEV_6010) {
  471. solo_dev->usec_lsb = 0x3f;
  472. solo_set_time(solo_dev);
  473. }
  474. /* Disable watchdog */
  475. solo_reg_write(solo_dev, SOLO_WATCHDOG, 0);
  476. /* Initialize sub components */
  477. ret = solo_p2m_init(solo_dev);
  478. if (ret)
  479. goto fail_probe;
  480. ret = solo_disp_init(solo_dev);
  481. if (ret)
  482. goto fail_probe;
  483. ret = solo_gpio_init(solo_dev);
  484. if (ret)
  485. goto fail_probe;
  486. ret = solo_tw28_init(solo_dev);
  487. if (ret)
  488. goto fail_probe;
  489. ret = solo_v4l2_init(solo_dev, video_nr);
  490. if (ret)
  491. goto fail_probe;
  492. ret = solo_enc_init(solo_dev);
  493. if (ret)
  494. goto fail_probe;
  495. ret = solo_enc_v4l2_init(solo_dev, video_nr);
  496. if (ret)
  497. goto fail_probe;
  498. ret = solo_g723_init(solo_dev);
  499. if (ret)
  500. goto fail_probe;
  501. ret = solo_sysfs_init(solo_dev);
  502. if (ret)
  503. goto fail_probe;
  504. /* Now that init is over, set this lower */
  505. solo_dev->p2m_jiffies = msecs_to_jiffies(20);
  506. return 0;
  507. fail_probe:
  508. free_solo_dev(solo_dev);
  509. return ret;
  510. }
  511. static void solo_pci_remove(struct pci_dev *pdev)
  512. {
  513. struct v4l2_device *v4l2_dev = pci_get_drvdata(pdev);
  514. struct solo_dev *solo_dev = container_of(v4l2_dev, struct solo_dev, v4l2_dev);
  515. free_solo_dev(solo_dev);
  516. }
  517. static const struct pci_device_id solo_id_table[] = {
  518. /* 6010 based cards */
  519. { PCI_DEVICE(PCI_VENDOR_ID_SOFTLOGIC, PCI_DEVICE_ID_SOLO6010),
  520. .driver_data = SOLO_DEV_6010 },
  521. { PCI_DEVICE(PCI_VENDOR_ID_BLUECHERRY, PCI_DEVICE_ID_NEUSOLO_4),
  522. .driver_data = SOLO_DEV_6010 },
  523. { PCI_DEVICE(PCI_VENDOR_ID_BLUECHERRY, PCI_DEVICE_ID_NEUSOLO_9),
  524. .driver_data = SOLO_DEV_6010 },
  525. { PCI_DEVICE(PCI_VENDOR_ID_BLUECHERRY, PCI_DEVICE_ID_NEUSOLO_16),
  526. .driver_data = SOLO_DEV_6010 },
  527. { PCI_DEVICE(PCI_VENDOR_ID_BLUECHERRY, PCI_DEVICE_ID_BC_SOLO_4),
  528. .driver_data = SOLO_DEV_6010 },
  529. { PCI_DEVICE(PCI_VENDOR_ID_BLUECHERRY, PCI_DEVICE_ID_BC_SOLO_9),
  530. .driver_data = SOLO_DEV_6010 },
  531. { PCI_DEVICE(PCI_VENDOR_ID_BLUECHERRY, PCI_DEVICE_ID_BC_SOLO_16),
  532. .driver_data = SOLO_DEV_6010 },
  533. /* 6110 based cards */
  534. { PCI_DEVICE(PCI_VENDOR_ID_SOFTLOGIC, PCI_DEVICE_ID_SOLO6110),
  535. .driver_data = SOLO_DEV_6110 },
  536. { PCI_DEVICE(PCI_VENDOR_ID_BLUECHERRY, PCI_DEVICE_ID_BC_6110_4),
  537. .driver_data = SOLO_DEV_6110 },
  538. { PCI_DEVICE(PCI_VENDOR_ID_BLUECHERRY, PCI_DEVICE_ID_BC_6110_8),
  539. .driver_data = SOLO_DEV_6110 },
  540. { PCI_DEVICE(PCI_VENDOR_ID_BLUECHERRY, PCI_DEVICE_ID_BC_6110_16),
  541. .driver_data = SOLO_DEV_6110 },
  542. {0,}
  543. };
  544. MODULE_DEVICE_TABLE(pci, solo_id_table);
  545. static struct pci_driver solo_pci_driver = {
  546. .name = SOLO6X10_NAME,
  547. .id_table = solo_id_table,
  548. .probe = solo_pci_probe,
  549. .remove = solo_pci_remove,
  550. };
  551. module_pci_driver(solo_pci_driver);