solo6x10-p2m.c 8.6 KB

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  1. /*
  2. * Copyright (C) 2010-2013 Bluecherry, LLC <http://www.bluecherrydvr.com>
  3. *
  4. * Original author:
  5. * Ben Collins <bcollins@ubuntu.com>
  6. *
  7. * Additional work by:
  8. * John Brooks <john.brooks@bluecherry.net>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/module.h>
  22. #include <linux/slab.h>
  23. #include "solo6x10.h"
  24. static int multi_p2m;
  25. module_param(multi_p2m, uint, 0644);
  26. MODULE_PARM_DESC(multi_p2m,
  27. "Use multiple P2M DMA channels (default: no, 6010-only)");
  28. static int desc_mode;
  29. module_param(desc_mode, uint, 0644);
  30. MODULE_PARM_DESC(desc_mode,
  31. "Allow use of descriptor mode DMA (default: no, 6010-only)");
  32. int solo_p2m_dma(struct solo_dev *solo_dev, int wr,
  33. void *sys_addr, u32 ext_addr, u32 size,
  34. int repeat, u32 ext_size)
  35. {
  36. dma_addr_t dma_addr;
  37. int ret;
  38. if (WARN_ON_ONCE((unsigned long)sys_addr & 0x03))
  39. return -EINVAL;
  40. if (WARN_ON_ONCE(!size))
  41. return -EINVAL;
  42. dma_addr = pci_map_single(solo_dev->pdev, sys_addr, size,
  43. wr ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  44. if (pci_dma_mapping_error(solo_dev->pdev, dma_addr))
  45. return -ENOMEM;
  46. ret = solo_p2m_dma_t(solo_dev, wr, dma_addr, ext_addr, size,
  47. repeat, ext_size);
  48. pci_unmap_single(solo_dev->pdev, dma_addr, size,
  49. wr ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  50. return ret;
  51. }
  52. /* Mutex must be held for p2m_id before calling this!! */
  53. int solo_p2m_dma_desc(struct solo_dev *solo_dev,
  54. struct solo_p2m_desc *desc, dma_addr_t desc_dma,
  55. int desc_cnt)
  56. {
  57. struct solo_p2m_dev *p2m_dev;
  58. unsigned int timeout;
  59. unsigned int config = 0;
  60. int ret = 0;
  61. int p2m_id = 0;
  62. /* Get next ID. According to Softlogic, 6110 has problems on !=0 P2M */
  63. if (solo_dev->type != SOLO_DEV_6110 && multi_p2m) {
  64. p2m_id = atomic_inc_return(&solo_dev->p2m_count) % SOLO_NR_P2M;
  65. if (p2m_id < 0)
  66. p2m_id = -p2m_id;
  67. }
  68. p2m_dev = &solo_dev->p2m_dev[p2m_id];
  69. if (mutex_lock_interruptible(&p2m_dev->mutex))
  70. return -EINTR;
  71. reinit_completion(&p2m_dev->completion);
  72. p2m_dev->error = 0;
  73. if (desc_cnt > 1 && solo_dev->type != SOLO_DEV_6110 && desc_mode) {
  74. /* For 6010 with more than one desc, we can do a one-shot */
  75. p2m_dev->desc_count = p2m_dev->desc_idx = 0;
  76. config = solo_reg_read(solo_dev, SOLO_P2M_CONFIG(p2m_id));
  77. solo_reg_write(solo_dev, SOLO_P2M_DES_ADR(p2m_id), desc_dma);
  78. solo_reg_write(solo_dev, SOLO_P2M_DESC_ID(p2m_id), desc_cnt);
  79. solo_reg_write(solo_dev, SOLO_P2M_CONFIG(p2m_id), config |
  80. SOLO_P2M_DESC_MODE);
  81. } else {
  82. /* For single descriptors and 6110, we need to run each desc */
  83. p2m_dev->desc_count = desc_cnt;
  84. p2m_dev->desc_idx = 1;
  85. p2m_dev->descs = desc;
  86. solo_reg_write(solo_dev, SOLO_P2M_TAR_ADR(p2m_id),
  87. desc[1].dma_addr);
  88. solo_reg_write(solo_dev, SOLO_P2M_EXT_ADR(p2m_id),
  89. desc[1].ext_addr);
  90. solo_reg_write(solo_dev, SOLO_P2M_EXT_CFG(p2m_id),
  91. desc[1].cfg);
  92. solo_reg_write(solo_dev, SOLO_P2M_CONTROL(p2m_id),
  93. desc[1].ctrl);
  94. }
  95. timeout = wait_for_completion_timeout(&p2m_dev->completion,
  96. solo_dev->p2m_jiffies);
  97. if (WARN_ON_ONCE(p2m_dev->error))
  98. ret = -EIO;
  99. else if (timeout == 0) {
  100. solo_dev->p2m_timeouts++;
  101. ret = -EAGAIN;
  102. }
  103. solo_reg_write(solo_dev, SOLO_P2M_CONTROL(p2m_id), 0);
  104. /* Don't write here for the no_desc_mode case, because config is 0.
  105. * We can't test no_desc_mode again, it might race. */
  106. if (desc_cnt > 1 && solo_dev->type != SOLO_DEV_6110 && config)
  107. solo_reg_write(solo_dev, SOLO_P2M_CONFIG(p2m_id), config);
  108. mutex_unlock(&p2m_dev->mutex);
  109. return ret;
  110. }
  111. void solo_p2m_fill_desc(struct solo_p2m_desc *desc, int wr,
  112. dma_addr_t dma_addr, u32 ext_addr, u32 size,
  113. int repeat, u32 ext_size)
  114. {
  115. WARN_ON_ONCE(dma_addr & 0x03);
  116. WARN_ON_ONCE(!size);
  117. desc->cfg = SOLO_P2M_COPY_SIZE(size >> 2);
  118. desc->ctrl = SOLO_P2M_BURST_SIZE(SOLO_P2M_BURST_256) |
  119. (wr ? SOLO_P2M_WRITE : 0) | SOLO_P2M_TRANS_ON;
  120. if (repeat) {
  121. desc->cfg |= SOLO_P2M_EXT_INC(ext_size >> 2);
  122. desc->ctrl |= SOLO_P2M_PCI_INC(size >> 2) |
  123. SOLO_P2M_REPEAT(repeat);
  124. }
  125. desc->dma_addr = dma_addr;
  126. desc->ext_addr = ext_addr;
  127. }
  128. int solo_p2m_dma_t(struct solo_dev *solo_dev, int wr,
  129. dma_addr_t dma_addr, u32 ext_addr, u32 size,
  130. int repeat, u32 ext_size)
  131. {
  132. struct solo_p2m_desc desc[2];
  133. solo_p2m_fill_desc(&desc[1], wr, dma_addr, ext_addr, size, repeat,
  134. ext_size);
  135. /* No need for desc_dma since we know it is a single-shot */
  136. return solo_p2m_dma_desc(solo_dev, desc, 0, 1);
  137. }
  138. void solo_p2m_isr(struct solo_dev *solo_dev, int id)
  139. {
  140. struct solo_p2m_dev *p2m_dev = &solo_dev->p2m_dev[id];
  141. struct solo_p2m_desc *desc;
  142. if (p2m_dev->desc_count <= p2m_dev->desc_idx) {
  143. complete(&p2m_dev->completion);
  144. return;
  145. }
  146. /* Setup next descriptor */
  147. p2m_dev->desc_idx++;
  148. desc = &p2m_dev->descs[p2m_dev->desc_idx];
  149. solo_reg_write(solo_dev, SOLO_P2M_CONTROL(id), 0);
  150. solo_reg_write(solo_dev, SOLO_P2M_TAR_ADR(id), desc->dma_addr);
  151. solo_reg_write(solo_dev, SOLO_P2M_EXT_ADR(id), desc->ext_addr);
  152. solo_reg_write(solo_dev, SOLO_P2M_EXT_CFG(id), desc->cfg);
  153. solo_reg_write(solo_dev, SOLO_P2M_CONTROL(id), desc->ctrl);
  154. }
  155. void solo_p2m_error_isr(struct solo_dev *solo_dev)
  156. {
  157. unsigned int err = solo_reg_read(solo_dev, SOLO_PCI_ERR);
  158. struct solo_p2m_dev *p2m_dev;
  159. int i;
  160. if (!(err & (SOLO_PCI_ERR_P2M | SOLO_PCI_ERR_P2M_DESC)))
  161. return;
  162. for (i = 0; i < SOLO_NR_P2M; i++) {
  163. p2m_dev = &solo_dev->p2m_dev[i];
  164. p2m_dev->error = 1;
  165. solo_reg_write(solo_dev, SOLO_P2M_CONTROL(i), 0);
  166. complete(&p2m_dev->completion);
  167. }
  168. }
  169. void solo_p2m_exit(struct solo_dev *solo_dev)
  170. {
  171. int i;
  172. for (i = 0; i < SOLO_NR_P2M; i++)
  173. solo_irq_off(solo_dev, SOLO_IRQ_P2M(i));
  174. }
  175. static int solo_p2m_test(struct solo_dev *solo_dev, int base, int size)
  176. {
  177. u32 *wr_buf;
  178. u32 *rd_buf;
  179. int i;
  180. int ret = -EIO;
  181. int order = get_order(size);
  182. wr_buf = (u32 *)__get_free_pages(GFP_KERNEL, order);
  183. if (wr_buf == NULL)
  184. return -1;
  185. rd_buf = (u32 *)__get_free_pages(GFP_KERNEL, order);
  186. if (rd_buf == NULL) {
  187. free_pages((unsigned long)wr_buf, order);
  188. return -1;
  189. }
  190. for (i = 0; i < (size >> 3); i++)
  191. *(wr_buf + i) = (i << 16) | (i + 1);
  192. for (i = (size >> 3); i < (size >> 2); i++)
  193. *(wr_buf + i) = ~((i << 16) | (i + 1));
  194. memset(rd_buf, 0x55, size);
  195. if (solo_p2m_dma(solo_dev, 1, wr_buf, base, size, 0, 0))
  196. goto test_fail;
  197. if (solo_p2m_dma(solo_dev, 0, rd_buf, base, size, 0, 0))
  198. goto test_fail;
  199. for (i = 0; i < (size >> 2); i++) {
  200. if (*(wr_buf + i) != *(rd_buf + i))
  201. goto test_fail;
  202. }
  203. ret = 0;
  204. test_fail:
  205. free_pages((unsigned long)wr_buf, order);
  206. free_pages((unsigned long)rd_buf, order);
  207. return ret;
  208. }
  209. int solo_p2m_init(struct solo_dev *solo_dev)
  210. {
  211. struct solo_p2m_dev *p2m_dev;
  212. int i;
  213. for (i = 0; i < SOLO_NR_P2M; i++) {
  214. p2m_dev = &solo_dev->p2m_dev[i];
  215. mutex_init(&p2m_dev->mutex);
  216. init_completion(&p2m_dev->completion);
  217. solo_reg_write(solo_dev, SOLO_P2M_CONTROL(i), 0);
  218. solo_reg_write(solo_dev, SOLO_P2M_CONFIG(i),
  219. SOLO_P2M_CSC_16BIT_565 |
  220. SOLO_P2M_DESC_INTR_OPT |
  221. SOLO_P2M_DMA_INTERVAL(0) |
  222. SOLO_P2M_PCI_MASTER_MODE);
  223. solo_irq_on(solo_dev, SOLO_IRQ_P2M(i));
  224. }
  225. /* Find correct SDRAM size */
  226. for (solo_dev->sdram_size = 0, i = 2; i >= 0; i--) {
  227. solo_reg_write(solo_dev, SOLO_DMA_CTRL,
  228. SOLO_DMA_CTRL_REFRESH_CYCLE(1) |
  229. SOLO_DMA_CTRL_SDRAM_SIZE(i) |
  230. SOLO_DMA_CTRL_SDRAM_CLK_INVERT |
  231. SOLO_DMA_CTRL_READ_CLK_SELECT |
  232. SOLO_DMA_CTRL_LATENCY(1));
  233. solo_reg_write(solo_dev, SOLO_SYS_CFG, solo_dev->sys_config |
  234. SOLO_SYS_CFG_RESET);
  235. solo_reg_write(solo_dev, SOLO_SYS_CFG, solo_dev->sys_config);
  236. switch (i) {
  237. case 2:
  238. if (solo_p2m_test(solo_dev, 0x07ff0000, 0x00010000) ||
  239. solo_p2m_test(solo_dev, 0x05ff0000, 0x00010000))
  240. continue;
  241. break;
  242. case 1:
  243. if (solo_p2m_test(solo_dev, 0x03ff0000, 0x00010000))
  244. continue;
  245. break;
  246. default:
  247. if (solo_p2m_test(solo_dev, 0x01ff0000, 0x00010000))
  248. continue;
  249. }
  250. solo_dev->sdram_size = (32 << 20) << i;
  251. break;
  252. }
  253. if (!solo_dev->sdram_size) {
  254. dev_err(&solo_dev->pdev->dev, "Error detecting SDRAM size\n");
  255. return -EIO;
  256. }
  257. if (SOLO_SDRAM_END(solo_dev) > solo_dev->sdram_size) {
  258. dev_err(&solo_dev->pdev->dev,
  259. "SDRAM is not large enough (%u < %u)\n",
  260. solo_dev->sdram_size, SOLO_SDRAM_END(solo_dev));
  261. return -EIO;
  262. }
  263. return 0;
  264. }