fintek-cir.h 6.5 KB

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  1. /*
  2. * Driver for Feature Integration Technology Inc. (aka Fintek) LPC CIR
  3. *
  4. * Copyright (C) 2011 Jarod Wilson <jarod@redhat.com>
  5. *
  6. * Special thanks to Fintek for providing hardware and spec sheets.
  7. * This driver is based upon the nuvoton, ite and ene drivers for
  8. * similar hardware.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of the
  13. * License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  23. * USA
  24. */
  25. #include <linux/spinlock.h>
  26. #include <linux/ioctl.h>
  27. /* platform driver name to register */
  28. #define FINTEK_DRIVER_NAME "fintek-cir"
  29. #define FINTEK_DESCRIPTION "Fintek LPC SuperIO Consumer IR Transceiver"
  30. #define VENDOR_ID_FINTEK 0x1934
  31. /* debugging module parameter */
  32. static int debug;
  33. #define fit_pr(level, text, ...) \
  34. printk(level KBUILD_MODNAME ": " text, ## __VA_ARGS__)
  35. #define fit_dbg(text, ...) \
  36. if (debug) \
  37. printk(KERN_DEBUG \
  38. KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
  39. #define fit_dbg_verbose(text, ...) \
  40. if (debug > 1) \
  41. printk(KERN_DEBUG \
  42. KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
  43. #define fit_dbg_wake(text, ...) \
  44. if (debug > 2) \
  45. printk(KERN_DEBUG \
  46. KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
  47. #define TX_BUF_LEN 256
  48. #define RX_BUF_LEN 32
  49. struct fintek_dev {
  50. struct pnp_dev *pdev;
  51. struct rc_dev *rdev;
  52. spinlock_t fintek_lock;
  53. /* for rx */
  54. u8 buf[RX_BUF_LEN];
  55. unsigned int pkts;
  56. struct {
  57. spinlock_t lock;
  58. u8 buf[TX_BUF_LEN];
  59. unsigned int buf_count;
  60. unsigned int cur_buf_num;
  61. wait_queue_head_t queue;
  62. } tx;
  63. /* Config register index/data port pair */
  64. u32 cr_ip;
  65. u32 cr_dp;
  66. /* hardware I/O settings */
  67. unsigned long cir_addr;
  68. int cir_irq;
  69. int cir_port_len;
  70. /* hardware id */
  71. u8 chip_major;
  72. u8 chip_minor;
  73. u16 chip_vendor;
  74. u8 logical_dev_cir;
  75. /* hardware features */
  76. bool hw_learning_capable;
  77. bool hw_tx_capable;
  78. /* rx settings */
  79. bool learning_enabled;
  80. bool carrier_detect_enabled;
  81. enum {
  82. CMD_HEADER = 0,
  83. SUBCMD,
  84. CMD_DATA,
  85. PARSE_IRDATA,
  86. } parser_state;
  87. u8 cmd, rem;
  88. /* carrier period = 1 / frequency */
  89. u32 carrier;
  90. };
  91. /* buffer packet constants, largely identical to mceusb.c */
  92. #define BUF_PULSE_BIT 0x80
  93. #define BUF_LEN_MASK 0x1f
  94. #define BUF_SAMPLE_MASK 0x7f
  95. #define BUF_COMMAND_HEADER 0x9f
  96. #define BUF_COMMAND_MASK 0xe0
  97. #define BUF_COMMAND_NULL 0x00
  98. #define BUF_HW_CMD_HEADER 0xff
  99. #define BUF_CMD_G_REVISION 0x0b
  100. #define BUF_CMD_S_CARRIER 0x06
  101. #define BUF_CMD_S_TIMEOUT 0x0c
  102. #define BUF_CMD_SIG_END 0x01
  103. #define BUF_CMD_S_TXMASK 0x08
  104. #define BUF_CMD_S_RXSENSOR 0x14
  105. #define BUF_RSP_PULSE_COUNT 0x15
  106. #define CIR_SAMPLE_PERIOD 50
  107. /*
  108. * Configuration Register:
  109. * Index Port
  110. * Data Port
  111. */
  112. #define CR_INDEX_PORT 0x2e
  113. #define CR_DATA_PORT 0x2f
  114. /* Possible alternate values, depends on how the chip is wired */
  115. #define CR_INDEX_PORT2 0x4e
  116. #define CR_DATA_PORT2 0x4f
  117. /*
  118. * GCR_CONFIG_PORT_SEL bit 4 specifies which Index Port value is
  119. * active. 1 = 0x4e, 0 = 0x2e
  120. */
  121. #define PORT_SEL_PORT_4E_EN 0x10
  122. /* Extended Function Mode enable/disable magic values */
  123. #define CONFIG_REG_ENABLE 0x87
  124. #define CONFIG_REG_DISABLE 0xaa
  125. /* Chip IDs found in CR_CHIP_ID_{HI,LO} */
  126. #define CHIP_ID_HIGH_F71809U 0x04
  127. #define CHIP_ID_LOW_F71809U 0x08
  128. /*
  129. * Global control regs we need to care about:
  130. * Global Control def.
  131. * Register name addr val. */
  132. #define GCR_SOFTWARE_RESET 0x02 /* 0x00 */
  133. #define GCR_LOGICAL_DEV_NO 0x07 /* 0x00 */
  134. #define GCR_CHIP_ID_HI 0x20 /* 0x04 */
  135. #define GCR_CHIP_ID_LO 0x21 /* 0x08 */
  136. #define GCR_VENDOR_ID_HI 0x23 /* 0x19 */
  137. #define GCR_VENDOR_ID_LO 0x24 /* 0x34 */
  138. #define GCR_CONFIG_PORT_SEL 0x25 /* 0x01 */
  139. #define GCR_KBMOUSE_WAKEUP 0x27
  140. #define LOGICAL_DEV_DISABLE 0x00
  141. #define LOGICAL_DEV_ENABLE 0x01
  142. /* Logical device number of the CIR function */
  143. #define LOGICAL_DEV_CIR_REV1 0x05
  144. #define LOGICAL_DEV_CIR_REV2 0x08
  145. /* CIR Logical Device (LDN 0x08) config registers */
  146. #define CIR_CR_COMMAND_INDEX 0x04
  147. #define CIR_CR_IRCS 0x05 /* Before host writes command to IR, host
  148. must set to 1. When host finshes write
  149. command to IR, host must clear to 0. */
  150. #define CIR_CR_COMMAND_DATA 0x06 /* Host read or write comand data */
  151. #define CIR_CR_CLASS 0x07 /* 0xff = rx-only, 0x66 = rx + 2 tx,
  152. 0x33 = rx + 1 tx */
  153. #define CIR_CR_DEV_EN 0x30 /* bit0 = 1 enables CIR */
  154. #define CIR_CR_BASE_ADDR_HI 0x60 /* MSB of CIR IO base addr */
  155. #define CIR_CR_BASE_ADDR_LO 0x61 /* LSB of CIR IO base addr */
  156. #define CIR_CR_IRQ_SEL 0x70 /* bits3-0 store CIR IRQ */
  157. #define CIR_CR_PSOUT_STATUS 0xf1
  158. #define CIR_CR_WAKE_KEY3_ADDR 0xf8
  159. #define CIR_CR_WAKE_KEY3_CODE 0xf9
  160. #define CIR_CR_WAKE_KEY3_DC 0xfa
  161. #define CIR_CR_WAKE_CONTROL 0xfb
  162. #define CIR_CR_WAKE_KEY12_ADDR 0xfc
  163. #define CIR_CR_WAKE_KEY4_ADDR 0xfd
  164. #define CIR_CR_WAKE_KEY5_ADDR 0xfe
  165. #define CLASS_RX_ONLY 0xff
  166. #define CLASS_RX_2TX 0x66
  167. #define CLASS_RX_1TX 0x33
  168. /* CIR device registers */
  169. #define CIR_STATUS 0x00
  170. #define CIR_RX_DATA 0x01
  171. #define CIR_TX_CONTROL 0x02
  172. #define CIR_TX_DATA 0x03
  173. #define CIR_CONTROL 0x04
  174. /* Bits to enable CIR wake */
  175. #define LOGICAL_DEV_ACPI 0x01
  176. #define LDEV_ACPI_WAKE_EN_REG 0xe8
  177. #define ACPI_WAKE_EN_CIR_BIT 0x04
  178. #define LDEV_ACPI_PME_EN_REG 0xf0
  179. #define LDEV_ACPI_PME_CLR_REG 0xf1
  180. #define ACPI_PME_CIR_BIT 0x02
  181. #define LDEV_ACPI_STATE_REG 0xf4
  182. #define ACPI_STATE_CIR_BIT 0x20
  183. /*
  184. * CIR status register (0x00):
  185. * 7 - CIR_IRQ_EN (1 = enable CIR IRQ, 0 = disable)
  186. * 3 - TX_FINISH (1 when TX finished, write 1 to clear)
  187. * 2 - TX_UNDERRUN (1 on TX underrun, write 1 to clear)
  188. * 1 - RX_TIMEOUT (1 on RX timeout, write 1 to clear)
  189. * 0 - RX_RECEIVE (1 on RX receive, write 1 to clear)
  190. */
  191. #define CIR_STATUS_IRQ_EN 0x80
  192. #define CIR_STATUS_TX_FINISH 0x08
  193. #define CIR_STATUS_TX_UNDERRUN 0x04
  194. #define CIR_STATUS_RX_TIMEOUT 0x02
  195. #define CIR_STATUS_RX_RECEIVE 0x01
  196. #define CIR_STATUS_IRQ_MASK 0x0f
  197. /*
  198. * CIR TX control register (0x02):
  199. * 7 - TX_START (1 to indicate TX start, auto-cleared when done)
  200. * 6 - TX_END (1 to indicate TX data written to TX fifo)
  201. */
  202. #define CIR_TX_CONTROL_TX_START 0x80
  203. #define CIR_TX_CONTROL_TX_END 0x40