tm6000-core.c 27 KB

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  1. /*
  2. * tm6000-core.c - driver for TM5600/TM6000/TM6010 USB video capture devices
  3. *
  4. * Copyright (C) 2006-2007 Mauro Carvalho Chehab <mchehab@infradead.org>
  5. *
  6. * Copyright (C) 2007 Michel Ludwig <michel.ludwig@gmail.com>
  7. * - DVB-T support
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation version 2
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/module.h>
  23. #include <linux/kernel.h>
  24. #include <linux/slab.h>
  25. #include <linux/usb.h>
  26. #include <linux/i2c.h>
  27. #include "tm6000.h"
  28. #include "tm6000-regs.h"
  29. #include <media/v4l2-common.h>
  30. #include <media/tuner.h>
  31. #define USB_TIMEOUT (5 * HZ) /* ms */
  32. int tm6000_read_write_usb(struct tm6000_core *dev, u8 req_type, u8 req,
  33. u16 value, u16 index, u8 *buf, u16 len)
  34. {
  35. int ret, i;
  36. unsigned int pipe;
  37. u8 *data = NULL;
  38. int delay = 5000;
  39. if (len) {
  40. data = kzalloc(len, GFP_KERNEL);
  41. if (!data)
  42. return -ENOMEM;
  43. }
  44. mutex_lock(&dev->usb_lock);
  45. if (req_type & USB_DIR_IN)
  46. pipe = usb_rcvctrlpipe(dev->udev, 0);
  47. else {
  48. pipe = usb_sndctrlpipe(dev->udev, 0);
  49. memcpy(data, buf, len);
  50. }
  51. if (tm6000_debug & V4L2_DEBUG_I2C) {
  52. printk(KERN_DEBUG "(dev %p, pipe %08x): ", dev->udev, pipe);
  53. printk(KERN_CONT "%s: %02x %02x %02x %02x %02x %02x %02x %02x ",
  54. (req_type & USB_DIR_IN) ? " IN" : "OUT",
  55. req_type, req, value&0xff, value>>8, index&0xff,
  56. index>>8, len&0xff, len>>8);
  57. if (!(req_type & USB_DIR_IN)) {
  58. printk(KERN_CONT ">>> ");
  59. for (i = 0; i < len; i++)
  60. printk(KERN_CONT " %02x", buf[i]);
  61. printk(KERN_CONT "\n");
  62. }
  63. }
  64. ret = usb_control_msg(dev->udev, pipe, req, req_type, value, index,
  65. data, len, USB_TIMEOUT);
  66. if (req_type & USB_DIR_IN)
  67. memcpy(buf, data, len);
  68. if (tm6000_debug & V4L2_DEBUG_I2C) {
  69. if (ret < 0) {
  70. if (req_type & USB_DIR_IN)
  71. printk(KERN_DEBUG "<<< (len=%d)\n", len);
  72. printk(KERN_CONT "%s: Error #%d\n", __func__, ret);
  73. } else if (req_type & USB_DIR_IN) {
  74. printk(KERN_CONT "<<< ");
  75. for (i = 0; i < len; i++)
  76. printk(KERN_CONT " %02x", buf[i]);
  77. printk(KERN_CONT "\n");
  78. }
  79. }
  80. kfree(data);
  81. if (dev->quirks & TM6000_QUIRK_NO_USB_DELAY)
  82. delay = 0;
  83. if (req == REQ_16_SET_GET_I2C_WR1_RDN && !(req_type & USB_DIR_IN)) {
  84. unsigned int tsleep;
  85. /* Calculate delay time, 14000us for 64 bytes */
  86. tsleep = (len * 200) + 200;
  87. if (tsleep < delay)
  88. tsleep = delay;
  89. usleep_range(tsleep, tsleep + 1000);
  90. }
  91. else if (delay)
  92. usleep_range(delay, delay + 1000);
  93. mutex_unlock(&dev->usb_lock);
  94. return ret;
  95. }
  96. int tm6000_set_reg(struct tm6000_core *dev, u8 req, u16 value, u16 index)
  97. {
  98. return
  99. tm6000_read_write_usb(dev, USB_DIR_OUT | USB_TYPE_VENDOR,
  100. req, value, index, NULL, 0);
  101. }
  102. EXPORT_SYMBOL_GPL(tm6000_set_reg);
  103. int tm6000_get_reg(struct tm6000_core *dev, u8 req, u16 value, u16 index)
  104. {
  105. int rc;
  106. u8 buf[1];
  107. rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
  108. value, index, buf, 1);
  109. if (rc < 0)
  110. return rc;
  111. return *buf;
  112. }
  113. EXPORT_SYMBOL_GPL(tm6000_get_reg);
  114. int tm6000_set_reg_mask(struct tm6000_core *dev, u8 req, u16 value,
  115. u16 index, u16 mask)
  116. {
  117. int rc;
  118. u8 buf[1];
  119. u8 new_index;
  120. rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
  121. value, 0, buf, 1);
  122. if (rc < 0)
  123. return rc;
  124. new_index = (buf[0] & ~mask) | (index & mask);
  125. if (new_index == buf[0])
  126. return 0;
  127. return tm6000_read_write_usb(dev, USB_DIR_OUT | USB_TYPE_VENDOR,
  128. req, value, new_index, NULL, 0);
  129. }
  130. EXPORT_SYMBOL_GPL(tm6000_set_reg_mask);
  131. int tm6000_get_reg16(struct tm6000_core *dev, u8 req, u16 value, u16 index)
  132. {
  133. int rc;
  134. u8 buf[2];
  135. rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
  136. value, index, buf, 2);
  137. if (rc < 0)
  138. return rc;
  139. return buf[1]|buf[0]<<8;
  140. }
  141. int tm6000_get_reg32(struct tm6000_core *dev, u8 req, u16 value, u16 index)
  142. {
  143. int rc;
  144. u8 buf[4];
  145. rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
  146. value, index, buf, 4);
  147. if (rc < 0)
  148. return rc;
  149. return buf[3] | buf[2] << 8 | buf[1] << 16 | buf[0] << 24;
  150. }
  151. int tm6000_i2c_reset(struct tm6000_core *dev, u16 tsleep)
  152. {
  153. int rc;
  154. rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_CLK, 0);
  155. if (rc < 0)
  156. return rc;
  157. msleep(tsleep);
  158. rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_CLK, 1);
  159. msleep(tsleep);
  160. return rc;
  161. }
  162. void tm6000_set_fourcc_format(struct tm6000_core *dev)
  163. {
  164. if (dev->dev_type == TM6010) {
  165. int val;
  166. val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_IF, 0) & 0xfc;
  167. if (dev->fourcc == V4L2_PIX_FMT_UYVY)
  168. tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_IF, val);
  169. else
  170. tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_IF, val | 1);
  171. } else {
  172. if (dev->fourcc == V4L2_PIX_FMT_UYVY)
  173. tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
  174. else
  175. tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0x90);
  176. }
  177. }
  178. static void tm6000_set_vbi(struct tm6000_core *dev)
  179. {
  180. /*
  181. * FIXME:
  182. * VBI lines and start/end are different between 60Hz and 50Hz
  183. * So, it is very likely that we need to change the config to
  184. * something that takes it into account, doing something different
  185. * if (dev->norm & V4L2_STD_525_60)
  186. */
  187. if (dev->dev_type == TM6010) {
  188. tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
  189. tm6000_set_reg(dev, TM6010_REQ07_R41_TELETEXT_VBI_CODE1, 0x27);
  190. tm6000_set_reg(dev, TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55);
  191. tm6000_set_reg(dev, TM6010_REQ07_R43_VBI_DATA_TYPE_LINE7, 0x66);
  192. tm6000_set_reg(dev, TM6010_REQ07_R44_VBI_DATA_TYPE_LINE8, 0x66);
  193. tm6000_set_reg(dev, TM6010_REQ07_R45_VBI_DATA_TYPE_LINE9, 0x66);
  194. tm6000_set_reg(dev,
  195. TM6010_REQ07_R46_VBI_DATA_TYPE_LINE10, 0x66);
  196. tm6000_set_reg(dev,
  197. TM6010_REQ07_R47_VBI_DATA_TYPE_LINE11, 0x66);
  198. tm6000_set_reg(dev,
  199. TM6010_REQ07_R48_VBI_DATA_TYPE_LINE12, 0x66);
  200. tm6000_set_reg(dev,
  201. TM6010_REQ07_R49_VBI_DATA_TYPE_LINE13, 0x66);
  202. tm6000_set_reg(dev,
  203. TM6010_REQ07_R4A_VBI_DATA_TYPE_LINE14, 0x66);
  204. tm6000_set_reg(dev,
  205. TM6010_REQ07_R4B_VBI_DATA_TYPE_LINE15, 0x66);
  206. tm6000_set_reg(dev,
  207. TM6010_REQ07_R4C_VBI_DATA_TYPE_LINE16, 0x66);
  208. tm6000_set_reg(dev,
  209. TM6010_REQ07_R4D_VBI_DATA_TYPE_LINE17, 0x66);
  210. tm6000_set_reg(dev,
  211. TM6010_REQ07_R4E_VBI_DATA_TYPE_LINE18, 0x66);
  212. tm6000_set_reg(dev,
  213. TM6010_REQ07_R4F_VBI_DATA_TYPE_LINE19, 0x66);
  214. tm6000_set_reg(dev,
  215. TM6010_REQ07_R50_VBI_DATA_TYPE_LINE20, 0x66);
  216. tm6000_set_reg(dev,
  217. TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x66);
  218. tm6000_set_reg(dev,
  219. TM6010_REQ07_R52_VBI_DATA_TYPE_LINE22, 0x66);
  220. tm6000_set_reg(dev,
  221. TM6010_REQ07_R53_VBI_DATA_TYPE_LINE23, 0x00);
  222. tm6000_set_reg(dev,
  223. TM6010_REQ07_R54_VBI_DATA_TYPE_RLINES, 0x00);
  224. tm6000_set_reg(dev,
  225. TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01);
  226. tm6000_set_reg(dev,
  227. TM6010_REQ07_R56_VBI_LOOP_FILTER_I_GAIN, 0x00);
  228. tm6000_set_reg(dev,
  229. TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02);
  230. tm6000_set_reg(dev, TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35);
  231. tm6000_set_reg(dev, TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0);
  232. tm6000_set_reg(dev, TM6010_REQ07_R5A_VBI_TELETEXT_DTO1, 0x11);
  233. tm6000_set_reg(dev, TM6010_REQ07_R5B_VBI_TELETEXT_DTO0, 0x4c);
  234. tm6000_set_reg(dev, TM6010_REQ07_R40_TELETEXT_VBI_CODE0, 0x01);
  235. tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00);
  236. }
  237. }
  238. int tm6000_init_analog_mode(struct tm6000_core *dev)
  239. {
  240. struct v4l2_frequency f;
  241. if (dev->dev_type == TM6010) {
  242. u8 active = TM6010_REQ07_RCC_ACTIVE_IF_AUDIO_ENABLE;
  243. if (!dev->radio)
  244. active |= TM6010_REQ07_RCC_ACTIVE_IF_VIDEO_ENABLE;
  245. /* Enable video and audio */
  246. tm6000_set_reg_mask(dev, TM6010_REQ07_RCC_ACTIVE_IF,
  247. active, 0x60);
  248. /* Disable TS input */
  249. tm6000_set_reg_mask(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE,
  250. 0x00, 0x40);
  251. } else {
  252. /* Enables soft reset */
  253. tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
  254. if (dev->scaler)
  255. /* Disable Hfilter and Enable TS Drop err */
  256. tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x20);
  257. else /* Enable Hfilter and disable TS Drop err */
  258. tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x80);
  259. tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x88);
  260. tm6000_set_reg(dev, TM6000_REQ07_RDA_CLK_SEL, 0x23);
  261. tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xc0);
  262. tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xd8);
  263. tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x06);
  264. tm6000_set_reg(dev, TM6000_REQ07_RDF_PWDOWN_ACLK, 0x1f);
  265. /* AP Software reset */
  266. tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
  267. tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
  268. tm6000_set_fourcc_format(dev);
  269. /* Disables soft reset */
  270. tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00);
  271. }
  272. msleep(20);
  273. /* Tuner firmware can now be loaded */
  274. /*
  275. * FIXME: This is a hack! xc3028 "sleeps" when no channel is detected
  276. * for more than a few seconds. Not sure why, as this behavior does
  277. * not happen on other devices with xc3028. So, I suspect that it
  278. * is yet another bug at tm6000. After start sleeping, decoding
  279. * doesn't start automatically. Instead, it requires some
  280. * I2C commands to wake it up. As we want to have image at the
  281. * beginning, we needed to add this hack. The better would be to
  282. * discover some way to make tm6000 to wake up without this hack.
  283. */
  284. f.frequency = dev->freq;
  285. v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_frequency, &f);
  286. msleep(100);
  287. tm6000_set_standard(dev);
  288. tm6000_set_vbi(dev);
  289. tm6000_set_audio_bitrate(dev, 48000);
  290. /* switch dvb led off */
  291. if (dev->gpio.dvb_led) {
  292. tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
  293. dev->gpio.dvb_led, 0x01);
  294. }
  295. return 0;
  296. }
  297. int tm6000_init_digital_mode(struct tm6000_core *dev)
  298. {
  299. if (dev->dev_type == TM6010) {
  300. /* Disable video and audio */
  301. tm6000_set_reg_mask(dev, TM6010_REQ07_RCC_ACTIVE_IF,
  302. 0x00, 0x60);
  303. /* Enable TS input */
  304. tm6000_set_reg_mask(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE,
  305. 0x40, 0x40);
  306. /* all power down, but not the digital data port */
  307. tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, 0x28);
  308. tm6000_set_reg(dev, TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xfc);
  309. tm6000_set_reg(dev, TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0xff);
  310. } else {
  311. tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
  312. tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
  313. tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
  314. tm6000_set_reg(dev, TM6000_REQ07_RDF_PWDOWN_ACLK, 0x08);
  315. tm6000_set_reg(dev, TM6000_REQ07_RE2_VADC_STATUS_CTL, 0x0c);
  316. tm6000_set_reg(dev, TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0xff);
  317. tm6000_set_reg(dev, TM6000_REQ07_REB_VADC_AADC_MODE, 0xd8);
  318. tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x40);
  319. tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
  320. tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x09);
  321. tm6000_set_reg(dev, TM6000_REQ07_RDA_CLK_SEL, 0x37);
  322. tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xd8);
  323. tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xc0);
  324. tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x60);
  325. tm6000_set_reg(dev, TM6000_REQ07_RE2_VADC_STATUS_CTL, 0x0c);
  326. tm6000_set_reg(dev, TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0xff);
  327. tm6000_set_reg(dev, TM6000_REQ07_REB_VADC_AADC_MODE, 0x08);
  328. msleep(50);
  329. tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
  330. msleep(50);
  331. tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x01);
  332. msleep(50);
  333. tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
  334. msleep(100);
  335. }
  336. /* switch dvb led on */
  337. if (dev->gpio.dvb_led) {
  338. tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
  339. dev->gpio.dvb_led, 0x00);
  340. }
  341. return 0;
  342. }
  343. EXPORT_SYMBOL(tm6000_init_digital_mode);
  344. struct reg_init {
  345. u8 req;
  346. u8 reg;
  347. u8 val;
  348. };
  349. /* The meaning of those initializations are unknown */
  350. static struct reg_init tm6000_init_tab[] = {
  351. /* REG VALUE */
  352. { TM6000_REQ07_RDF_PWDOWN_ACLK, 0x1f },
  353. { TM6010_REQ07_RFF_SOFT_RESET, 0x08 },
  354. { TM6010_REQ07_RFF_SOFT_RESET, 0x00 },
  355. { TM6010_REQ07_RD5_POWERSAVE, 0x4f },
  356. { TM6000_REQ07_RDA_CLK_SEL, 0x23 },
  357. { TM6000_REQ07_RDB_OUT_SEL, 0x08 },
  358. { TM6000_REQ07_RE2_VADC_STATUS_CTL, 0x00 },
  359. { TM6000_REQ07_RE3_VADC_INP_LPF_SEL1, 0x10 },
  360. { TM6000_REQ07_RE5_VADC_INP_LPF_SEL2, 0x00 },
  361. { TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0x00 },
  362. { TM6000_REQ07_REB_VADC_AADC_MODE, 0x64 }, /* 48000 bits/sample, external input */
  363. { TM6000_REQ07_REE_VADC_CTRL_SEL_CONTROL, 0xc2 },
  364. { TM6010_REQ07_R3F_RESET, 0x01 }, /* Start of soft reset */
  365. { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
  366. { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
  367. { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
  368. { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
  369. { TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
  370. { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
  371. { TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
  372. { TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
  373. { TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
  374. { TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
  375. { TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
  376. { TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
  377. { TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
  378. { TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
  379. { TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
  380. { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
  381. { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
  382. { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
  383. { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
  384. { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
  385. { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
  386. { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
  387. { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
  388. { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
  389. { TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
  390. { TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
  391. { TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
  392. { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
  393. { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
  394. { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
  395. { TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
  396. { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
  397. { TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
  398. { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
  399. { TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
  400. { TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
  401. { TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
  402. { TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
  403. { TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
  404. { TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
  405. { TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
  406. { TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
  407. { TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
  408. { TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
  409. { TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
  410. { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
  411. { TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
  412. { TM6010_REQ07_RC3_HSTART1, 0x88 },
  413. { TM6010_REQ07_R3F_RESET, 0x00 }, /* End of the soft reset */
  414. { TM6010_REQ05_R18_IMASK7, 0x00 },
  415. };
  416. static struct reg_init tm6010_init_tab[] = {
  417. { TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x00 },
  418. { TM6010_REQ07_RC4_HSTART0, 0xa0 },
  419. { TM6010_REQ07_RC6_HEND0, 0x40 },
  420. { TM6010_REQ07_RCA_VEND0, 0x31 },
  421. { TM6010_REQ07_RCC_ACTIVE_IF, 0xe1 },
  422. { TM6010_REQ07_RE0_DVIDEO_SOURCE, 0x03 },
  423. { TM6010_REQ07_RFE_POWER_DOWN, 0x7f },
  424. { TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0 },
  425. { TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4 },
  426. { TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8 },
  427. { TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00 },
  428. { TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2 },
  429. { TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0 },
  430. { TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2 },
  431. { TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60 },
  432. { TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc },
  433. { TM6010_REQ07_R3F_RESET, 0x01 },
  434. { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
  435. { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
  436. { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
  437. { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
  438. { TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
  439. { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
  440. { TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
  441. { TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
  442. { TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
  443. { TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
  444. { TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
  445. { TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
  446. { TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
  447. { TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
  448. { TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
  449. { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
  450. { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
  451. { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
  452. { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
  453. { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
  454. { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
  455. { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
  456. { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
  457. { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
  458. { TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
  459. { TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
  460. { TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
  461. { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
  462. { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
  463. { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
  464. { TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
  465. { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
  466. { TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
  467. { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
  468. { TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
  469. { TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
  470. { TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
  471. { TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
  472. { TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
  473. { TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
  474. { TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
  475. { TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
  476. { TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
  477. { TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
  478. { TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
  479. { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
  480. { TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
  481. { TM6010_REQ07_RC3_HSTART1, 0x88 },
  482. { TM6010_REQ07_R3F_RESET, 0x00 },
  483. { TM6010_REQ05_R18_IMASK7, 0x00 },
  484. { TM6010_REQ07_RDC_IR_LEADER1, 0xaa },
  485. { TM6010_REQ07_RDD_IR_LEADER0, 0x30 },
  486. { TM6010_REQ07_RDE_IR_PULSE_CNT1, 0x20 },
  487. { TM6010_REQ07_RDF_IR_PULSE_CNT0, 0xd0 },
  488. { REQ_04_EN_DISABLE_MCU_INT, 0x02, 0x00 },
  489. { TM6010_REQ07_RD8_IR, 0x0f },
  490. /* set remote wakeup key:any key wakeup */
  491. { TM6010_REQ07_RE5_REMOTE_WAKEUP, 0xfe },
  492. { TM6010_REQ07_RDA_IR_WAKEUP_SEL, 0xff },
  493. };
  494. int tm6000_init(struct tm6000_core *dev)
  495. {
  496. int board, rc = 0, i, size;
  497. struct reg_init *tab;
  498. /* Check board revision */
  499. board = tm6000_get_reg32(dev, REQ_40_GET_VERSION, 0, 0);
  500. if (board >= 0) {
  501. switch (board & 0xff) {
  502. case 0xf3:
  503. printk(KERN_INFO "Found tm6000\n");
  504. if (dev->dev_type != TM6000)
  505. dev->dev_type = TM6000;
  506. break;
  507. case 0xf4:
  508. printk(KERN_INFO "Found tm6010\n");
  509. if (dev->dev_type != TM6010)
  510. dev->dev_type = TM6010;
  511. break;
  512. default:
  513. printk(KERN_INFO "Unknown board version = 0x%08x\n", board);
  514. }
  515. } else
  516. printk(KERN_ERR "Error %i while retrieving board version\n", board);
  517. if (dev->dev_type == TM6010) {
  518. tab = tm6010_init_tab;
  519. size = ARRAY_SIZE(tm6010_init_tab);
  520. } else {
  521. tab = tm6000_init_tab;
  522. size = ARRAY_SIZE(tm6000_init_tab);
  523. }
  524. /* Load board's initialization table */
  525. for (i = 0; i < size; i++) {
  526. rc = tm6000_set_reg(dev, tab[i].req, tab[i].reg, tab[i].val);
  527. if (rc < 0) {
  528. printk(KERN_ERR "Error %i while setting req %d, "
  529. "reg %d to value %d\n", rc,
  530. tab[i].req, tab[i].reg, tab[i].val);
  531. return rc;
  532. }
  533. }
  534. msleep(5); /* Just to be conservative */
  535. rc = tm6000_cards_setup(dev);
  536. return rc;
  537. }
  538. int tm6000_set_audio_bitrate(struct tm6000_core *dev, int bitrate)
  539. {
  540. int val = 0;
  541. u8 areg_f0 = 0x60; /* ADC MCLK = 250 Fs */
  542. u8 areg_0a = 0x91; /* SIF 48KHz */
  543. switch (bitrate) {
  544. case 48000:
  545. areg_f0 = 0x60; /* ADC MCLK = 250 Fs */
  546. areg_0a = 0x91; /* SIF 48KHz */
  547. dev->audio_bitrate = bitrate;
  548. break;
  549. case 32000:
  550. areg_f0 = 0x00; /* ADC MCLK = 375 Fs */
  551. areg_0a = 0x90; /* SIF 32KHz */
  552. dev->audio_bitrate = bitrate;
  553. break;
  554. default:
  555. return -EINVAL;
  556. }
  557. /* enable I2S, if we use sif or external I2S device */
  558. if (dev->dev_type == TM6010) {
  559. val = tm6000_set_reg(dev, TM6010_REQ08_R0A_A_I2S_MOD, areg_0a);
  560. if (val < 0)
  561. return val;
  562. val = tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG,
  563. areg_f0, 0xf0);
  564. if (val < 0)
  565. return val;
  566. } else {
  567. val = tm6000_set_reg_mask(dev, TM6000_REQ07_REB_VADC_AADC_MODE,
  568. areg_f0, 0xf0);
  569. if (val < 0)
  570. return val;
  571. }
  572. return 0;
  573. }
  574. EXPORT_SYMBOL_GPL(tm6000_set_audio_bitrate);
  575. int tm6000_set_audio_rinput(struct tm6000_core *dev)
  576. {
  577. if (dev->dev_type == TM6010) {
  578. /* Audio crossbar setting, default SIF1 */
  579. u8 areg_f0;
  580. u8 areg_07 = 0x10;
  581. switch (dev->rinput.amux) {
  582. case TM6000_AMUX_SIF1:
  583. case TM6000_AMUX_SIF2:
  584. areg_f0 = 0x03;
  585. areg_07 = 0x30;
  586. break;
  587. case TM6000_AMUX_ADC1:
  588. areg_f0 = 0x00;
  589. break;
  590. case TM6000_AMUX_ADC2:
  591. areg_f0 = 0x08;
  592. break;
  593. case TM6000_AMUX_I2S:
  594. areg_f0 = 0x04;
  595. break;
  596. default:
  597. printk(KERN_INFO "%s: audio input dosn't support\n",
  598. dev->name);
  599. return 0;
  600. break;
  601. }
  602. /* Set audio input crossbar */
  603. tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG,
  604. areg_f0, 0x0f);
  605. /* Mux overflow workaround */
  606. tm6000_set_reg_mask(dev, TM6010_REQ07_R07_OUTPUT_CONTROL,
  607. areg_07, 0xf0);
  608. } else {
  609. u8 areg_eb;
  610. /* Audio setting, default LINE1 */
  611. switch (dev->rinput.amux) {
  612. case TM6000_AMUX_ADC1:
  613. areg_eb = 0x00;
  614. break;
  615. case TM6000_AMUX_ADC2:
  616. areg_eb = 0x04;
  617. break;
  618. default:
  619. printk(KERN_INFO "%s: audio input dosn't support\n",
  620. dev->name);
  621. return 0;
  622. break;
  623. }
  624. /* Set audio input */
  625. tm6000_set_reg_mask(dev, TM6000_REQ07_REB_VADC_AADC_MODE,
  626. areg_eb, 0x0f);
  627. }
  628. return 0;
  629. }
  630. static void tm6010_set_mute_sif(struct tm6000_core *dev, u8 mute)
  631. {
  632. u8 mute_reg = 0;
  633. if (mute)
  634. mute_reg = 0x08;
  635. tm6000_set_reg_mask(dev, TM6010_REQ08_R0A_A_I2S_MOD, mute_reg, 0x08);
  636. }
  637. static void tm6010_set_mute_adc(struct tm6000_core *dev, u8 mute)
  638. {
  639. u8 mute_reg = 0;
  640. if (mute)
  641. mute_reg = 0x20;
  642. if (dev->dev_type == TM6010) {
  643. tm6000_set_reg_mask(dev, TM6010_REQ08_RF2_LEFT_CHANNEL_VOL,
  644. mute_reg, 0x20);
  645. tm6000_set_reg_mask(dev, TM6010_REQ08_RF3_RIGHT_CHANNEL_VOL,
  646. mute_reg, 0x20);
  647. } else {
  648. tm6000_set_reg_mask(dev, TM6000_REQ07_REC_VADC_AADC_LVOL,
  649. mute_reg, 0x20);
  650. tm6000_set_reg_mask(dev, TM6000_REQ07_RED_VADC_AADC_RVOL,
  651. mute_reg, 0x20);
  652. }
  653. }
  654. int tm6000_tvaudio_set_mute(struct tm6000_core *dev, u8 mute)
  655. {
  656. enum tm6000_mux mux;
  657. if (dev->radio)
  658. mux = dev->rinput.amux;
  659. else
  660. mux = dev->vinput[dev->input].amux;
  661. switch (mux) {
  662. case TM6000_AMUX_SIF1:
  663. case TM6000_AMUX_SIF2:
  664. if (dev->dev_type == TM6010)
  665. tm6010_set_mute_sif(dev, mute);
  666. else {
  667. printk(KERN_INFO "ERROR: TM5600 and TM6000 don't has"
  668. " SIF audio inputs. Please check the %s"
  669. " configuration.\n", dev->name);
  670. return -EINVAL;
  671. }
  672. break;
  673. case TM6000_AMUX_ADC1:
  674. case TM6000_AMUX_ADC2:
  675. tm6010_set_mute_adc(dev, mute);
  676. break;
  677. default:
  678. return -EINVAL;
  679. break;
  680. }
  681. return 0;
  682. }
  683. static void tm6010_set_volume_sif(struct tm6000_core *dev, int vol)
  684. {
  685. u8 vol_reg;
  686. vol_reg = vol & 0x0F;
  687. if (vol < 0)
  688. vol_reg |= 0x40;
  689. tm6000_set_reg(dev, TM6010_REQ08_R07_A_LEFT_VOL, vol_reg);
  690. tm6000_set_reg(dev, TM6010_REQ08_R08_A_RIGHT_VOL, vol_reg);
  691. }
  692. static void tm6010_set_volume_adc(struct tm6000_core *dev, int vol)
  693. {
  694. u8 vol_reg;
  695. vol_reg = (vol + 0x10) & 0x1f;
  696. if (dev->dev_type == TM6010) {
  697. tm6000_set_reg(dev, TM6010_REQ08_RF2_LEFT_CHANNEL_VOL, vol_reg);
  698. tm6000_set_reg(dev, TM6010_REQ08_RF3_RIGHT_CHANNEL_VOL, vol_reg);
  699. } else {
  700. tm6000_set_reg(dev, TM6000_REQ07_REC_VADC_AADC_LVOL, vol_reg);
  701. tm6000_set_reg(dev, TM6000_REQ07_RED_VADC_AADC_RVOL, vol_reg);
  702. }
  703. }
  704. void tm6000_set_volume(struct tm6000_core *dev, int vol)
  705. {
  706. enum tm6000_mux mux;
  707. if (dev->radio) {
  708. mux = dev->rinput.amux;
  709. vol += 8; /* Offset to 0 dB */
  710. } else
  711. mux = dev->vinput[dev->input].amux;
  712. switch (mux) {
  713. case TM6000_AMUX_SIF1:
  714. case TM6000_AMUX_SIF2:
  715. if (dev->dev_type == TM6010)
  716. tm6010_set_volume_sif(dev, vol);
  717. else
  718. printk(KERN_INFO "ERROR: TM5600 and TM6000 don't has"
  719. " SIF audio inputs. Please check the %s"
  720. " configuration.\n", dev->name);
  721. break;
  722. case TM6000_AMUX_ADC1:
  723. case TM6000_AMUX_ADC2:
  724. tm6010_set_volume_adc(dev, vol);
  725. break;
  726. default:
  727. break;
  728. }
  729. }
  730. static LIST_HEAD(tm6000_devlist);
  731. static DEFINE_MUTEX(tm6000_devlist_mutex);
  732. /*
  733. * tm6000_realease_resource()
  734. */
  735. void tm6000_remove_from_devlist(struct tm6000_core *dev)
  736. {
  737. mutex_lock(&tm6000_devlist_mutex);
  738. list_del(&dev->devlist);
  739. mutex_unlock(&tm6000_devlist_mutex);
  740. };
  741. void tm6000_add_into_devlist(struct tm6000_core *dev)
  742. {
  743. mutex_lock(&tm6000_devlist_mutex);
  744. list_add_tail(&dev->devlist, &tm6000_devlist);
  745. mutex_unlock(&tm6000_devlist_mutex);
  746. };
  747. /*
  748. * Extension interface
  749. */
  750. static LIST_HEAD(tm6000_extension_devlist);
  751. int tm6000_call_fillbuf(struct tm6000_core *dev, enum tm6000_ops_type type,
  752. char *buf, int size)
  753. {
  754. struct tm6000_ops *ops = NULL;
  755. /* FIXME: tm6000_extension_devlist_lock should be a spinlock */
  756. if (!list_empty(&tm6000_extension_devlist)) {
  757. list_for_each_entry(ops, &tm6000_extension_devlist, next) {
  758. if (ops->fillbuf && ops->type == type)
  759. ops->fillbuf(dev, buf, size);
  760. }
  761. }
  762. return 0;
  763. }
  764. int tm6000_register_extension(struct tm6000_ops *ops)
  765. {
  766. struct tm6000_core *dev = NULL;
  767. mutex_lock(&tm6000_devlist_mutex);
  768. list_add_tail(&ops->next, &tm6000_extension_devlist);
  769. list_for_each_entry(dev, &tm6000_devlist, devlist) {
  770. ops->init(dev);
  771. printk(KERN_INFO "%s: Initialized (%s) extension\n",
  772. dev->name, ops->name);
  773. }
  774. mutex_unlock(&tm6000_devlist_mutex);
  775. return 0;
  776. }
  777. EXPORT_SYMBOL(tm6000_register_extension);
  778. void tm6000_unregister_extension(struct tm6000_ops *ops)
  779. {
  780. struct tm6000_core *dev = NULL;
  781. mutex_lock(&tm6000_devlist_mutex);
  782. list_for_each_entry(dev, &tm6000_devlist, devlist)
  783. ops->fini(dev);
  784. printk(KERN_INFO "tm6000: Remove (%s) extension\n", ops->name);
  785. list_del(&ops->next);
  786. mutex_unlock(&tm6000_devlist_mutex);
  787. }
  788. EXPORT_SYMBOL(tm6000_unregister_extension);
  789. void tm6000_init_extension(struct tm6000_core *dev)
  790. {
  791. struct tm6000_ops *ops = NULL;
  792. mutex_lock(&tm6000_devlist_mutex);
  793. if (!list_empty(&tm6000_extension_devlist)) {
  794. list_for_each_entry(ops, &tm6000_extension_devlist, next) {
  795. if (ops->init)
  796. ops->init(dev);
  797. }
  798. }
  799. mutex_unlock(&tm6000_devlist_mutex);
  800. }
  801. void tm6000_close_extension(struct tm6000_core *dev)
  802. {
  803. struct tm6000_ops *ops = NULL;
  804. mutex_lock(&tm6000_devlist_mutex);
  805. if (!list_empty(&tm6000_extension_devlist)) {
  806. list_for_each_entry(ops, &tm6000_extension_devlist, next) {
  807. if (ops->fini)
  808. ops->fini(dev);
  809. }
  810. }
  811. mutex_unlock(&tm6000_devlist_mutex);
  812. }