88pm800.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633
  1. /*
  2. * Base driver for Marvell 88PM800
  3. *
  4. * Copyright (C) 2012 Marvell International Ltd.
  5. * Haojian Zhuang <haojian.zhuang@marvell.com>
  6. * Joseph(Yossi) Hanin <yhanin@marvell.com>
  7. * Qiao Zhou <zhouqiao@marvell.com>
  8. *
  9. * This file is subject to the terms and conditions of the GNU General
  10. * Public License. See the file "COPYING" in the main directory of this
  11. * archive for more details.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <linux/kernel.h>
  23. #include <linux/module.h>
  24. #include <linux/err.h>
  25. #include <linux/i2c.h>
  26. #include <linux/mfd/core.h>
  27. #include <linux/mfd/88pm80x.h>
  28. #include <linux/slab.h>
  29. /* Interrupt Registers */
  30. #define PM800_INT_STATUS1 (0x05)
  31. #define PM800_ONKEY_INT_STS1 (1 << 0)
  32. #define PM800_EXTON_INT_STS1 (1 << 1)
  33. #define PM800_CHG_INT_STS1 (1 << 2)
  34. #define PM800_BAT_INT_STS1 (1 << 3)
  35. #define PM800_RTC_INT_STS1 (1 << 4)
  36. #define PM800_CLASSD_OC_INT_STS1 (1 << 5)
  37. #define PM800_INT_STATUS2 (0x06)
  38. #define PM800_VBAT_INT_STS2 (1 << 0)
  39. #define PM800_VSYS_INT_STS2 (1 << 1)
  40. #define PM800_VCHG_INT_STS2 (1 << 2)
  41. #define PM800_TINT_INT_STS2 (1 << 3)
  42. #define PM800_GPADC0_INT_STS2 (1 << 4)
  43. #define PM800_TBAT_INT_STS2 (1 << 5)
  44. #define PM800_GPADC2_INT_STS2 (1 << 6)
  45. #define PM800_GPADC3_INT_STS2 (1 << 7)
  46. #define PM800_INT_STATUS3 (0x07)
  47. #define PM800_INT_STATUS4 (0x08)
  48. #define PM800_GPIO0_INT_STS4 (1 << 0)
  49. #define PM800_GPIO1_INT_STS4 (1 << 1)
  50. #define PM800_GPIO2_INT_STS4 (1 << 2)
  51. #define PM800_GPIO3_INT_STS4 (1 << 3)
  52. #define PM800_GPIO4_INT_STS4 (1 << 4)
  53. #define PM800_INT_ENA_1 (0x09)
  54. #define PM800_ONKEY_INT_ENA1 (1 << 0)
  55. #define PM800_EXTON_INT_ENA1 (1 << 1)
  56. #define PM800_CHG_INT_ENA1 (1 << 2)
  57. #define PM800_BAT_INT_ENA1 (1 << 3)
  58. #define PM800_RTC_INT_ENA1 (1 << 4)
  59. #define PM800_CLASSD_OC_INT_ENA1 (1 << 5)
  60. #define PM800_INT_ENA_2 (0x0A)
  61. #define PM800_VBAT_INT_ENA2 (1 << 0)
  62. #define PM800_VSYS_INT_ENA2 (1 << 1)
  63. #define PM800_VCHG_INT_ENA2 (1 << 2)
  64. #define PM800_TINT_INT_ENA2 (1 << 3)
  65. #define PM800_INT_ENA_3 (0x0B)
  66. #define PM800_GPADC0_INT_ENA3 (1 << 0)
  67. #define PM800_GPADC1_INT_ENA3 (1 << 1)
  68. #define PM800_GPADC2_INT_ENA3 (1 << 2)
  69. #define PM800_GPADC3_INT_ENA3 (1 << 3)
  70. #define PM800_GPADC4_INT_ENA3 (1 << 4)
  71. #define PM800_INT_ENA_4 (0x0C)
  72. #define PM800_GPIO0_INT_ENA4 (1 << 0)
  73. #define PM800_GPIO1_INT_ENA4 (1 << 1)
  74. #define PM800_GPIO2_INT_ENA4 (1 << 2)
  75. #define PM800_GPIO3_INT_ENA4 (1 << 3)
  76. #define PM800_GPIO4_INT_ENA4 (1 << 4)
  77. /* number of INT_ENA & INT_STATUS regs */
  78. #define PM800_INT_REG_NUM (4)
  79. /* Interrupt Number in 88PM800 */
  80. enum {
  81. PM800_IRQ_ONKEY, /*EN1b0 *//*0 */
  82. PM800_IRQ_EXTON, /*EN1b1 */
  83. PM800_IRQ_CHG, /*EN1b2 */
  84. PM800_IRQ_BAT, /*EN1b3 */
  85. PM800_IRQ_RTC, /*EN1b4 */
  86. PM800_IRQ_CLASSD, /*EN1b5 *//*5 */
  87. PM800_IRQ_VBAT, /*EN2b0 */
  88. PM800_IRQ_VSYS, /*EN2b1 */
  89. PM800_IRQ_VCHG, /*EN2b2 */
  90. PM800_IRQ_TINT, /*EN2b3 */
  91. PM800_IRQ_GPADC0, /*EN3b0 *//*10 */
  92. PM800_IRQ_GPADC1, /*EN3b1 */
  93. PM800_IRQ_GPADC2, /*EN3b2 */
  94. PM800_IRQ_GPADC3, /*EN3b3 */
  95. PM800_IRQ_GPADC4, /*EN3b4 */
  96. PM800_IRQ_GPIO0, /*EN4b0 *//*15 */
  97. PM800_IRQ_GPIO1, /*EN4b1 */
  98. PM800_IRQ_GPIO2, /*EN4b2 */
  99. PM800_IRQ_GPIO3, /*EN4b3 */
  100. PM800_IRQ_GPIO4, /*EN4b4 *//*19 */
  101. PM800_MAX_IRQ,
  102. };
  103. /* PM800: generation identification number */
  104. #define PM800_CHIP_GEN_ID_NUM 0x3
  105. static const struct i2c_device_id pm80x_id_table[] = {
  106. {"88PM800", 0},
  107. {} /* NULL terminated */
  108. };
  109. MODULE_DEVICE_TABLE(i2c, pm80x_id_table);
  110. static struct resource rtc_resources[] = {
  111. {
  112. .name = "88pm80x-rtc",
  113. .start = PM800_IRQ_RTC,
  114. .end = PM800_IRQ_RTC,
  115. .flags = IORESOURCE_IRQ,
  116. },
  117. };
  118. static struct mfd_cell rtc_devs[] = {
  119. {
  120. .name = "88pm80x-rtc",
  121. .num_resources = ARRAY_SIZE(rtc_resources),
  122. .resources = &rtc_resources[0],
  123. .id = -1,
  124. },
  125. };
  126. static struct resource onkey_resources[] = {
  127. {
  128. .name = "88pm80x-onkey",
  129. .start = PM800_IRQ_ONKEY,
  130. .end = PM800_IRQ_ONKEY,
  131. .flags = IORESOURCE_IRQ,
  132. },
  133. };
  134. static const struct mfd_cell onkey_devs[] = {
  135. {
  136. .name = "88pm80x-onkey",
  137. .num_resources = 1,
  138. .resources = &onkey_resources[0],
  139. .id = -1,
  140. },
  141. };
  142. static const struct mfd_cell regulator_devs[] = {
  143. {
  144. .name = "88pm80x-regulator",
  145. .id = -1,
  146. },
  147. };
  148. static const struct regmap_irq pm800_irqs[] = {
  149. /* INT0 */
  150. [PM800_IRQ_ONKEY] = {
  151. .mask = PM800_ONKEY_INT_ENA1,
  152. },
  153. [PM800_IRQ_EXTON] = {
  154. .mask = PM800_EXTON_INT_ENA1,
  155. },
  156. [PM800_IRQ_CHG] = {
  157. .mask = PM800_CHG_INT_ENA1,
  158. },
  159. [PM800_IRQ_BAT] = {
  160. .mask = PM800_BAT_INT_ENA1,
  161. },
  162. [PM800_IRQ_RTC] = {
  163. .mask = PM800_RTC_INT_ENA1,
  164. },
  165. [PM800_IRQ_CLASSD] = {
  166. .mask = PM800_CLASSD_OC_INT_ENA1,
  167. },
  168. /* INT1 */
  169. [PM800_IRQ_VBAT] = {
  170. .reg_offset = 1,
  171. .mask = PM800_VBAT_INT_ENA2,
  172. },
  173. [PM800_IRQ_VSYS] = {
  174. .reg_offset = 1,
  175. .mask = PM800_VSYS_INT_ENA2,
  176. },
  177. [PM800_IRQ_VCHG] = {
  178. .reg_offset = 1,
  179. .mask = PM800_VCHG_INT_ENA2,
  180. },
  181. [PM800_IRQ_TINT] = {
  182. .reg_offset = 1,
  183. .mask = PM800_TINT_INT_ENA2,
  184. },
  185. /* INT2 */
  186. [PM800_IRQ_GPADC0] = {
  187. .reg_offset = 2,
  188. .mask = PM800_GPADC0_INT_ENA3,
  189. },
  190. [PM800_IRQ_GPADC1] = {
  191. .reg_offset = 2,
  192. .mask = PM800_GPADC1_INT_ENA3,
  193. },
  194. [PM800_IRQ_GPADC2] = {
  195. .reg_offset = 2,
  196. .mask = PM800_GPADC2_INT_ENA3,
  197. },
  198. [PM800_IRQ_GPADC3] = {
  199. .reg_offset = 2,
  200. .mask = PM800_GPADC3_INT_ENA3,
  201. },
  202. [PM800_IRQ_GPADC4] = {
  203. .reg_offset = 2,
  204. .mask = PM800_GPADC4_INT_ENA3,
  205. },
  206. /* INT3 */
  207. [PM800_IRQ_GPIO0] = {
  208. .reg_offset = 3,
  209. .mask = PM800_GPIO0_INT_ENA4,
  210. },
  211. [PM800_IRQ_GPIO1] = {
  212. .reg_offset = 3,
  213. .mask = PM800_GPIO1_INT_ENA4,
  214. },
  215. [PM800_IRQ_GPIO2] = {
  216. .reg_offset = 3,
  217. .mask = PM800_GPIO2_INT_ENA4,
  218. },
  219. [PM800_IRQ_GPIO3] = {
  220. .reg_offset = 3,
  221. .mask = PM800_GPIO3_INT_ENA4,
  222. },
  223. [PM800_IRQ_GPIO4] = {
  224. .reg_offset = 3,
  225. .mask = PM800_GPIO4_INT_ENA4,
  226. },
  227. };
  228. static int device_gpadc_init(struct pm80x_chip *chip,
  229. struct pm80x_platform_data *pdata)
  230. {
  231. struct pm80x_subchip *subchip = chip->subchip;
  232. struct regmap *map = subchip->regmap_gpadc;
  233. int data = 0, mask = 0, ret = 0;
  234. if (!map) {
  235. dev_warn(chip->dev,
  236. "Warning: gpadc regmap is not available!\n");
  237. return -EINVAL;
  238. }
  239. /*
  240. * initialize GPADC without activating it turn on GPADC
  241. * measurments
  242. */
  243. ret = regmap_update_bits(map,
  244. PM800_GPADC_MISC_CONFIG2,
  245. PM800_GPADC_MISC_GPFSM_EN,
  246. PM800_GPADC_MISC_GPFSM_EN);
  247. if (ret < 0)
  248. goto out;
  249. /*
  250. * This function configures the ADC as requires for
  251. * CP implementation.CP does not "own" the ADC configuration
  252. * registers and relies on AP.
  253. * Reason: enable automatic ADC measurements needed
  254. * for CP to get VBAT and RF temperature readings.
  255. */
  256. ret = regmap_update_bits(map, PM800_GPADC_MEAS_EN1,
  257. PM800_MEAS_EN1_VBAT, PM800_MEAS_EN1_VBAT);
  258. if (ret < 0)
  259. goto out;
  260. ret = regmap_update_bits(map, PM800_GPADC_MEAS_EN2,
  261. (PM800_MEAS_EN2_RFTMP | PM800_MEAS_GP0_EN),
  262. (PM800_MEAS_EN2_RFTMP | PM800_MEAS_GP0_EN));
  263. if (ret < 0)
  264. goto out;
  265. /*
  266. * the defult of PM800 is GPADC operates at 100Ks/s rate
  267. * and Number of GPADC slots with active current bias prior
  268. * to GPADC sampling = 1 slot for all GPADCs set for
  269. * Temprature mesurmants
  270. */
  271. mask = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN1 |
  272. PM800_GPADC_GP_BIAS_EN2 | PM800_GPADC_GP_BIAS_EN3);
  273. if (pdata && (pdata->batt_det == 0))
  274. data = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN1 |
  275. PM800_GPADC_GP_BIAS_EN2 | PM800_GPADC_GP_BIAS_EN3);
  276. else
  277. data = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN2 |
  278. PM800_GPADC_GP_BIAS_EN3);
  279. ret = regmap_update_bits(map, PM800_GP_BIAS_ENA1, mask, data);
  280. if (ret < 0)
  281. goto out;
  282. dev_info(chip->dev, "pm800 device_gpadc_init: Done\n");
  283. return 0;
  284. out:
  285. dev_info(chip->dev, "pm800 device_gpadc_init: Failed!\n");
  286. return ret;
  287. }
  288. static int device_onkey_init(struct pm80x_chip *chip,
  289. struct pm80x_platform_data *pdata)
  290. {
  291. int ret;
  292. ret = mfd_add_devices(chip->dev, 0, &onkey_devs[0],
  293. ARRAY_SIZE(onkey_devs), &onkey_resources[0], 0,
  294. NULL);
  295. if (ret) {
  296. dev_err(chip->dev, "Failed to add onkey subdev\n");
  297. return ret;
  298. }
  299. return 0;
  300. }
  301. static int device_rtc_init(struct pm80x_chip *chip,
  302. struct pm80x_platform_data *pdata)
  303. {
  304. int ret;
  305. if (pdata) {
  306. rtc_devs[0].platform_data = pdata->rtc;
  307. rtc_devs[0].pdata_size =
  308. pdata->rtc ? sizeof(struct pm80x_rtc_pdata) : 0;
  309. }
  310. ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0],
  311. ARRAY_SIZE(rtc_devs), NULL, 0, NULL);
  312. if (ret) {
  313. dev_err(chip->dev, "Failed to add rtc subdev\n");
  314. return ret;
  315. }
  316. return 0;
  317. }
  318. static int device_regulator_init(struct pm80x_chip *chip,
  319. struct pm80x_platform_data *pdata)
  320. {
  321. int ret;
  322. ret = mfd_add_devices(chip->dev, 0, &regulator_devs[0],
  323. ARRAY_SIZE(regulator_devs), NULL, 0, NULL);
  324. if (ret) {
  325. dev_err(chip->dev, "Failed to add regulator subdev\n");
  326. return ret;
  327. }
  328. return 0;
  329. }
  330. static int device_irq_init_800(struct pm80x_chip *chip)
  331. {
  332. struct regmap *map = chip->regmap;
  333. unsigned long flags = IRQF_ONESHOT;
  334. int data, mask, ret = -EINVAL;
  335. if (!map || !chip->irq) {
  336. dev_err(chip->dev, "incorrect parameters\n");
  337. return -EINVAL;
  338. }
  339. /*
  340. * irq_mode defines the way of clearing interrupt. it's read-clear by
  341. * default.
  342. */
  343. mask =
  344. PM800_WAKEUP2_INV_INT | PM800_WAKEUP2_INT_CLEAR |
  345. PM800_WAKEUP2_INT_MASK;
  346. data = PM800_WAKEUP2_INT_CLEAR;
  347. ret = regmap_update_bits(map, PM800_WAKEUP2, mask, data);
  348. if (ret < 0)
  349. goto out;
  350. ret =
  351. regmap_add_irq_chip(chip->regmap, chip->irq, flags, -1,
  352. chip->regmap_irq_chip, &chip->irq_data);
  353. out:
  354. return ret;
  355. }
  356. static void device_irq_exit_800(struct pm80x_chip *chip)
  357. {
  358. regmap_del_irq_chip(chip->irq, chip->irq_data);
  359. }
  360. static struct regmap_irq_chip pm800_irq_chip = {
  361. .name = "88pm800",
  362. .irqs = pm800_irqs,
  363. .num_irqs = ARRAY_SIZE(pm800_irqs),
  364. .num_regs = 4,
  365. .status_base = PM800_INT_STATUS1,
  366. .mask_base = PM800_INT_ENA_1,
  367. .ack_base = PM800_INT_STATUS1,
  368. .mask_invert = 1,
  369. };
  370. static int pm800_pages_init(struct pm80x_chip *chip)
  371. {
  372. struct pm80x_subchip *subchip;
  373. struct i2c_client *client = chip->client;
  374. int ret = 0;
  375. subchip = chip->subchip;
  376. if (!subchip || !subchip->power_page_addr || !subchip->gpadc_page_addr)
  377. return -ENODEV;
  378. /* PM800 block power page */
  379. subchip->power_page = i2c_new_dummy(client->adapter,
  380. subchip->power_page_addr);
  381. if (subchip->power_page == NULL) {
  382. ret = -ENODEV;
  383. goto out;
  384. }
  385. subchip->regmap_power = devm_regmap_init_i2c(subchip->power_page,
  386. &pm80x_regmap_config);
  387. if (IS_ERR(subchip->regmap_power)) {
  388. ret = PTR_ERR(subchip->regmap_power);
  389. dev_err(chip->dev,
  390. "Failed to allocate regmap_power: %d\n", ret);
  391. goto out;
  392. }
  393. i2c_set_clientdata(subchip->power_page, chip);
  394. /* PM800 block GPADC */
  395. subchip->gpadc_page = i2c_new_dummy(client->adapter,
  396. subchip->gpadc_page_addr);
  397. if (subchip->gpadc_page == NULL) {
  398. ret = -ENODEV;
  399. goto out;
  400. }
  401. subchip->regmap_gpadc = devm_regmap_init_i2c(subchip->gpadc_page,
  402. &pm80x_regmap_config);
  403. if (IS_ERR(subchip->regmap_gpadc)) {
  404. ret = PTR_ERR(subchip->regmap_gpadc);
  405. dev_err(chip->dev,
  406. "Failed to allocate regmap_gpadc: %d\n", ret);
  407. goto out;
  408. }
  409. i2c_set_clientdata(subchip->gpadc_page, chip);
  410. out:
  411. return ret;
  412. }
  413. static void pm800_pages_exit(struct pm80x_chip *chip)
  414. {
  415. struct pm80x_subchip *subchip;
  416. subchip = chip->subchip;
  417. if (subchip && subchip->power_page)
  418. i2c_unregister_device(subchip->power_page);
  419. if (subchip && subchip->gpadc_page)
  420. i2c_unregister_device(subchip->gpadc_page);
  421. }
  422. static int device_800_init(struct pm80x_chip *chip,
  423. struct pm80x_platform_data *pdata)
  424. {
  425. int ret;
  426. unsigned int val;
  427. /*
  428. * alarm wake up bit will be clear in device_irq_init(),
  429. * read before that
  430. */
  431. ret = regmap_read(chip->regmap, PM800_RTC_CONTROL, &val);
  432. if (ret < 0) {
  433. dev_err(chip->dev, "Failed to read RTC register: %d\n", ret);
  434. goto out;
  435. }
  436. if (val & PM800_ALARM_WAKEUP) {
  437. if (pdata && pdata->rtc)
  438. pdata->rtc->rtc_wakeup = 1;
  439. }
  440. ret = device_gpadc_init(chip, pdata);
  441. if (ret < 0) {
  442. dev_err(chip->dev, "[%s]Failed to init gpadc\n", __func__);
  443. goto out;
  444. }
  445. chip->regmap_irq_chip = &pm800_irq_chip;
  446. ret = device_irq_init_800(chip);
  447. if (ret < 0) {
  448. dev_err(chip->dev, "[%s]Failed to init pm800 irq\n", __func__);
  449. goto out;
  450. }
  451. ret = device_onkey_init(chip, pdata);
  452. if (ret) {
  453. dev_err(chip->dev, "Failed to add onkey subdev\n");
  454. goto out_dev;
  455. }
  456. ret = device_rtc_init(chip, pdata);
  457. if (ret) {
  458. dev_err(chip->dev, "Failed to add rtc subdev\n");
  459. goto out;
  460. }
  461. ret = device_regulator_init(chip, pdata);
  462. if (ret) {
  463. dev_err(chip->dev, "Failed to add regulators subdev\n");
  464. goto out;
  465. }
  466. return 0;
  467. out_dev:
  468. mfd_remove_devices(chip->dev);
  469. device_irq_exit_800(chip);
  470. out:
  471. return ret;
  472. }
  473. static int pm800_probe(struct i2c_client *client,
  474. const struct i2c_device_id *id)
  475. {
  476. int ret = 0;
  477. struct pm80x_chip *chip;
  478. struct pm80x_platform_data *pdata = dev_get_platdata(&client->dev);
  479. struct pm80x_subchip *subchip;
  480. ret = pm80x_init(client);
  481. if (ret) {
  482. dev_err(&client->dev, "pm800_init fail\n");
  483. goto out_init;
  484. }
  485. chip = i2c_get_clientdata(client);
  486. /* init subchip for PM800 */
  487. subchip =
  488. devm_kzalloc(&client->dev, sizeof(struct pm80x_subchip),
  489. GFP_KERNEL);
  490. if (!subchip) {
  491. ret = -ENOMEM;
  492. goto err_subchip_alloc;
  493. }
  494. /* pm800 has 2 addtional pages to support power and gpadc. */
  495. subchip->power_page_addr = client->addr + 1;
  496. subchip->gpadc_page_addr = client->addr + 2;
  497. chip->subchip = subchip;
  498. ret = pm800_pages_init(chip);
  499. if (ret) {
  500. dev_err(&client->dev, "pm800_pages_init failed!\n");
  501. goto err_device_init;
  502. }
  503. ret = device_800_init(chip, pdata);
  504. if (ret) {
  505. dev_err(chip->dev, "Failed to initialize 88pm800 devices\n");
  506. goto err_device_init;
  507. }
  508. if (pdata && pdata->plat_config)
  509. pdata->plat_config(chip, pdata);
  510. return 0;
  511. err_device_init:
  512. pm800_pages_exit(chip);
  513. err_subchip_alloc:
  514. pm80x_deinit();
  515. out_init:
  516. return ret;
  517. }
  518. static int pm800_remove(struct i2c_client *client)
  519. {
  520. struct pm80x_chip *chip = i2c_get_clientdata(client);
  521. mfd_remove_devices(chip->dev);
  522. device_irq_exit_800(chip);
  523. pm800_pages_exit(chip);
  524. pm80x_deinit();
  525. return 0;
  526. }
  527. static struct i2c_driver pm800_driver = {
  528. .driver = {
  529. .name = "88PM800",
  530. .pm = &pm80x_pm_ops,
  531. },
  532. .probe = pm800_probe,
  533. .remove = pm800_remove,
  534. .id_table = pm80x_id_table,
  535. };
  536. static int __init pm800_i2c_init(void)
  537. {
  538. return i2c_add_driver(&pm800_driver);
  539. }
  540. subsys_initcall(pm800_i2c_init);
  541. static void __exit pm800_i2c_exit(void)
  542. {
  543. i2c_del_driver(&pm800_driver);
  544. }
  545. module_exit(pm800_i2c_exit);
  546. MODULE_DESCRIPTION("PMIC Driver for Marvell 88PM800");
  547. MODULE_AUTHOR("Qiao Zhou <zhouqiao@marvell.com>");
  548. MODULE_LICENSE("GPL");