tps65912-irq.c 6.0 KB

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  1. /*
  2. * tps65912-irq.c -- TI TPS6591x
  3. *
  4. * Copyright 2011 Texas Instruments Inc.
  5. *
  6. * Author: Margarita Olaya <magi@slimlogic.co.uk>
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. * This driver is based on wm8350 implementation.
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/bug.h>
  18. #include <linux/device.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/irq.h>
  21. #include <linux/gpio.h>
  22. #include <linux/mfd/tps65912.h>
  23. static inline int irq_to_tps65912_irq(struct tps65912 *tps65912,
  24. int irq)
  25. {
  26. return irq - tps65912->irq_base;
  27. }
  28. /*
  29. * This is a threaded IRQ handler so can access I2C/SPI. Since the
  30. * IRQ handler explicitly clears the IRQ it handles the IRQ line
  31. * will be reasserted and the physical IRQ will be handled again if
  32. * another interrupt is asserted while we run - in the normal course
  33. * of events this is a rare occurrence so we save I2C/SPI reads. We're
  34. * also assuming that it's rare to get lots of interrupts firing
  35. * simultaneously so try to minimise I/O.
  36. */
  37. static irqreturn_t tps65912_irq(int irq, void *irq_data)
  38. {
  39. struct tps65912 *tps65912 = irq_data;
  40. u32 irq_sts;
  41. u32 irq_mask;
  42. u8 reg;
  43. int i;
  44. tps65912->read(tps65912, TPS65912_INT_STS, 1, &reg);
  45. irq_sts = reg;
  46. tps65912->read(tps65912, TPS65912_INT_STS2, 1, &reg);
  47. irq_sts |= reg << 8;
  48. tps65912->read(tps65912, TPS65912_INT_STS3, 1, &reg);
  49. irq_sts |= reg << 16;
  50. tps65912->read(tps65912, TPS65912_INT_STS4, 1, &reg);
  51. irq_sts |= reg << 24;
  52. tps65912->read(tps65912, TPS65912_INT_MSK, 1, &reg);
  53. irq_mask = reg;
  54. tps65912->read(tps65912, TPS65912_INT_MSK2, 1, &reg);
  55. irq_mask |= reg << 8;
  56. tps65912->read(tps65912, TPS65912_INT_MSK3, 1, &reg);
  57. irq_mask |= reg << 16;
  58. tps65912->read(tps65912, TPS65912_INT_MSK4, 1, &reg);
  59. irq_mask |= reg << 24;
  60. irq_sts &= ~irq_mask;
  61. if (!irq_sts)
  62. return IRQ_NONE;
  63. for (i = 0; i < tps65912->irq_num; i++) {
  64. if (!(irq_sts & (1 << i)))
  65. continue;
  66. handle_nested_irq(tps65912->irq_base + i);
  67. }
  68. /* Write the STS register back to clear IRQs we handled */
  69. reg = irq_sts & 0xFF;
  70. irq_sts >>= 8;
  71. if (reg)
  72. tps65912->write(tps65912, TPS65912_INT_STS, 1, &reg);
  73. reg = irq_sts & 0xFF;
  74. irq_sts >>= 8;
  75. if (reg)
  76. tps65912->write(tps65912, TPS65912_INT_STS2, 1, &reg);
  77. reg = irq_sts & 0xFF;
  78. irq_sts >>= 8;
  79. if (reg)
  80. tps65912->write(tps65912, TPS65912_INT_STS3, 1, &reg);
  81. reg = irq_sts & 0xFF;
  82. if (reg)
  83. tps65912->write(tps65912, TPS65912_INT_STS4, 1, &reg);
  84. return IRQ_HANDLED;
  85. }
  86. static void tps65912_irq_lock(struct irq_data *data)
  87. {
  88. struct tps65912 *tps65912 = irq_data_get_irq_chip_data(data);
  89. mutex_lock(&tps65912->irq_lock);
  90. }
  91. static void tps65912_irq_sync_unlock(struct irq_data *data)
  92. {
  93. struct tps65912 *tps65912 = irq_data_get_irq_chip_data(data);
  94. u32 reg_mask;
  95. u8 reg;
  96. tps65912->read(tps65912, TPS65912_INT_MSK, 1, &reg);
  97. reg_mask = reg;
  98. tps65912->read(tps65912, TPS65912_INT_MSK2, 1, &reg);
  99. reg_mask |= reg << 8;
  100. tps65912->read(tps65912, TPS65912_INT_MSK3, 1, &reg);
  101. reg_mask |= reg << 16;
  102. tps65912->read(tps65912, TPS65912_INT_MSK4, 1, &reg);
  103. reg_mask |= reg << 24;
  104. if (tps65912->irq_mask != reg_mask) {
  105. reg = tps65912->irq_mask & 0xFF;
  106. tps65912->write(tps65912, TPS65912_INT_MSK, 1, &reg);
  107. reg = tps65912->irq_mask >> 8 & 0xFF;
  108. tps65912->write(tps65912, TPS65912_INT_MSK2, 1, &reg);
  109. reg = tps65912->irq_mask >> 16 & 0xFF;
  110. tps65912->write(tps65912, TPS65912_INT_MSK3, 1, &reg);
  111. reg = tps65912->irq_mask >> 24 & 0xFF;
  112. tps65912->write(tps65912, TPS65912_INT_MSK4, 1, &reg);
  113. }
  114. mutex_unlock(&tps65912->irq_lock);
  115. }
  116. static void tps65912_irq_enable(struct irq_data *data)
  117. {
  118. struct tps65912 *tps65912 = irq_data_get_irq_chip_data(data);
  119. tps65912->irq_mask &= ~(1 << irq_to_tps65912_irq(tps65912, data->irq));
  120. }
  121. static void tps65912_irq_disable(struct irq_data *data)
  122. {
  123. struct tps65912 *tps65912 = irq_data_get_irq_chip_data(data);
  124. tps65912->irq_mask |= (1 << irq_to_tps65912_irq(tps65912, data->irq));
  125. }
  126. static struct irq_chip tps65912_irq_chip = {
  127. .name = "tps65912",
  128. .irq_bus_lock = tps65912_irq_lock,
  129. .irq_bus_sync_unlock = tps65912_irq_sync_unlock,
  130. .irq_disable = tps65912_irq_disable,
  131. .irq_enable = tps65912_irq_enable,
  132. };
  133. int tps65912_irq_init(struct tps65912 *tps65912, int irq,
  134. struct tps65912_platform_data *pdata)
  135. {
  136. int ret, cur_irq;
  137. int flags = IRQF_ONESHOT;
  138. u8 reg;
  139. if (!irq) {
  140. dev_warn(tps65912->dev, "No interrupt support, no core IRQ\n");
  141. return 0;
  142. }
  143. if (!pdata || !pdata->irq_base) {
  144. dev_warn(tps65912->dev, "No interrupt support, no IRQ base\n");
  145. return 0;
  146. }
  147. /* Clear unattended interrupts */
  148. tps65912->read(tps65912, TPS65912_INT_STS, 1, &reg);
  149. tps65912->write(tps65912, TPS65912_INT_STS, 1, &reg);
  150. tps65912->read(tps65912, TPS65912_INT_STS2, 1, &reg);
  151. tps65912->write(tps65912, TPS65912_INT_STS2, 1, &reg);
  152. tps65912->read(tps65912, TPS65912_INT_STS3, 1, &reg);
  153. tps65912->write(tps65912, TPS65912_INT_STS3, 1, &reg);
  154. tps65912->read(tps65912, TPS65912_INT_STS4, 1, &reg);
  155. tps65912->write(tps65912, TPS65912_INT_STS4, 1, &reg);
  156. /* Mask top level interrupts */
  157. tps65912->irq_mask = 0xFFFFFFFF;
  158. mutex_init(&tps65912->irq_lock);
  159. tps65912->chip_irq = irq;
  160. tps65912->irq_base = pdata->irq_base;
  161. tps65912->irq_num = TPS65912_NUM_IRQ;
  162. /* Register with genirq */
  163. for (cur_irq = tps65912->irq_base;
  164. cur_irq < tps65912->irq_num + tps65912->irq_base;
  165. cur_irq++) {
  166. irq_set_chip_data(cur_irq, tps65912);
  167. irq_set_chip_and_handler(cur_irq, &tps65912_irq_chip,
  168. handle_edge_irq);
  169. irq_set_nested_thread(cur_irq, 1);
  170. irq_clear_status_flags(cur_irq, IRQ_NOREQUEST | IRQ_NOPROBE);
  171. }
  172. ret = request_threaded_irq(irq, NULL, tps65912_irq, flags,
  173. "tps65912", tps65912);
  174. irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW);
  175. if (ret != 0)
  176. dev_err(tps65912->dev, "Failed to request IRQ: %d\n", ret);
  177. return ret;
  178. }
  179. int tps65912_irq_exit(struct tps65912 *tps65912)
  180. {
  181. free_irq(tps65912->chip_irq, tps65912);
  182. return 0;
  183. }