Kconfig 8.2 KB

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  1. menu "RAM/ROM/Flash chip drivers"
  2. depends on MTD!=n
  3. config MTD_CFI
  4. tristate "Detect flash chips by Common Flash Interface (CFI) probe"
  5. select MTD_GEN_PROBE
  6. select MTD_CFI_UTIL
  7. help
  8. The Common Flash Interface specification was developed by Intel,
  9. AMD and other flash manufactures that provides a universal method
  10. for probing the capabilities of flash devices. If you wish to
  11. support any device that is CFI-compliant, you need to enable this
  12. option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
  13. for more information on CFI.
  14. config MTD_JEDECPROBE
  15. tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
  16. select MTD_GEN_PROBE
  17. select MTD_CFI_UTIL
  18. help
  19. This option enables JEDEC-style probing of flash chips which are not
  20. compatible with the Common Flash Interface, but will use the common
  21. CFI-targeted flash drivers for any chips which are identified which
  22. are in fact compatible in all but the probe method. This actually
  23. covers most AMD/Fujitsu-compatible chips and also non-CFI
  24. Intel chips.
  25. config MTD_GEN_PROBE
  26. tristate
  27. config MTD_CFI_ADV_OPTIONS
  28. bool "Flash chip driver advanced configuration options"
  29. depends on MTD_GEN_PROBE
  30. help
  31. If you need to specify a specific endianness for access to flash
  32. chips, or if you wish to reduce the size of the kernel by including
  33. support for only specific arrangements of flash chips, say 'Y'. This
  34. option does not directly affect the code, but will enable other
  35. configuration options which allow you to do so.
  36. If unsure, say 'N'.
  37. choice
  38. prompt "Flash cmd/query data swapping"
  39. depends on MTD_CFI_ADV_OPTIONS
  40. default MTD_CFI_NOSWAP
  41. ---help---
  42. This option defines the way in which the CPU attempts to arrange
  43. data bits when writing the 'magic' commands to the chips. Saying
  44. 'NO', which is the default when CONFIG_MTD_CFI_ADV_OPTIONS isn't
  45. enabled, means that the CPU will not do any swapping; the chips
  46. are expected to be wired to the CPU in 'host-endian' form.
  47. Specific arrangements are possible with the BIG_ENDIAN_BYTE and
  48. LITTLE_ENDIAN_BYTE, if the bytes are reversed.
  49. config MTD_CFI_NOSWAP
  50. bool "NO"
  51. config MTD_CFI_BE_BYTE_SWAP
  52. bool "BIG_ENDIAN_BYTE"
  53. config MTD_CFI_LE_BYTE_SWAP
  54. bool "LITTLE_ENDIAN_BYTE"
  55. endchoice
  56. config MTD_CFI_GEOMETRY
  57. bool "Specific CFI Flash geometry selection"
  58. depends on MTD_CFI_ADV_OPTIONS
  59. select MTD_MAP_BANK_WIDTH_1 if !(MTD_MAP_BANK_WIDTH_2 || \
  60. MTD_MAP_BANK_WIDTH_4 || MTD_MAP_BANK_WIDTH_8 || \
  61. MTD_MAP_BANK_WIDTH_16 || MTD_MAP_BANK_WIDTH_32)
  62. select MTD_CFI_I1 if !(MTD_CFI_I2 || MTD_CFI_I4 || MTD_CFI_I8)
  63. help
  64. This option does not affect the code directly, but will enable
  65. some other configuration options which would allow you to reduce
  66. the size of the kernel by including support for only certain
  67. arrangements of CFI chips. If unsure, say 'N' and all options
  68. which are supported by the current code will be enabled.
  69. config MTD_MAP_BANK_WIDTH_1
  70. bool "Support 8-bit buswidth" if MTD_CFI_GEOMETRY
  71. default y
  72. help
  73. If you wish to support CFI devices on a physical bus which is
  74. 8 bits wide, say 'Y'.
  75. config MTD_MAP_BANK_WIDTH_2
  76. bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
  77. default y
  78. help
  79. If you wish to support CFI devices on a physical bus which is
  80. 16 bits wide, say 'Y'.
  81. config MTD_MAP_BANK_WIDTH_4
  82. bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
  83. default y
  84. help
  85. If you wish to support CFI devices on a physical bus which is
  86. 32 bits wide, say 'Y'.
  87. config MTD_MAP_BANK_WIDTH_8
  88. bool "Support 64-bit buswidth" if MTD_CFI_GEOMETRY
  89. default n
  90. help
  91. If you wish to support CFI devices on a physical bus which is
  92. 64 bits wide, say 'Y'.
  93. config MTD_MAP_BANK_WIDTH_16
  94. bool "Support 128-bit buswidth" if MTD_CFI_GEOMETRY
  95. default n
  96. help
  97. If you wish to support CFI devices on a physical bus which is
  98. 128 bits wide, say 'Y'.
  99. config MTD_MAP_BANK_WIDTH_32
  100. bool "Support 256-bit buswidth" if MTD_CFI_GEOMETRY
  101. select MTD_COMPLEX_MAPPINGS if HAS_IOMEM
  102. default n
  103. help
  104. If you wish to support CFI devices on a physical bus which is
  105. 256 bits wide, say 'Y'.
  106. config MTD_CFI_I1
  107. bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY
  108. default y
  109. help
  110. If your flash chips are not interleaved - i.e. you only have one
  111. flash chip addressed by each bus cycle, then say 'Y'.
  112. config MTD_CFI_I2
  113. bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY
  114. default y
  115. help
  116. If your flash chips are interleaved in pairs - i.e. you have two
  117. flash chips addressed by each bus cycle, then say 'Y'.
  118. config MTD_CFI_I4
  119. bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY
  120. default n
  121. help
  122. If your flash chips are interleaved in fours - i.e. you have four
  123. flash chips addressed by each bus cycle, then say 'Y'.
  124. config MTD_CFI_I8
  125. bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY
  126. default n
  127. help
  128. If your flash chips are interleaved in eights - i.e. you have eight
  129. flash chips addressed by each bus cycle, then say 'Y'.
  130. config MTD_OTP
  131. bool "Protection Registers aka one-time programmable (OTP) bits"
  132. depends on MTD_CFI_ADV_OPTIONS
  133. default n
  134. help
  135. This enables support for reading, writing and locking so called
  136. "Protection Registers" present on some flash chips.
  137. A subset of them are pre-programmed at the factory with a
  138. unique set of values. The rest is user-programmable.
  139. The user-programmable Protection Registers contain one-time
  140. programmable (OTP) bits; when programmed, register bits cannot be
  141. erased. Each Protection Register can be accessed multiple times to
  142. program individual bits, as long as the register remains unlocked.
  143. Each Protection Register has an associated Lock Register bit. When a
  144. Lock Register bit is programmed, the associated Protection Register
  145. can only be read; it can no longer be programmed. Additionally,
  146. because the Lock Register bits themselves are OTP, when programmed,
  147. Lock Register bits cannot be erased. Therefore, when a Protection
  148. Register is locked, it cannot be unlocked.
  149. This feature should therefore be used with extreme care. Any mistake
  150. in the programming of OTP bits will waste them.
  151. config MTD_CFI_INTELEXT
  152. tristate "Support for CFI command set 0001 (Intel/Sharp chips)"
  153. depends on MTD_GEN_PROBE
  154. select MTD_CFI_UTIL
  155. help
  156. The Common Flash Interface defines a number of different command
  157. sets which a CFI-compliant chip may claim to implement. This code
  158. provides support for command set 0001, used on Intel StrataFlash
  159. and other parts.
  160. config MTD_CFI_AMDSTD
  161. tristate "Support for CFI command set 0002 (AMD/Fujitsu/Spansion chips)"
  162. depends on MTD_GEN_PROBE
  163. select MTD_CFI_UTIL
  164. help
  165. The Common Flash Interface defines a number of different command
  166. sets which a CFI-compliant chip may claim to implement. This code
  167. provides support for command set 0002, used on chips including
  168. the AMD Am29LV320.
  169. config MTD_CFI_STAA
  170. tristate "Support for CFI command set 0020 (ST (Advanced Architecture) chips)"
  171. depends on MTD_GEN_PROBE
  172. select MTD_CFI_UTIL
  173. help
  174. The Common Flash Interface defines a number of different command
  175. sets which a CFI-compliant chip may claim to implement. This code
  176. provides support for command set 0020.
  177. config MTD_CFI_UTIL
  178. tristate
  179. config MTD_RAM
  180. tristate "Support for RAM chips in bus mapping"
  181. help
  182. This option enables basic support for RAM chips accessed through
  183. a bus mapping driver.
  184. config MTD_ROM
  185. tristate "Support for ROM chips in bus mapping"
  186. help
  187. This option enables basic support for ROM chips accessed through
  188. a bus mapping driver.
  189. config MTD_ABSENT
  190. tristate "Support for absent chips in bus mapping"
  191. help
  192. This option enables support for a dummy probing driver used to
  193. allocated placeholder MTD devices on systems that have socketed
  194. or removable media. Use of this driver as a fallback chip probe
  195. preserves the expected registration order of MTD device nodes on
  196. the system regardless of media presence. Device nodes created
  197. with this driver will return -ENODEV upon access.
  198. config MTD_XIP
  199. bool "XIP aware MTD support"
  200. depends on !SMP && (MTD_CFI_INTELEXT || MTD_CFI_AMDSTD) && ARCH_MTD_XIP
  201. default y if XIP_KERNEL
  202. help
  203. This allows MTD support to work with flash memory which is also
  204. used for XIP purposes. If you're not sure what this is all about
  205. then say N.
  206. endmenu