7990.c 17 KB

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  1. /*
  2. * 7990.c -- LANCE ethernet IC generic routines.
  3. * This is an attempt to separate out the bits of various ethernet
  4. * drivers that are common because they all use the AMD 7990 LANCE
  5. * (Local Area Network Controller for Ethernet) chip.
  6. *
  7. * Copyright (C) 05/1998 Peter Maydell <pmaydell@chiark.greenend.org.uk>
  8. *
  9. * Most of this stuff was obtained by looking at other LANCE drivers,
  10. * in particular a2065.[ch]. The AMD C-LANCE datasheet was also helpful.
  11. * NB: this was made easy by the fact that Jes Sorensen had cleaned up
  12. * most of a2025 and sunlance with the aim of merging them, so the
  13. * common code was pretty obvious.
  14. */
  15. #include <linux/crc32.h>
  16. #include <linux/delay.h>
  17. #include <linux/errno.h>
  18. #include <linux/netdevice.h>
  19. #include <linux/etherdevice.h>
  20. #include <linux/module.h>
  21. #include <linux/kernel.h>
  22. #include <linux/types.h>
  23. #include <linux/fcntl.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/ioport.h>
  26. #include <linux/in.h>
  27. #include <linux/route.h>
  28. #include <linux/string.h>
  29. #include <linux/skbuff.h>
  30. #include <asm/irq.h>
  31. /* Used for the temporal inet entries and routing */
  32. #include <linux/socket.h>
  33. #include <linux/bitops.h>
  34. #include <asm/io.h>
  35. #include <asm/dma.h>
  36. #include <asm/pgtable.h>
  37. #ifdef CONFIG_HP300
  38. #include <asm/blinken.h>
  39. #endif
  40. #include "7990.h"
  41. #define WRITERAP(lp, x) out_be16(lp->base + LANCE_RAP, (x))
  42. #define WRITERDP(lp, x) out_be16(lp->base + LANCE_RDP, (x))
  43. #define READRDP(lp) in_be16(lp->base + LANCE_RDP)
  44. #if defined(CONFIG_HPLANCE) || defined(CONFIG_HPLANCE_MODULE)
  45. #include "hplance.h"
  46. #undef WRITERAP
  47. #undef WRITERDP
  48. #undef READRDP
  49. #if defined(CONFIG_MVME147_NET) || defined(CONFIG_MVME147_NET_MODULE)
  50. /* Lossage Factor Nine, Mr Sulu. */
  51. #define WRITERAP(lp, x) (lp->writerap(lp, x))
  52. #define WRITERDP(lp, x) (lp->writerdp(lp, x))
  53. #define READRDP(lp) (lp->readrdp(lp))
  54. #else
  55. /* These inlines can be used if only CONFIG_HPLANCE is defined */
  56. static inline void WRITERAP(struct lance_private *lp, __u16 value)
  57. {
  58. do {
  59. out_be16(lp->base + HPLANCE_REGOFF + LANCE_RAP, value);
  60. } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
  61. }
  62. static inline void WRITERDP(struct lance_private *lp, __u16 value)
  63. {
  64. do {
  65. out_be16(lp->base + HPLANCE_REGOFF + LANCE_RDP, value);
  66. } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
  67. }
  68. static inline __u16 READRDP(struct lance_private *lp)
  69. {
  70. __u16 value;
  71. do {
  72. value = in_be16(lp->base + HPLANCE_REGOFF + LANCE_RDP);
  73. } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
  74. return value;
  75. }
  76. #endif
  77. #endif /* CONFIG_HPLANCE || CONFIG_HPLANCE_MODULE */
  78. /* debugging output macros, various flavours */
  79. /* #define TEST_HITS */
  80. #ifdef UNDEF
  81. #define PRINT_RINGS() \
  82. do { \
  83. int t; \
  84. for (t = 0; t < RX_RING_SIZE; t++) { \
  85. printk("R%d: @(%02X %04X) len %04X, mblen %04X, bits %02X\n", \
  86. t, ib->brx_ring[t].rmd1_hadr, ib->brx_ring[t].rmd0, \
  87. ib->brx_ring[t].length, \
  88. ib->brx_ring[t].mblength, ib->brx_ring[t].rmd1_bits); \
  89. } \
  90. for (t = 0; t < TX_RING_SIZE; t++) { \
  91. printk("T%d: @(%02X %04X) len %04X, misc %04X, bits %02X\n", \
  92. t, ib->btx_ring[t].tmd1_hadr, ib->btx_ring[t].tmd0, \
  93. ib->btx_ring[t].length, \
  94. ib->btx_ring[t].misc, ib->btx_ring[t].tmd1_bits); \
  95. } \
  96. } while (0)
  97. #else
  98. #define PRINT_RINGS()
  99. #endif
  100. /* Load the CSR registers. The LANCE has to be STOPped when we do this! */
  101. static void load_csrs(struct lance_private *lp)
  102. {
  103. volatile struct lance_init_block *aib = lp->lance_init_block;
  104. int leptr;
  105. leptr = LANCE_ADDR(aib);
  106. WRITERAP(lp, LE_CSR1); /* load address of init block */
  107. WRITERDP(lp, leptr & 0xFFFF);
  108. WRITERAP(lp, LE_CSR2);
  109. WRITERDP(lp, leptr >> 16);
  110. WRITERAP(lp, LE_CSR3);
  111. WRITERDP(lp, lp->busmaster_regval); /* set byteswap/ALEctrl/byte ctrl */
  112. /* Point back to csr0 */
  113. WRITERAP(lp, LE_CSR0);
  114. }
  115. /* #define to 0 or 1 appropriately */
  116. #define DEBUG_IRING 0
  117. /* Set up the Lance Rx and Tx rings and the init block */
  118. static void lance_init_ring(struct net_device *dev)
  119. {
  120. struct lance_private *lp = netdev_priv(dev);
  121. volatile struct lance_init_block *ib = lp->init_block;
  122. volatile struct lance_init_block *aib; /* for LANCE_ADDR computations */
  123. int leptr;
  124. int i;
  125. aib = lp->lance_init_block;
  126. lp->rx_new = lp->tx_new = 0;
  127. lp->rx_old = lp->tx_old = 0;
  128. ib->mode = LE_MO_PROM; /* normal, enable Tx & Rx */
  129. /* Copy the ethernet address to the lance init block
  130. * Notice that we do a byteswap if we're big endian.
  131. * [I think this is the right criterion; at least, sunlance,
  132. * a2065 and atarilance do the byteswap and lance.c (PC) doesn't.
  133. * However, the datasheet says that the BSWAP bit doesn't affect
  134. * the init block, so surely it should be low byte first for
  135. * everybody? Um.]
  136. * We could define the ib->physaddr as three 16bit values and
  137. * use (addr[1] << 8) | addr[0] & co, but this is more efficient.
  138. */
  139. #ifdef __BIG_ENDIAN
  140. ib->phys_addr[0] = dev->dev_addr[1];
  141. ib->phys_addr[1] = dev->dev_addr[0];
  142. ib->phys_addr[2] = dev->dev_addr[3];
  143. ib->phys_addr[3] = dev->dev_addr[2];
  144. ib->phys_addr[4] = dev->dev_addr[5];
  145. ib->phys_addr[5] = dev->dev_addr[4];
  146. #else
  147. for (i = 0; i < 6; i++)
  148. ib->phys_addr[i] = dev->dev_addr[i];
  149. #endif
  150. if (DEBUG_IRING)
  151. printk("TX rings:\n");
  152. lp->tx_full = 0;
  153. /* Setup the Tx ring entries */
  154. for (i = 0; i < (1 << lp->lance_log_tx_bufs); i++) {
  155. leptr = LANCE_ADDR(&aib->tx_buf[i][0]);
  156. ib->btx_ring[i].tmd0 = leptr;
  157. ib->btx_ring[i].tmd1_hadr = leptr >> 16;
  158. ib->btx_ring[i].tmd1_bits = 0;
  159. ib->btx_ring[i].length = 0xf000; /* The ones required by tmd2 */
  160. ib->btx_ring[i].misc = 0;
  161. if (DEBUG_IRING)
  162. printk("%d: 0x%8.8x\n", i, leptr);
  163. }
  164. /* Setup the Rx ring entries */
  165. if (DEBUG_IRING)
  166. printk("RX rings:\n");
  167. for (i = 0; i < (1 << lp->lance_log_rx_bufs); i++) {
  168. leptr = LANCE_ADDR(&aib->rx_buf[i][0]);
  169. ib->brx_ring[i].rmd0 = leptr;
  170. ib->brx_ring[i].rmd1_hadr = leptr >> 16;
  171. ib->brx_ring[i].rmd1_bits = LE_R1_OWN;
  172. /* 0xf000 == bits that must be one (reserved, presumably) */
  173. ib->brx_ring[i].length = -RX_BUFF_SIZE | 0xf000;
  174. ib->brx_ring[i].mblength = 0;
  175. if (DEBUG_IRING)
  176. printk("%d: 0x%8.8x\n", i, leptr);
  177. }
  178. /* Setup the initialization block */
  179. /* Setup rx descriptor pointer */
  180. leptr = LANCE_ADDR(&aib->brx_ring);
  181. ib->rx_len = (lp->lance_log_rx_bufs << 13) | (leptr >> 16);
  182. ib->rx_ptr = leptr;
  183. if (DEBUG_IRING)
  184. printk("RX ptr: %8.8x\n", leptr);
  185. /* Setup tx descriptor pointer */
  186. leptr = LANCE_ADDR(&aib->btx_ring);
  187. ib->tx_len = (lp->lance_log_tx_bufs << 13) | (leptr >> 16);
  188. ib->tx_ptr = leptr;
  189. if (DEBUG_IRING)
  190. printk("TX ptr: %8.8x\n", leptr);
  191. /* Clear the multicast filter */
  192. ib->filter[0] = 0;
  193. ib->filter[1] = 0;
  194. PRINT_RINGS();
  195. }
  196. /* LANCE must be STOPped before we do this, too... */
  197. static int init_restart_lance(struct lance_private *lp)
  198. {
  199. int i;
  200. WRITERAP(lp, LE_CSR0);
  201. WRITERDP(lp, LE_C0_INIT);
  202. /* Need a hook here for sunlance ledma stuff */
  203. /* Wait for the lance to complete initialization */
  204. for (i = 0; (i < 100) && !(READRDP(lp) & (LE_C0_ERR | LE_C0_IDON)); i++)
  205. barrier();
  206. if ((i == 100) || (READRDP(lp) & LE_C0_ERR)) {
  207. printk("LANCE unopened after %d ticks, csr0=%4.4x.\n", i, READRDP(lp));
  208. return -1;
  209. }
  210. /* Clear IDON by writing a "1", enable interrupts and start lance */
  211. WRITERDP(lp, LE_C0_IDON);
  212. WRITERDP(lp, LE_C0_INEA | LE_C0_STRT);
  213. return 0;
  214. }
  215. static int lance_reset(struct net_device *dev)
  216. {
  217. struct lance_private *lp = netdev_priv(dev);
  218. int status;
  219. /* Stop the lance */
  220. WRITERAP(lp, LE_CSR0);
  221. WRITERDP(lp, LE_C0_STOP);
  222. load_csrs(lp);
  223. lance_init_ring(dev);
  224. dev->trans_start = jiffies; /* prevent tx timeout */
  225. status = init_restart_lance(lp);
  226. #ifdef DEBUG_DRIVER
  227. printk("Lance restart=%d\n", status);
  228. #endif
  229. return status;
  230. }
  231. static int lance_rx(struct net_device *dev)
  232. {
  233. struct lance_private *lp = netdev_priv(dev);
  234. volatile struct lance_init_block *ib = lp->init_block;
  235. volatile struct lance_rx_desc *rd;
  236. unsigned char bits;
  237. #ifdef TEST_HITS
  238. int i;
  239. #endif
  240. #ifdef TEST_HITS
  241. printk("[");
  242. for (i = 0; i < RX_RING_SIZE; i++) {
  243. if (i == lp->rx_new)
  244. printk("%s",
  245. ib->brx_ring[i].rmd1_bits & LE_R1_OWN ? "_" : "X");
  246. else
  247. printk("%s",
  248. ib->brx_ring[i].rmd1_bits & LE_R1_OWN ? "." : "1");
  249. }
  250. printk("]");
  251. #endif
  252. #ifdef CONFIG_HP300
  253. blinken_leds(0x40, 0);
  254. #endif
  255. WRITERDP(lp, LE_C0_RINT | LE_C0_INEA); /* ack Rx int, reenable ints */
  256. for (rd = &ib->brx_ring[lp->rx_new]; /* For each Rx ring we own... */
  257. !((bits = rd->rmd1_bits) & LE_R1_OWN);
  258. rd = &ib->brx_ring[lp->rx_new]) {
  259. /* We got an incomplete frame? */
  260. if ((bits & LE_R1_POK) != LE_R1_POK) {
  261. dev->stats.rx_over_errors++;
  262. dev->stats.rx_errors++;
  263. continue;
  264. } else if (bits & LE_R1_ERR) {
  265. /* Count only the end frame as a rx error,
  266. * not the beginning
  267. */
  268. if (bits & LE_R1_BUF)
  269. dev->stats.rx_fifo_errors++;
  270. if (bits & LE_R1_CRC)
  271. dev->stats.rx_crc_errors++;
  272. if (bits & LE_R1_OFL)
  273. dev->stats.rx_over_errors++;
  274. if (bits & LE_R1_FRA)
  275. dev->stats.rx_frame_errors++;
  276. if (bits & LE_R1_EOP)
  277. dev->stats.rx_errors++;
  278. } else {
  279. int len = (rd->mblength & 0xfff) - 4;
  280. struct sk_buff *skb = netdev_alloc_skb(dev, len + 2);
  281. if (!skb) {
  282. dev->stats.rx_dropped++;
  283. rd->mblength = 0;
  284. rd->rmd1_bits = LE_R1_OWN;
  285. lp->rx_new = (lp->rx_new + 1) & lp->rx_ring_mod_mask;
  286. return 0;
  287. }
  288. skb_reserve(skb, 2); /* 16 byte align */
  289. skb_put(skb, len); /* make room */
  290. skb_copy_to_linear_data(skb,
  291. (unsigned char *)&(ib->rx_buf[lp->rx_new][0]),
  292. len);
  293. skb->protocol = eth_type_trans(skb, dev);
  294. netif_rx(skb);
  295. dev->stats.rx_packets++;
  296. dev->stats.rx_bytes += len;
  297. }
  298. /* Return the packet to the pool */
  299. rd->mblength = 0;
  300. rd->rmd1_bits = LE_R1_OWN;
  301. lp->rx_new = (lp->rx_new + 1) & lp->rx_ring_mod_mask;
  302. }
  303. return 0;
  304. }
  305. static int lance_tx(struct net_device *dev)
  306. {
  307. struct lance_private *lp = netdev_priv(dev);
  308. volatile struct lance_init_block *ib = lp->init_block;
  309. volatile struct lance_tx_desc *td;
  310. int i, j;
  311. int status;
  312. #ifdef CONFIG_HP300
  313. blinken_leds(0x80, 0);
  314. #endif
  315. /* csr0 is 2f3 */
  316. WRITERDP(lp, LE_C0_TINT | LE_C0_INEA);
  317. /* csr0 is 73 */
  318. j = lp->tx_old;
  319. for (i = j; i != lp->tx_new; i = j) {
  320. td = &ib->btx_ring[i];
  321. /* If we hit a packet not owned by us, stop */
  322. if (td->tmd1_bits & LE_T1_OWN)
  323. break;
  324. if (td->tmd1_bits & LE_T1_ERR) {
  325. status = td->misc;
  326. dev->stats.tx_errors++;
  327. if (status & LE_T3_RTY)
  328. dev->stats.tx_aborted_errors++;
  329. if (status & LE_T3_LCOL)
  330. dev->stats.tx_window_errors++;
  331. if (status & LE_T3_CLOS) {
  332. dev->stats.tx_carrier_errors++;
  333. if (lp->auto_select) {
  334. lp->tpe = 1 - lp->tpe;
  335. printk("%s: Carrier Lost, trying %s\n",
  336. dev->name,
  337. lp->tpe ? "TPE" : "AUI");
  338. /* Stop the lance */
  339. WRITERAP(lp, LE_CSR0);
  340. WRITERDP(lp, LE_C0_STOP);
  341. lance_init_ring(dev);
  342. load_csrs(lp);
  343. init_restart_lance(lp);
  344. return 0;
  345. }
  346. }
  347. /* buffer errors and underflows turn off the transmitter */
  348. /* Restart the adapter */
  349. if (status & (LE_T3_BUF|LE_T3_UFL)) {
  350. dev->stats.tx_fifo_errors++;
  351. printk("%s: Tx: ERR_BUF|ERR_UFL, restarting\n",
  352. dev->name);
  353. /* Stop the lance */
  354. WRITERAP(lp, LE_CSR0);
  355. WRITERDP(lp, LE_C0_STOP);
  356. lance_init_ring(dev);
  357. load_csrs(lp);
  358. init_restart_lance(lp);
  359. return 0;
  360. }
  361. } else if ((td->tmd1_bits & LE_T1_POK) == LE_T1_POK) {
  362. /*
  363. * So we don't count the packet more than once.
  364. */
  365. td->tmd1_bits &= ~(LE_T1_POK);
  366. /* One collision before packet was sent. */
  367. if (td->tmd1_bits & LE_T1_EONE)
  368. dev->stats.collisions++;
  369. /* More than one collision, be optimistic. */
  370. if (td->tmd1_bits & LE_T1_EMORE)
  371. dev->stats.collisions += 2;
  372. dev->stats.tx_packets++;
  373. }
  374. j = (j + 1) & lp->tx_ring_mod_mask;
  375. }
  376. lp->tx_old = j;
  377. WRITERDP(lp, LE_C0_TINT | LE_C0_INEA);
  378. return 0;
  379. }
  380. static irqreturn_t
  381. lance_interrupt(int irq, void *dev_id)
  382. {
  383. struct net_device *dev = (struct net_device *)dev_id;
  384. struct lance_private *lp = netdev_priv(dev);
  385. int csr0;
  386. spin_lock(&lp->devlock);
  387. WRITERAP(lp, LE_CSR0); /* LANCE Controller Status */
  388. csr0 = READRDP(lp);
  389. PRINT_RINGS();
  390. if (!(csr0 & LE_C0_INTR)) { /* Check if any interrupt has */
  391. spin_unlock(&lp->devlock);
  392. return IRQ_NONE; /* been generated by the Lance. */
  393. }
  394. /* Acknowledge all the interrupt sources ASAP */
  395. WRITERDP(lp, csr0 & ~(LE_C0_INEA|LE_C0_TDMD|LE_C0_STOP|LE_C0_STRT|LE_C0_INIT));
  396. if ((csr0 & LE_C0_ERR)) {
  397. /* Clear the error condition */
  398. WRITERDP(lp, LE_C0_BABL|LE_C0_ERR|LE_C0_MISS|LE_C0_INEA);
  399. }
  400. if (csr0 & LE_C0_RINT)
  401. lance_rx(dev);
  402. if (csr0 & LE_C0_TINT)
  403. lance_tx(dev);
  404. /* Log misc errors. */
  405. if (csr0 & LE_C0_BABL)
  406. dev->stats.tx_errors++; /* Tx babble. */
  407. if (csr0 & LE_C0_MISS)
  408. dev->stats.rx_errors++; /* Missed a Rx frame. */
  409. if (csr0 & LE_C0_MERR) {
  410. printk("%s: Bus master arbitration failure, status %4.4x.\n",
  411. dev->name, csr0);
  412. /* Restart the chip. */
  413. WRITERDP(lp, LE_C0_STRT);
  414. }
  415. if (lp->tx_full && netif_queue_stopped(dev) && (TX_BUFFS_AVAIL >= 0)) {
  416. lp->tx_full = 0;
  417. netif_wake_queue(dev);
  418. }
  419. WRITERAP(lp, LE_CSR0);
  420. WRITERDP(lp, LE_C0_BABL|LE_C0_CERR|LE_C0_MISS|LE_C0_MERR|LE_C0_IDON|LE_C0_INEA);
  421. spin_unlock(&lp->devlock);
  422. return IRQ_HANDLED;
  423. }
  424. int lance_open(struct net_device *dev)
  425. {
  426. struct lance_private *lp = netdev_priv(dev);
  427. int res;
  428. /* Install the Interrupt handler. Or we could shunt this out to specific drivers? */
  429. if (request_irq(lp->irq, lance_interrupt, IRQF_SHARED, lp->name, dev))
  430. return -EAGAIN;
  431. res = lance_reset(dev);
  432. spin_lock_init(&lp->devlock);
  433. netif_start_queue(dev);
  434. return res;
  435. }
  436. EXPORT_SYMBOL_GPL(lance_open);
  437. int lance_close(struct net_device *dev)
  438. {
  439. struct lance_private *lp = netdev_priv(dev);
  440. netif_stop_queue(dev);
  441. /* Stop the LANCE */
  442. WRITERAP(lp, LE_CSR0);
  443. WRITERDP(lp, LE_C0_STOP);
  444. free_irq(lp->irq, dev);
  445. return 0;
  446. }
  447. EXPORT_SYMBOL_GPL(lance_close);
  448. void lance_tx_timeout(struct net_device *dev)
  449. {
  450. printk("lance_tx_timeout\n");
  451. lance_reset(dev);
  452. dev->trans_start = jiffies; /* prevent tx timeout */
  453. netif_wake_queue(dev);
  454. }
  455. EXPORT_SYMBOL_GPL(lance_tx_timeout);
  456. int lance_start_xmit(struct sk_buff *skb, struct net_device *dev)
  457. {
  458. struct lance_private *lp = netdev_priv(dev);
  459. volatile struct lance_init_block *ib = lp->init_block;
  460. int entry, skblen, len;
  461. static int outs;
  462. unsigned long flags;
  463. if (!TX_BUFFS_AVAIL)
  464. return NETDEV_TX_LOCKED;
  465. netif_stop_queue(dev);
  466. skblen = skb->len;
  467. #ifdef DEBUG_DRIVER
  468. /* dump the packet */
  469. {
  470. int i;
  471. for (i = 0; i < 64; i++) {
  472. if ((i % 16) == 0)
  473. printk("\n");
  474. printk("%2.2x ", skb->data[i]);
  475. }
  476. }
  477. #endif
  478. len = (skblen <= ETH_ZLEN) ? ETH_ZLEN : skblen;
  479. entry = lp->tx_new & lp->tx_ring_mod_mask;
  480. ib->btx_ring[entry].length = (-len) | 0xf000;
  481. ib->btx_ring[entry].misc = 0;
  482. if (skb->len < ETH_ZLEN)
  483. memset((void *)&ib->tx_buf[entry][0], 0, ETH_ZLEN);
  484. skb_copy_from_linear_data(skb, (void *)&ib->tx_buf[entry][0], skblen);
  485. /* Now, give the packet to the lance */
  486. ib->btx_ring[entry].tmd1_bits = (LE_T1_POK|LE_T1_OWN);
  487. lp->tx_new = (lp->tx_new + 1) & lp->tx_ring_mod_mask;
  488. outs++;
  489. /* Kick the lance: transmit now */
  490. WRITERDP(lp, LE_C0_INEA | LE_C0_TDMD);
  491. dev_consume_skb_any(skb);
  492. spin_lock_irqsave(&lp->devlock, flags);
  493. if (TX_BUFFS_AVAIL)
  494. netif_start_queue(dev);
  495. else
  496. lp->tx_full = 1;
  497. spin_unlock_irqrestore(&lp->devlock, flags);
  498. return NETDEV_TX_OK;
  499. }
  500. EXPORT_SYMBOL_GPL(lance_start_xmit);
  501. /* taken from the depca driver via a2065.c */
  502. static void lance_load_multicast(struct net_device *dev)
  503. {
  504. struct lance_private *lp = netdev_priv(dev);
  505. volatile struct lance_init_block *ib = lp->init_block;
  506. volatile u16 *mcast_table = (u16 *)&ib->filter;
  507. struct netdev_hw_addr *ha;
  508. u32 crc;
  509. /* set all multicast bits */
  510. if (dev->flags & IFF_ALLMULTI) {
  511. ib->filter[0] = 0xffffffff;
  512. ib->filter[1] = 0xffffffff;
  513. return;
  514. }
  515. /* clear the multicast filter */
  516. ib->filter[0] = 0;
  517. ib->filter[1] = 0;
  518. /* Add addresses */
  519. netdev_for_each_mc_addr(ha, dev) {
  520. crc = ether_crc_le(6, ha->addr);
  521. crc = crc >> 26;
  522. mcast_table[crc >> 4] |= 1 << (crc & 0xf);
  523. }
  524. }
  525. void lance_set_multicast(struct net_device *dev)
  526. {
  527. struct lance_private *lp = netdev_priv(dev);
  528. volatile struct lance_init_block *ib = lp->init_block;
  529. int stopped;
  530. stopped = netif_queue_stopped(dev);
  531. if (!stopped)
  532. netif_stop_queue(dev);
  533. while (lp->tx_old != lp->tx_new)
  534. schedule();
  535. WRITERAP(lp, LE_CSR0);
  536. WRITERDP(lp, LE_C0_STOP);
  537. lance_init_ring(dev);
  538. if (dev->flags & IFF_PROMISC) {
  539. ib->mode |= LE_MO_PROM;
  540. } else {
  541. ib->mode &= ~LE_MO_PROM;
  542. lance_load_multicast(dev);
  543. }
  544. load_csrs(lp);
  545. init_restart_lance(lp);
  546. if (!stopped)
  547. netif_start_queue(dev);
  548. }
  549. EXPORT_SYMBOL_GPL(lance_set_multicast);
  550. #ifdef CONFIG_NET_POLL_CONTROLLER
  551. void lance_poll(struct net_device *dev)
  552. {
  553. struct lance_private *lp = netdev_priv(dev);
  554. spin_lock(&lp->devlock);
  555. WRITERAP(lp, LE_CSR0);
  556. WRITERDP(lp, LE_C0_STRT);
  557. spin_unlock(&lp->devlock);
  558. lance_interrupt(dev->irq, dev);
  559. }
  560. EXPORT_SYMBOL_GPL(lance_poll);
  561. #endif
  562. MODULE_LICENSE("GPL");