ariadne.h 15 KB

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  1. /*
  2. * Amiga Linux/m68k Ariadne Ethernet Driver
  3. *
  4. * © Copyright 1995 by Geert Uytterhoeven (geert@linux-m68k.org)
  5. * Peter De Schrijver
  6. * (Peter.DeSchrijver@linux.cc.kuleuven.ac.be)
  7. *
  8. * ----------------------------------------------------------------------------------
  9. *
  10. * This program is based on
  11. *
  12. * lance.c: An AMD LANCE ethernet driver for linux.
  13. * Written 1993-94 by Donald Becker.
  14. *
  15. * Am79C960: PCnet(tm)-ISA Single-Chip Ethernet Controller
  16. * Advanced Micro Devices
  17. * Publication #16907, Rev. B, Amendment/0, May 1994
  18. *
  19. * MC68230: Parallel Interface/Timer (PI/T)
  20. * Motorola Semiconductors, December, 1983
  21. *
  22. * ----------------------------------------------------------------------------------
  23. *
  24. * This file is subject to the terms and conditions of the GNU General Public
  25. * License. See the file COPYING in the main directory of the Linux
  26. * distribution for more details.
  27. *
  28. * ----------------------------------------------------------------------------------
  29. *
  30. * The Ariadne is a Zorro-II board made by Village Tronic. It contains:
  31. *
  32. * - an Am79C960 PCnet-ISA Single-Chip Ethernet Controller with both
  33. * 10BASE-2 (thin coax) and 10BASE-T (UTP) connectors
  34. *
  35. * - an MC68230 Parallel Interface/Timer configured as 2 parallel ports
  36. */
  37. /*
  38. * Am79C960 PCnet-ISA
  39. */
  40. struct Am79C960 {
  41. volatile u_short AddressPROM[8];
  42. /* IEEE Address PROM (Unused in the Ariadne) */
  43. volatile u_short RDP; /* Register Data Port */
  44. volatile u_short RAP; /* Register Address Port */
  45. volatile u_short Reset; /* Reset Chip on Read Access */
  46. volatile u_short IDP; /* ISACSR Data Port */
  47. };
  48. /*
  49. * Am79C960 Control and Status Registers
  50. *
  51. * These values are already swap()ed!!
  52. *
  53. * Only registers marked with a `-' are intended for network software
  54. * access
  55. */
  56. #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
  57. #define CSR1 0x0100 /* - IADR[15:0] */
  58. #define CSR2 0x0200 /* - IADR[23:16] */
  59. #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
  60. #define CSR4 0x0400 /* - Test and Features Control */
  61. #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
  62. #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
  63. #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
  64. #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
  65. #define CSR11 0x0b00 /* - Logical Address Filter, LADRF[63:48] */
  66. #define CSR12 0x0c00 /* - Physical Address Register, PADR[15:0] */
  67. #define CSR13 0x0d00 /* - Physical Address Register, PADR[31:16] */
  68. #define CSR14 0x0e00 /* - Physical Address Register, PADR[47:32] */
  69. #define CSR15 0x0f00 /* - Mode Register */
  70. #define CSR16 0x1000 /* Initialization Block Address Lower */
  71. #define CSR17 0x1100 /* Initialization Block Address Upper */
  72. #define CSR18 0x1200 /* Current Receive Buffer Address */
  73. #define CSR19 0x1300 /* Current Receive Buffer Address */
  74. #define CSR20 0x1400 /* Current Transmit Buffer Address */
  75. #define CSR21 0x1500 /* Current Transmit Buffer Address */
  76. #define CSR22 0x1600 /* Next Receive Buffer Address */
  77. #define CSR23 0x1700 /* Next Receive Buffer Address */
  78. #define CSR24 0x1800 /* - Base Address of Receive Ring */
  79. #define CSR25 0x1900 /* - Base Address of Receive Ring */
  80. #define CSR26 0x1a00 /* Next Receive Descriptor Address */
  81. #define CSR27 0x1b00 /* Next Receive Descriptor Address */
  82. #define CSR28 0x1c00 /* Current Receive Descriptor Address */
  83. #define CSR29 0x1d00 /* Current Receive Descriptor Address */
  84. #define CSR30 0x1e00 /* - Base Address of Transmit Ring */
  85. #define CSR31 0x1f00 /* - Base Address of transmit Ring */
  86. #define CSR32 0x2000 /* Next Transmit Descriptor Address */
  87. #define CSR33 0x2100 /* Next Transmit Descriptor Address */
  88. #define CSR34 0x2200 /* Current Transmit Descriptor Address */
  89. #define CSR35 0x2300 /* Current Transmit Descriptor Address */
  90. #define CSR36 0x2400 /* Next Next Receive Descriptor Address */
  91. #define CSR37 0x2500 /* Next Next Receive Descriptor Address */
  92. #define CSR38 0x2600 /* Next Next Transmit Descriptor Address */
  93. #define CSR39 0x2700 /* Next Next Transmit Descriptor Address */
  94. #define CSR40 0x2800 /* Current Receive Status and Byte Count */
  95. #define CSR41 0x2900 /* Current Receive Status and Byte Count */
  96. #define CSR42 0x2a00 /* Current Transmit Status and Byte Count */
  97. #define CSR43 0x2b00 /* Current Transmit Status and Byte Count */
  98. #define CSR44 0x2c00 /* Next Receive Status and Byte Count */
  99. #define CSR45 0x2d00 /* Next Receive Status and Byte Count */
  100. #define CSR46 0x2e00 /* Poll Time Counter */
  101. #define CSR47 0x2f00 /* Polling Interval */
  102. #define CSR48 0x3000 /* Temporary Storage */
  103. #define CSR49 0x3100 /* Temporary Storage */
  104. #define CSR50 0x3200 /* Temporary Storage */
  105. #define CSR51 0x3300 /* Temporary Storage */
  106. #define CSR52 0x3400 /* Temporary Storage */
  107. #define CSR53 0x3500 /* Temporary Storage */
  108. #define CSR54 0x3600 /* Temporary Storage */
  109. #define CSR55 0x3700 /* Temporary Storage */
  110. #define CSR56 0x3800 /* Temporary Storage */
  111. #define CSR57 0x3900 /* Temporary Storage */
  112. #define CSR58 0x3a00 /* Temporary Storage */
  113. #define CSR59 0x3b00 /* Temporary Storage */
  114. #define CSR60 0x3c00 /* Previous Transmit Descriptor Address */
  115. #define CSR61 0x3d00 /* Previous Transmit Descriptor Address */
  116. #define CSR62 0x3e00 /* Previous Transmit Status and Byte Count */
  117. #define CSR63 0x3f00 /* Previous Transmit Status and Byte Count */
  118. #define CSR64 0x4000 /* Next Transmit Buffer Address */
  119. #define CSR65 0x4100 /* Next Transmit Buffer Address */
  120. #define CSR66 0x4200 /* Next Transmit Status and Byte Count */
  121. #define CSR67 0x4300 /* Next Transmit Status and Byte Count */
  122. #define CSR68 0x4400 /* Transmit Status Temporary Storage */
  123. #define CSR69 0x4500 /* Transmit Status Temporary Storage */
  124. #define CSR70 0x4600 /* Temporary Storage */
  125. #define CSR71 0x4700 /* Temporary Storage */
  126. #define CSR72 0x4800 /* Receive Ring Counter */
  127. #define CSR74 0x4a00 /* Transmit Ring Counter */
  128. #define CSR76 0x4c00 /* - Receive Ring Length */
  129. #define CSR78 0x4e00 /* - Transmit Ring Length */
  130. #define CSR80 0x5000 /* - Burst and FIFO Threshold Control */
  131. #define CSR82 0x5200 /* - Bus Activity Timer */
  132. #define CSR84 0x5400 /* DMA Address */
  133. #define CSR85 0x5500 /* DMA Address */
  134. #define CSR86 0x5600 /* Buffer Byte Counter */
  135. #define CSR88 0x5800 /* - Chip ID */
  136. #define CSR89 0x5900 /* - Chip ID */
  137. #define CSR92 0x5c00 /* Ring Length Conversion */
  138. #define CSR94 0x5e00 /* Transmit Time Domain Reflectometry Count */
  139. #define CSR96 0x6000 /* Bus Interface Scratch Register 0 */
  140. #define CSR97 0x6100 /* Bus Interface Scratch Register 0 */
  141. #define CSR98 0x6200 /* Bus Interface Scratch Register 1 */
  142. #define CSR99 0x6300 /* Bus Interface Scratch Register 1 */
  143. #define CSR104 0x6800 /* SWAP */
  144. #define CSR105 0x6900 /* SWAP */
  145. #define CSR108 0x6c00 /* Buffer Management Scratch */
  146. #define CSR109 0x6d00 /* Buffer Management Scratch */
  147. #define CSR112 0x7000 /* - Missed Frame Count */
  148. #define CSR114 0x7200 /* - Receive Collision Count */
  149. #define CSR124 0x7c00 /* - Buffer Management Unit Test */
  150. /*
  151. * Am79C960 ISA Control and Status Registers
  152. *
  153. * These values are already swap()ed!!
  154. */
  155. #define ISACSR0 0x0000 /* Master Mode Read Active */
  156. #define ISACSR1 0x0100 /* Master Mode Write Active */
  157. #define ISACSR2 0x0200 /* Miscellaneous Configuration */
  158. #define ISACSR4 0x0400 /* LED0 Status (Link Integrity) */
  159. #define ISACSR5 0x0500 /* LED1 Status */
  160. #define ISACSR6 0x0600 /* LED2 Status */
  161. #define ISACSR7 0x0700 /* LED3 Status */
  162. /*
  163. * Bit definitions for CSR0 (PCnet-ISA Controller Status)
  164. *
  165. * These values are already swap()ed!!
  166. */
  167. #define ERR 0x0080 /* Error */
  168. #define BABL 0x0040 /* Babble: Transmitted too many bits */
  169. #define CERR 0x0020 /* No Heartbeat (10BASE-T) */
  170. #define MISS 0x0010 /* Missed Frame */
  171. #define MERR 0x0008 /* Memory Error */
  172. #define RINT 0x0004 /* Receive Interrupt */
  173. #define TINT 0x0002 /* Transmit Interrupt */
  174. #define IDON 0x0001 /* Initialization Done */
  175. #define INTR 0x8000 /* Interrupt Flag */
  176. #define INEA 0x4000 /* Interrupt Enable */
  177. #define RXON 0x2000 /* Receive On */
  178. #define TXON 0x1000 /* Transmit On */
  179. #define TDMD 0x0800 /* Transmit Demand */
  180. #define STOP 0x0400 /* Stop */
  181. #define STRT 0x0200 /* Start */
  182. #define INIT 0x0100 /* Initialize */
  183. /*
  184. * Bit definitions for CSR3 (Interrupt Masks and Deferral Control)
  185. *
  186. * These values are already swap()ed!!
  187. */
  188. #define BABLM 0x0040 /* Babble Mask */
  189. #define MISSM 0x0010 /* Missed Frame Mask */
  190. #define MERRM 0x0008 /* Memory Error Mask */
  191. #define RINTM 0x0004 /* Receive Interrupt Mask */
  192. #define TINTM 0x0002 /* Transmit Interrupt Mask */
  193. #define IDONM 0x0001 /* Initialization Done Mask */
  194. #define DXMT2PD 0x1000 /* Disable Transmit Two Part Deferral */
  195. #define EMBA 0x0800 /* Enable Modified Back-off Algorithm */
  196. /*
  197. * Bit definitions for CSR4 (Test and Features Control)
  198. *
  199. * These values are already swap()ed!!
  200. */
  201. #define ENTST 0x0080 /* Enable Test Mode */
  202. #define DMAPLUS 0x0040 /* Disable Burst Transaction Counter */
  203. #define TIMER 0x0020 /* Timer Enable Register */
  204. #define DPOLL 0x0010 /* Disable Transmit Polling */
  205. #define APAD_XMT 0x0008 /* Auto Pad Transmit */
  206. #define ASTRP_RCV 0x0004 /* Auto Pad Stripping */
  207. #define MFCO 0x0002 /* Missed Frame Counter Overflow Interrupt */
  208. #define MFCOM 0x0001 /* Missed Frame Counter Overflow Mask */
  209. #define RCVCCO 0x2000 /* Receive Collision Counter Overflow Interrupt */
  210. #define RCVCCOM 0x1000 /* Receive Collision Counter Overflow Mask */
  211. #define TXSTRT 0x0800 /* Transmit Start Status */
  212. #define TXSTRTM 0x0400 /* Transmit Start Mask */
  213. #define JAB 0x0200 /* Jabber Error */
  214. #define JABM 0x0100 /* Jabber Error Mask */
  215. /*
  216. * Bit definitions for CSR15 (Mode Register)
  217. *
  218. * These values are already swap()ed!!
  219. */
  220. #define PROM 0x0080 /* Promiscuous Mode */
  221. #define DRCVBC 0x0040 /* Disable Receive Broadcast */
  222. #define DRCVPA 0x0020 /* Disable Receive Physical Address */
  223. #define DLNKTST 0x0010 /* Disable Link Status */
  224. #define DAPC 0x0008 /* Disable Automatic Polarity Correction */
  225. #define MENDECL 0x0004 /* MENDEC Loopback Mode */
  226. #define LRTTSEL 0x0002 /* Low Receive Threshold/Transmit Mode Select */
  227. #define PORTSEL1 0x0001 /* Port Select Bits */
  228. #define PORTSEL2 0x8000 /* Port Select Bits */
  229. #define INTL 0x4000 /* Internal Loopback */
  230. #define DRTY 0x2000 /* Disable Retry */
  231. #define FCOLL 0x1000 /* Force Collision */
  232. #define DXMTFCS 0x0800 /* Disable Transmit CRC */
  233. #define LOOP 0x0400 /* Loopback Enable */
  234. #define DTX 0x0200 /* Disable Transmitter */
  235. #define DRX 0x0100 /* Disable Receiver */
  236. /*
  237. * Bit definitions for ISACSR2 (Miscellaneous Configuration)
  238. *
  239. * These values are already swap()ed!!
  240. */
  241. #define ASEL 0x0200 /* Media Interface Port Auto Select */
  242. /*
  243. * Bit definitions for ISACSR5-7 (LED1-3 Status)
  244. *
  245. * These values are already swap()ed!!
  246. */
  247. #define LEDOUT 0x0080 /* Current LED Status */
  248. #define PSE 0x8000 /* Pulse Stretcher Enable */
  249. #define XMTE 0x1000 /* Enable Transmit Status Signal */
  250. #define RVPOLE 0x0800 /* Enable Receive Polarity Signal */
  251. #define RCVE 0x0400 /* Enable Receive Status Signal */
  252. #define JABE 0x0200 /* Enable Jabber Signal */
  253. #define COLE 0x0100 /* Enable Collision Signal */
  254. /*
  255. * Receive Descriptor Ring Entry
  256. */
  257. struct RDRE {
  258. volatile u_short RMD0; /* LADR[15:0] */
  259. volatile u_short RMD1; /* HADR[23:16] | Receive Flags */
  260. volatile u_short RMD2; /* Buffer Byte Count (two's complement) */
  261. volatile u_short RMD3; /* Message Byte Count */
  262. };
  263. /*
  264. * Transmit Descriptor Ring Entry
  265. */
  266. struct TDRE {
  267. volatile u_short TMD0; /* LADR[15:0] */
  268. volatile u_short TMD1; /* HADR[23:16] | Transmit Flags */
  269. volatile u_short TMD2; /* Buffer Byte Count (two's complement) */
  270. volatile u_short TMD3; /* Error Flags */
  271. };
  272. /*
  273. * Receive Flags
  274. */
  275. #define RF_OWN 0x0080 /* PCnet-ISA controller owns the descriptor */
  276. #define RF_ERR 0x0040 /* Error */
  277. #define RF_FRAM 0x0020 /* Framing Error */
  278. #define RF_OFLO 0x0010 /* Overflow Error */
  279. #define RF_CRC 0x0008 /* CRC Error */
  280. #define RF_BUFF 0x0004 /* Buffer Error */
  281. #define RF_STP 0x0002 /* Start of Packet */
  282. #define RF_ENP 0x0001 /* End of Packet */
  283. /*
  284. * Transmit Flags
  285. */
  286. #define TF_OWN 0x0080 /* PCnet-ISA controller owns the descriptor */
  287. #define TF_ERR 0x0040 /* Error */
  288. #define TF_ADD_FCS 0x0020 /* Controls FCS Generation */
  289. #define TF_MORE 0x0010 /* More than one retry needed */
  290. #define TF_ONE 0x0008 /* One retry needed */
  291. #define TF_DEF 0x0004 /* Deferred */
  292. #define TF_STP 0x0002 /* Start of Packet */
  293. #define TF_ENP 0x0001 /* End of Packet */
  294. /*
  295. * Error Flags
  296. */
  297. #define EF_BUFF 0x0080 /* Buffer Error */
  298. #define EF_UFLO 0x0040 /* Underflow Error */
  299. #define EF_LCOL 0x0010 /* Late Collision */
  300. #define EF_LCAR 0x0008 /* Loss of Carrier */
  301. #define EF_RTRY 0x0004 /* Retry Error */
  302. #define EF_TDR 0xff03 /* Time Domain Reflectometry */
  303. /*
  304. * MC68230 Parallel Interface/Timer
  305. */
  306. struct MC68230 {
  307. volatile u_char PGCR; /* Port General Control Register */
  308. u_char Pad1[1];
  309. volatile u_char PSRR; /* Port Service Request Register */
  310. u_char Pad2[1];
  311. volatile u_char PADDR; /* Port A Data Direction Register */
  312. u_char Pad3[1];
  313. volatile u_char PBDDR; /* Port B Data Direction Register */
  314. u_char Pad4[1];
  315. volatile u_char PCDDR; /* Port C Data Direction Register */
  316. u_char Pad5[1];
  317. volatile u_char PIVR; /* Port Interrupt Vector Register */
  318. u_char Pad6[1];
  319. volatile u_char PACR; /* Port A Control Register */
  320. u_char Pad7[1];
  321. volatile u_char PBCR; /* Port B Control Register */
  322. u_char Pad8[1];
  323. volatile u_char PADR; /* Port A Data Register */
  324. u_char Pad9[1];
  325. volatile u_char PBDR; /* Port B Data Register */
  326. u_char Pad10[1];
  327. volatile u_char PAAR; /* Port A Alternate Register */
  328. u_char Pad11[1];
  329. volatile u_char PBAR; /* Port B Alternate Register */
  330. u_char Pad12[1];
  331. volatile u_char PCDR; /* Port C Data Register */
  332. u_char Pad13[1];
  333. volatile u_char PSR; /* Port Status Register */
  334. u_char Pad14[5];
  335. volatile u_char TCR; /* Timer Control Register */
  336. u_char Pad15[1];
  337. volatile u_char TIVR; /* Timer Interrupt Vector Register */
  338. u_char Pad16[3];
  339. volatile u_char CPRH; /* Counter Preload Register (High) */
  340. u_char Pad17[1];
  341. volatile u_char CPRM; /* Counter Preload Register (Mid) */
  342. u_char Pad18[1];
  343. volatile u_char CPRL; /* Counter Preload Register (Low) */
  344. u_char Pad19[3];
  345. volatile u_char CNTRH; /* Count Register (High) */
  346. u_char Pad20[1];
  347. volatile u_char CNTRM; /* Count Register (Mid) */
  348. u_char Pad21[1];
  349. volatile u_char CNTRL; /* Count Register (Low) */
  350. u_char Pad22[1];
  351. volatile u_char TSR; /* Timer Status Register */
  352. u_char Pad23[11];
  353. };
  354. /*
  355. * Ariadne Expansion Board Structure
  356. */
  357. #define ARIADNE_LANCE 0x360
  358. #define ARIADNE_PIT 0x1000
  359. #define ARIADNE_BOOTPROM 0x4000 /* I guess it's here :-) */
  360. #define ARIADNE_BOOTPROM_SIZE 0x4000
  361. #define ARIADNE_RAM 0x8000 /* Always access WORDs!! */
  362. #define ARIADNE_RAM_SIZE 0x8000