cs89x0.h 16 KB

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  1. /* Copyright, 1988-1992, Russell Nelson, Crynwr Software
  2. This program is free software; you can redistribute it and/or modify
  3. it under the terms of the GNU General Public License as published by
  4. the Free Software Foundation, version 1.
  5. This program is distributed in the hope that it will be useful,
  6. but WITHOUT ANY WARRANTY; without even the implied warranty of
  7. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  8. GNU General Public License for more details.
  9. You should have received a copy of the GNU General Public License
  10. along with this program; if not, write to the Free Software
  11. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  12. */
  13. #define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
  14. /* offset 2h -> Model/Product Number */
  15. /* offset 3h -> Chip Revision Number */
  16. #define PP_ISAIOB 0x0020 /* IO base address */
  17. #define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */
  18. #define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */
  19. #define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */
  20. #define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */
  21. #define PP_ISASOF 0x0026 /* ISA DMA offset */
  22. #define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */
  23. #define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */
  24. #define PP_CS8900_ISAMemB 0x002C /* Memory base */
  25. #define PP_CS8920_ISAMemB 0x0348 /* */
  26. #define PP_ISABootBase 0x0030 /* Boot Prom base */
  27. #define PP_ISABootMask 0x0034 /* Boot Prom Mask */
  28. /* EEPROM data and command registers */
  29. #define PP_EECMD 0x0040 /* NVR Interface Command register */
  30. #define PP_EEData 0x0042 /* NVR Interface Data Register */
  31. #define PP_DebugReg 0x0044 /* Debug Register */
  32. #define PP_RxCFG 0x0102 /* Rx Bus config */
  33. #define PP_RxCTL 0x0104 /* Receive Control Register */
  34. #define PP_TxCFG 0x0106 /* Transmit Config Register */
  35. #define PP_TxCMD 0x0108 /* Transmit Command Register */
  36. #define PP_BufCFG 0x010A /* Bus configuration Register */
  37. #define PP_LineCTL 0x0112 /* Line Config Register */
  38. #define PP_SelfCTL 0x0114 /* Self Command Register */
  39. #define PP_BusCTL 0x0116 /* ISA bus control Register */
  40. #define PP_TestCTL 0x0118 /* Test Register */
  41. #define PP_AutoNegCTL 0x011C /* Auto Negotiation Ctrl */
  42. #define PP_ISQ 0x0120 /* Interrupt Status */
  43. #define PP_RxEvent 0x0124 /* Rx Event Register */
  44. #define PP_TxEvent 0x0128 /* Tx Event Register */
  45. #define PP_BufEvent 0x012C /* Bus Event Register */
  46. #define PP_RxMiss 0x0130 /* Receive Miss Count */
  47. #define PP_TxCol 0x0132 /* Transmit Collision Count */
  48. #define PP_LineST 0x0134 /* Line State Register */
  49. #define PP_SelfST 0x0136 /* Self State register */
  50. #define PP_BusST 0x0138 /* Bus Status */
  51. #define PP_TDR 0x013C /* Time Domain Reflectometry */
  52. #define PP_AutoNegST 0x013E /* Auto Neg Status */
  53. #define PP_TxCommand 0x0144 /* Tx Command */
  54. #define PP_TxLength 0x0146 /* Tx Length */
  55. #define PP_LAF 0x0150 /* Hash Table */
  56. #define PP_IA 0x0158 /* Physical Address Register */
  57. #define PP_RxStatus 0x0400 /* Receive start of frame */
  58. #define PP_RxLength 0x0402 /* Receive Length of frame */
  59. #define PP_RxFrame 0x0404 /* Receive frame pointer */
  60. #define PP_TxFrame 0x0A00 /* Transmit frame pointer */
  61. /* Primary I/O Base Address. If no I/O base is supplied by the user, then this */
  62. /* can be used as the default I/O base to access the PacketPage Area. */
  63. #define DEFAULTIOBASE 0x0300
  64. #define FIRST_IO 0x020C /* First I/O port to check */
  65. #define LAST_IO 0x037C /* Last I/O port to check (+10h) */
  66. #define ADD_MASK 0x3000 /* Mask it use of the ADD_PORT register */
  67. #define ADD_SIG 0x3000 /* Expected ID signature */
  68. /* On Macs, we only need use the ISA I/O stuff until we do MEMORY_ON */
  69. #ifdef CONFIG_MAC
  70. #define LCSLOTBASE 0xfee00000
  71. #define MMIOBASE 0x40000
  72. #endif
  73. #define CHIP_EISA_ID_SIG 0x630E /* Product ID Code for Crystal Chip (CS8900 spec 4.3) */
  74. #define CHIP_EISA_ID_SIG_STR "0x630E"
  75. #ifdef IBMEIPKT
  76. #define EISA_ID_SIG 0x4D24 /* IBM */
  77. #define PART_NO_SIG 0x1010 /* IBM */
  78. #define MONGOOSE_BIT 0x0000 /* IBM */
  79. #else
  80. #define EISA_ID_SIG 0x630E /* PnP Vendor ID (same as chip id for Crystal board) */
  81. #define PART_NO_SIG 0x4000 /* ID code CS8920 board (PnP Vendor Product code) */
  82. #define MONGOOSE_BIT 0x2000 /* PART_NO_SIG + MONGOOSE_BUT => ID of mongoose */
  83. #endif
  84. #define PRODUCT_ID_ADD 0x0002 /* Address of product ID */
  85. /* Mask to find out the types of registers */
  86. #define REG_TYPE_MASK 0x001F
  87. /* Eeprom Commands */
  88. #define ERSE_WR_ENBL 0x00F0
  89. #define ERSE_WR_DISABLE 0x0000
  90. /* Defines Control/Config register quintuplet numbers */
  91. #define RX_BUF_CFG 0x0003
  92. #define RX_CONTROL 0x0005
  93. #define TX_CFG 0x0007
  94. #define TX_COMMAND 0x0009
  95. #define BUF_CFG 0x000B
  96. #define LINE_CONTROL 0x0013
  97. #define SELF_CONTROL 0x0015
  98. #define BUS_CONTROL 0x0017
  99. #define TEST_CONTROL 0x0019
  100. /* Defines Status/Count registers quintuplet numbers */
  101. #define RX_EVENT 0x0004
  102. #define TX_EVENT 0x0008
  103. #define BUF_EVENT 0x000C
  104. #define RX_MISS_COUNT 0x0010
  105. #define TX_COL_COUNT 0x0012
  106. #define LINE_STATUS 0x0014
  107. #define SELF_STATUS 0x0016
  108. #define BUS_STATUS 0x0018
  109. #define TDR 0x001C
  110. /* PP_RxCFG - Receive Configuration and Interrupt Mask bit definition - Read/write */
  111. #define SKIP_1 0x0040
  112. #define RX_STREAM_ENBL 0x0080
  113. #define RX_OK_ENBL 0x0100
  114. #define RX_DMA_ONLY 0x0200
  115. #define AUTO_RX_DMA 0x0400
  116. #define BUFFER_CRC 0x0800
  117. #define RX_CRC_ERROR_ENBL 0x1000
  118. #define RX_RUNT_ENBL 0x2000
  119. #define RX_EXTRA_DATA_ENBL 0x4000
  120. /* PP_RxCTL - Receive Control bit definition - Read/write */
  121. #define RX_IA_HASH_ACCEPT 0x0040
  122. #define RX_PROM_ACCEPT 0x0080
  123. #define RX_OK_ACCEPT 0x0100
  124. #define RX_MULTCAST_ACCEPT 0x0200
  125. #define RX_IA_ACCEPT 0x0400
  126. #define RX_BROADCAST_ACCEPT 0x0800
  127. #define RX_BAD_CRC_ACCEPT 0x1000
  128. #define RX_RUNT_ACCEPT 0x2000
  129. #define RX_EXTRA_DATA_ACCEPT 0x4000
  130. #define RX_ALL_ACCEPT (RX_PROM_ACCEPT|RX_BAD_CRC_ACCEPT|RX_RUNT_ACCEPT|RX_EXTRA_DATA_ACCEPT)
  131. /* Default receive mode - individually addressed, broadcast, and error free */
  132. #define DEF_RX_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT)
  133. /* PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write */
  134. #define TX_LOST_CRS_ENBL 0x0040
  135. #define TX_SQE_ERROR_ENBL 0x0080
  136. #define TX_OK_ENBL 0x0100
  137. #define TX_LATE_COL_ENBL 0x0200
  138. #define TX_JBR_ENBL 0x0400
  139. #define TX_ANY_COL_ENBL 0x0800
  140. #define TX_16_COL_ENBL 0x8000
  141. /* PP_TxCMD - Transmit Command bit definition - Read-only */
  142. #define TX_START_4_BYTES 0x0000
  143. #define TX_START_64_BYTES 0x0040
  144. #define TX_START_128_BYTES 0x0080
  145. #define TX_START_ALL_BYTES 0x00C0
  146. #define TX_FORCE 0x0100
  147. #define TX_ONE_COL 0x0200
  148. #define TX_TWO_PART_DEFF_DISABLE 0x0400
  149. #define TX_NO_CRC 0x1000
  150. #define TX_RUNT 0x2000
  151. /* PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write */
  152. #define GENERATE_SW_INTERRUPT 0x0040
  153. #define RX_DMA_ENBL 0x0080
  154. #define READY_FOR_TX_ENBL 0x0100
  155. #define TX_UNDERRUN_ENBL 0x0200
  156. #define RX_MISS_ENBL 0x0400
  157. #define RX_128_BYTE_ENBL 0x0800
  158. #define TX_COL_COUNT_OVRFLOW_ENBL 0x1000
  159. #define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000
  160. #define RX_DEST_MATCH_ENBL 0x8000
  161. /* PP_LineCTL - Line Control bit definition - Read/write */
  162. #define SERIAL_RX_ON 0x0040
  163. #define SERIAL_TX_ON 0x0080
  164. #define AUI_ONLY 0x0100
  165. #define AUTO_AUI_10BASET 0x0200
  166. #define MODIFIED_BACKOFF 0x0800
  167. #define NO_AUTO_POLARITY 0x1000
  168. #define TWO_PART_DEFDIS 0x2000
  169. #define LOW_RX_SQUELCH 0x4000
  170. /* PP_SelfCTL - Software Self Control bit definition - Read/write */
  171. #define POWER_ON_RESET 0x0040
  172. #define SW_STOP 0x0100
  173. #define SLEEP_ON 0x0200
  174. #define AUTO_WAKEUP 0x0400
  175. #define HCB0_ENBL 0x1000
  176. #define HCB1_ENBL 0x2000
  177. #define HCB0 0x4000
  178. #define HCB1 0x8000
  179. /* PP_BusCTL - ISA Bus Control bit definition - Read/write */
  180. #define RESET_RX_DMA 0x0040
  181. #define MEMORY_ON 0x0400
  182. #define DMA_BURST_MODE 0x0800
  183. #define IO_CHANNEL_READY_ON 0x1000
  184. #define RX_DMA_SIZE_64K 0x2000
  185. #define ENABLE_IRQ 0x8000
  186. /* PP_TestCTL - Test Control bit definition - Read/write */
  187. #define LINK_OFF 0x0080
  188. #define ENDEC_LOOPBACK 0x0200
  189. #define AUI_LOOPBACK 0x0400
  190. #define BACKOFF_OFF 0x0800
  191. #define FDX_8900 0x4000
  192. #define FAST_TEST 0x8000
  193. /* PP_RxEvent - Receive Event Bit definition - Read-only */
  194. #define RX_IA_HASHED 0x0040
  195. #define RX_DRIBBLE 0x0080
  196. #define RX_OK 0x0100
  197. #define RX_HASHED 0x0200
  198. #define RX_IA 0x0400
  199. #define RX_BROADCAST 0x0800
  200. #define RX_CRC_ERROR 0x1000
  201. #define RX_RUNT 0x2000
  202. #define RX_EXTRA_DATA 0x4000
  203. #define HASH_INDEX_MASK 0x0FC00
  204. /* PP_TxEvent - Transmit Event Bit definition - Read-only */
  205. #define TX_LOST_CRS 0x0040
  206. #define TX_SQE_ERROR 0x0080
  207. #define TX_OK 0x0100
  208. #define TX_LATE_COL 0x0200
  209. #define TX_JBR 0x0400
  210. #define TX_16_COL 0x8000
  211. #define TX_SEND_OK_BITS (TX_OK|TX_LOST_CRS)
  212. #define TX_COL_COUNT_MASK 0x7800
  213. /* PP_BufEvent - Buffer Event Bit definition - Read-only */
  214. #define SW_INTERRUPT 0x0040
  215. #define RX_DMA 0x0080
  216. #define READY_FOR_TX 0x0100
  217. #define TX_UNDERRUN 0x0200
  218. #define RX_MISS 0x0400
  219. #define RX_128_BYTE 0x0800
  220. #define TX_COL_OVRFLW 0x1000
  221. #define RX_MISS_OVRFLW 0x2000
  222. #define RX_DEST_MATCH 0x8000
  223. /* PP_LineST - Ethernet Line Status bit definition - Read-only */
  224. #define LINK_OK 0x0080
  225. #define AUI_ON 0x0100
  226. #define TENBASET_ON 0x0200
  227. #define POLARITY_OK 0x1000
  228. #define CRS_OK 0x4000
  229. /* PP_SelfST - Chip Software Status bit definition */
  230. #define ACTIVE_33V 0x0040
  231. #define INIT_DONE 0x0080
  232. #define SI_BUSY 0x0100
  233. #define EEPROM_PRESENT 0x0200
  234. #define EEPROM_OK 0x0400
  235. #define EL_PRESENT 0x0800
  236. #define EE_SIZE_64 0x1000
  237. /* PP_BusST - ISA Bus Status bit definition */
  238. #define TX_BID_ERROR 0x0080
  239. #define READY_FOR_TX_NOW 0x0100
  240. /* PP_AutoNegCTL - Auto Negotiation Control bit definition */
  241. #define RE_NEG_NOW 0x0040
  242. #define ALLOW_FDX 0x0080
  243. #define AUTO_NEG_ENABLE 0x0100
  244. #define NLP_ENABLE 0x0200
  245. #define FORCE_FDX 0x8000
  246. #define AUTO_NEG_BITS (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE)
  247. #define AUTO_NEG_MASK (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE|ALLOW_FDX|RE_NEG_NOW)
  248. /* PP_AutoNegST - Auto Negotiation Status bit definition */
  249. #define AUTO_NEG_BUSY 0x0080
  250. #define FLP_LINK 0x0100
  251. #define FLP_LINK_GOOD 0x0800
  252. #define LINK_FAULT 0x1000
  253. #define HDX_ACTIVE 0x4000
  254. #define FDX_ACTIVE 0x8000
  255. /* The following block defines the ISQ event types */
  256. #define ISQ_RECEIVER_EVENT 0x04
  257. #define ISQ_TRANSMITTER_EVENT 0x08
  258. #define ISQ_BUFFER_EVENT 0x0c
  259. #define ISQ_RX_MISS_EVENT 0x10
  260. #define ISQ_TX_COL_EVENT 0x12
  261. #define ISQ_EVENT_MASK 0x003F /* ISQ mask to find out type of event */
  262. #define ISQ_HIST 16 /* small history buffer */
  263. #define AUTOINCREMENT 0x8000 /* Bit mask to set bit-15 for autoincrement */
  264. #define TXRXBUFSIZE 0x0600
  265. #define RXDMABUFSIZE 0x8000
  266. #define RXDMASIZE 0x4000
  267. #define TXRX_LENGTH_MASK 0x07FF
  268. /* rx options bits */
  269. #define RCV_WITH_RXON 1 /* Set SerRx ON */
  270. #define RCV_COUNTS 2 /* Use Framecnt1 */
  271. #define RCV_PONG 4 /* Pong respondent */
  272. #define RCV_DONG 8 /* Dong operation */
  273. #define RCV_POLLING 0x10 /* Poll RxEvent */
  274. #define RCV_ISQ 0x20 /* Use ISQ, int */
  275. #define RCV_AUTO_DMA 0x100 /* Set AutoRxDMAE */
  276. #define RCV_DMA 0x200 /* Set RxDMA only */
  277. #define RCV_DMA_ALL 0x400 /* Copy all DMA'ed */
  278. #define RCV_FIXED_DATA 0x800 /* Every frame same */
  279. #define RCV_IO 0x1000 /* Use ISA IO only */
  280. #define RCV_MEMORY 0x2000 /* Use ISA Memory */
  281. #define RAM_SIZE 0x1000 /* The card has 4k bytes or RAM */
  282. #define PKT_START PP_TxFrame /* Start of packet RAM */
  283. #define RX_FRAME_PORT 0x0000
  284. #define TX_FRAME_PORT RX_FRAME_PORT
  285. #define TX_CMD_PORT 0x0004
  286. #define TX_NOW 0x0000 /* Tx packet after 5 bytes copied */
  287. #define TX_AFTER_381 0x0040 /* Tx packet after 381 bytes copied */
  288. #define TX_AFTER_ALL 0x00c0 /* Tx packet after all bytes copied */
  289. #define TX_LEN_PORT 0x0006
  290. #define ISQ_PORT 0x0008
  291. #define ADD_PORT 0x000A
  292. #define DATA_PORT 0x000C
  293. #define EEPROM_WRITE_EN 0x00F0
  294. #define EEPROM_WRITE_DIS 0x0000
  295. #define EEPROM_WRITE_CMD 0x0100
  296. #define EEPROM_READ_CMD 0x0200
  297. /* Receive Header */
  298. /* Description of header of each packet in receive area of memory */
  299. #define RBUF_EVENT_LOW 0 /* Low byte of RxEvent - status of received frame */
  300. #define RBUF_EVENT_HIGH 1 /* High byte of RxEvent - status of received frame */
  301. #define RBUF_LEN_LOW 2 /* Length of received data - low byte */
  302. #define RBUF_LEN_HI 3 /* Length of received data - high byte */
  303. #define RBUF_HEAD_LEN 4 /* Length of this header */
  304. #define CHIP_READ 0x1 /* Used to mark state of the repins code (chip or dma) */
  305. #define DMA_READ 0x2 /* Used to mark state of the repins code (chip or dma) */
  306. /* for bios scan */
  307. /* */
  308. #ifdef CSDEBUG
  309. /* use these values for debugging bios scan */
  310. #define BIOS_START_SEG 0x00000
  311. #define BIOS_OFFSET_INC 0x0010
  312. #else
  313. #define BIOS_START_SEG 0x0c000
  314. #define BIOS_OFFSET_INC 0x0200
  315. #endif
  316. #define BIOS_LAST_OFFSET 0x0fc00
  317. /* Byte offsets into the EEPROM configuration buffer */
  318. #define ISA_CNF_OFFSET 0x6
  319. #define TX_CTL_OFFSET (ISA_CNF_OFFSET + 8) /* 8900 eeprom */
  320. #define AUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 8) /* 8920 eeprom */
  321. /* the assumption here is that the bits in the eeprom are generally */
  322. /* in the same position as those in the autonegctl register. */
  323. /* Of course the IMM bit is not in that register so it must be */
  324. /* masked out */
  325. #define EE_FORCE_FDX 0x8000
  326. #define EE_NLP_ENABLE 0x0200
  327. #define EE_AUTO_NEG_ENABLE 0x0100
  328. #define EE_ALLOW_FDX 0x0080
  329. #define EE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX|EE_NLP_ENABLE|EE_AUTO_NEG_ENABLE|EE_ALLOW_FDX)
  330. #define IMM_BIT 0x0040 /* ignore missing media */
  331. #define ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2)
  332. #define A_CNF_10B_T 0x0001
  333. #define A_CNF_AUI 0x0002
  334. #define A_CNF_10B_2 0x0004
  335. #define A_CNF_MEDIA_TYPE 0x0070
  336. #define A_CNF_MEDIA_AUTO 0x0070
  337. #define A_CNF_MEDIA_10B_T 0x0020
  338. #define A_CNF_MEDIA_AUI 0x0040
  339. #define A_CNF_MEDIA_10B_2 0x0010
  340. #define A_CNF_DC_DC_POLARITY 0x0080
  341. #define A_CNF_NO_AUTO_POLARITY 0x2000
  342. #define A_CNF_LOW_RX_SQUELCH 0x4000
  343. #define A_CNF_EXTND_10B_2 0x8000
  344. #define PACKET_PAGE_OFFSET 0x8
  345. /* Bit definitions for the ISA configuration word from the EEPROM */
  346. #define INT_NO_MASK 0x000F
  347. #define DMA_NO_MASK 0x0070
  348. #define ISA_DMA_SIZE 0x0200
  349. #define ISA_AUTO_RxDMA 0x0400
  350. #define ISA_RxDMA 0x0800
  351. #define DMA_BURST 0x1000
  352. #define STREAM_TRANSFER 0x2000
  353. #define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA)
  354. /* DMA controller registers */
  355. #define DMA_BASE 0x00 /* DMA controller base */
  356. #define DMA_BASE_2 0x0C0 /* DMA controller base */
  357. #define DMA_STAT 0x0D0 /* DMA controller status register */
  358. #define DMA_MASK 0x0D4 /* DMA controller mask register */
  359. #define DMA_MODE 0x0D6 /* DMA controller mode register */
  360. #define DMA_RESETFF 0x0D8 /* DMA controller first/last flip flop */
  361. /* DMA data */
  362. #define DMA_DISABLE 0x04 /* Disable channel n */
  363. #define DMA_ENABLE 0x00 /* Enable channel n */
  364. /* Demand transfers, incr. address, auto init, writes, ch. n */
  365. #define DMA_RX_MODE 0x14
  366. /* Demand transfers, incr. address, auto init, reads, ch. n */
  367. #define DMA_TX_MODE 0x18
  368. #define DMA_SIZE (16*1024) /* Size of dma buffer - 16k */
  369. #define CS8900 0x0000
  370. #define CS8920 0x4000
  371. #define CS8920M 0x6000
  372. #define REVISON_BITS 0x1F00
  373. #define EEVER_NUMBER 0x12
  374. #define CHKSUM_LEN 0x14
  375. #define CHKSUM_VAL 0x0000
  376. #define START_EEPROM_DATA 0x001c /* Offset into eeprom for start of data */
  377. #define IRQ_MAP_EEPROM_DATA 0x0046 /* Offset into eeprom for the IRQ map */
  378. #define IRQ_MAP_LEN 0x0004 /* No of bytes to read for the IRQ map */
  379. #define PNP_IRQ_FRMT 0x0022 /* PNP small item IRQ format */
  380. #define CS8900_IRQ_MAP 0x1c20 /* This IRQ map is fixed */
  381. #define CS8920_NO_INTS 0x0F /* Max CS8920 interrupt select # */
  382. #define PNP_ADD_PORT 0x0279
  383. #define PNP_WRITE_PORT 0x0A79
  384. #define GET_PNP_ISA_STRUCT 0x40
  385. #define PNP_ISA_STRUCT_LEN 0x06
  386. #define PNP_CSN_CNT_OFF 0x01
  387. #define PNP_RD_PORT_OFF 0x02
  388. #define PNP_FUNCTION_OK 0x00
  389. #define PNP_WAKE 0x03
  390. #define PNP_RSRC_DATA 0x04
  391. #define PNP_RSRC_READY 0x01
  392. #define PNP_STATUS 0x05
  393. #define PNP_ACTIVATE 0x30
  394. #define PNP_CNF_IO_H 0x60
  395. #define PNP_CNF_IO_L 0x61
  396. #define PNP_CNF_INT 0x70
  397. #define PNP_CNF_DMA 0x74
  398. #define PNP_CNF_MEM 0x48
  399. #define BIT0 1
  400. #define BIT15 0x8000