ep93xx_eth.c 20 KB

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  1. /*
  2. * EP93xx ethernet network device driver
  3. * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
  4. * Dedicated to Marija Kulikova.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. */
  11. #define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__
  12. #include <linux/dma-mapping.h>
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/netdevice.h>
  16. #include <linux/mii.h>
  17. #include <linux/etherdevice.h>
  18. #include <linux/ethtool.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/moduleparam.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/delay.h>
  23. #include <linux/io.h>
  24. #include <linux/slab.h>
  25. #include <mach/hardware.h>
  26. #define DRV_MODULE_NAME "ep93xx-eth"
  27. #define DRV_MODULE_VERSION "0.1"
  28. #define RX_QUEUE_ENTRIES 64
  29. #define TX_QUEUE_ENTRIES 8
  30. #define MAX_PKT_SIZE 2044
  31. #define PKT_BUF_SIZE 2048
  32. #define REG_RXCTL 0x0000
  33. #define REG_RXCTL_DEFAULT 0x00073800
  34. #define REG_TXCTL 0x0004
  35. #define REG_TXCTL_ENABLE 0x00000001
  36. #define REG_MIICMD 0x0010
  37. #define REG_MIICMD_READ 0x00008000
  38. #define REG_MIICMD_WRITE 0x00004000
  39. #define REG_MIIDATA 0x0014
  40. #define REG_MIISTS 0x0018
  41. #define REG_MIISTS_BUSY 0x00000001
  42. #define REG_SELFCTL 0x0020
  43. #define REG_SELFCTL_RESET 0x00000001
  44. #define REG_INTEN 0x0024
  45. #define REG_INTEN_TX 0x00000008
  46. #define REG_INTEN_RX 0x00000007
  47. #define REG_INTSTSP 0x0028
  48. #define REG_INTSTS_TX 0x00000008
  49. #define REG_INTSTS_RX 0x00000004
  50. #define REG_INTSTSC 0x002c
  51. #define REG_AFP 0x004c
  52. #define REG_INDAD0 0x0050
  53. #define REG_INDAD1 0x0051
  54. #define REG_INDAD2 0x0052
  55. #define REG_INDAD3 0x0053
  56. #define REG_INDAD4 0x0054
  57. #define REG_INDAD5 0x0055
  58. #define REG_GIINTMSK 0x0064
  59. #define REG_GIINTMSK_ENABLE 0x00008000
  60. #define REG_BMCTL 0x0080
  61. #define REG_BMCTL_ENABLE_TX 0x00000100
  62. #define REG_BMCTL_ENABLE_RX 0x00000001
  63. #define REG_BMSTS 0x0084
  64. #define REG_BMSTS_RX_ACTIVE 0x00000008
  65. #define REG_RXDQBADD 0x0090
  66. #define REG_RXDQBLEN 0x0094
  67. #define REG_RXDCURADD 0x0098
  68. #define REG_RXDENQ 0x009c
  69. #define REG_RXSTSQBADD 0x00a0
  70. #define REG_RXSTSQBLEN 0x00a4
  71. #define REG_RXSTSQCURADD 0x00a8
  72. #define REG_RXSTSENQ 0x00ac
  73. #define REG_TXDQBADD 0x00b0
  74. #define REG_TXDQBLEN 0x00b4
  75. #define REG_TXDQCURADD 0x00b8
  76. #define REG_TXDENQ 0x00bc
  77. #define REG_TXSTSQBADD 0x00c0
  78. #define REG_TXSTSQBLEN 0x00c4
  79. #define REG_TXSTSQCURADD 0x00c8
  80. #define REG_MAXFRMLEN 0x00e8
  81. struct ep93xx_rdesc
  82. {
  83. u32 buf_addr;
  84. u32 rdesc1;
  85. };
  86. #define RDESC1_NSOF 0x80000000
  87. #define RDESC1_BUFFER_INDEX 0x7fff0000
  88. #define RDESC1_BUFFER_LENGTH 0x0000ffff
  89. struct ep93xx_rstat
  90. {
  91. u32 rstat0;
  92. u32 rstat1;
  93. };
  94. #define RSTAT0_RFP 0x80000000
  95. #define RSTAT0_RWE 0x40000000
  96. #define RSTAT0_EOF 0x20000000
  97. #define RSTAT0_EOB 0x10000000
  98. #define RSTAT0_AM 0x00c00000
  99. #define RSTAT0_RX_ERR 0x00200000
  100. #define RSTAT0_OE 0x00100000
  101. #define RSTAT0_FE 0x00080000
  102. #define RSTAT0_RUNT 0x00040000
  103. #define RSTAT0_EDATA 0x00020000
  104. #define RSTAT0_CRCE 0x00010000
  105. #define RSTAT0_CRCI 0x00008000
  106. #define RSTAT0_HTI 0x00003f00
  107. #define RSTAT1_RFP 0x80000000
  108. #define RSTAT1_BUFFER_INDEX 0x7fff0000
  109. #define RSTAT1_FRAME_LENGTH 0x0000ffff
  110. struct ep93xx_tdesc
  111. {
  112. u32 buf_addr;
  113. u32 tdesc1;
  114. };
  115. #define TDESC1_EOF 0x80000000
  116. #define TDESC1_BUFFER_INDEX 0x7fff0000
  117. #define TDESC1_BUFFER_ABORT 0x00008000
  118. #define TDESC1_BUFFER_LENGTH 0x00000fff
  119. struct ep93xx_tstat
  120. {
  121. u32 tstat0;
  122. };
  123. #define TSTAT0_TXFP 0x80000000
  124. #define TSTAT0_TXWE 0x40000000
  125. #define TSTAT0_FA 0x20000000
  126. #define TSTAT0_LCRS 0x10000000
  127. #define TSTAT0_OW 0x04000000
  128. #define TSTAT0_TXU 0x02000000
  129. #define TSTAT0_ECOLL 0x01000000
  130. #define TSTAT0_NCOLL 0x001f0000
  131. #define TSTAT0_BUFFER_INDEX 0x00007fff
  132. struct ep93xx_descs
  133. {
  134. struct ep93xx_rdesc rdesc[RX_QUEUE_ENTRIES];
  135. struct ep93xx_tdesc tdesc[TX_QUEUE_ENTRIES];
  136. struct ep93xx_rstat rstat[RX_QUEUE_ENTRIES];
  137. struct ep93xx_tstat tstat[TX_QUEUE_ENTRIES];
  138. };
  139. struct ep93xx_priv
  140. {
  141. struct resource *res;
  142. void __iomem *base_addr;
  143. int irq;
  144. struct ep93xx_descs *descs;
  145. dma_addr_t descs_dma_addr;
  146. void *rx_buf[RX_QUEUE_ENTRIES];
  147. void *tx_buf[TX_QUEUE_ENTRIES];
  148. spinlock_t rx_lock;
  149. unsigned int rx_pointer;
  150. unsigned int tx_clean_pointer;
  151. unsigned int tx_pointer;
  152. spinlock_t tx_pending_lock;
  153. unsigned int tx_pending;
  154. struct net_device *dev;
  155. struct napi_struct napi;
  156. struct mii_if_info mii;
  157. u8 mdc_divisor;
  158. };
  159. #define rdb(ep, off) __raw_readb((ep)->base_addr + (off))
  160. #define rdw(ep, off) __raw_readw((ep)->base_addr + (off))
  161. #define rdl(ep, off) __raw_readl((ep)->base_addr + (off))
  162. #define wrb(ep, off, val) __raw_writeb((val), (ep)->base_addr + (off))
  163. #define wrw(ep, off, val) __raw_writew((val), (ep)->base_addr + (off))
  164. #define wrl(ep, off, val) __raw_writel((val), (ep)->base_addr + (off))
  165. static int ep93xx_mdio_read(struct net_device *dev, int phy_id, int reg)
  166. {
  167. struct ep93xx_priv *ep = netdev_priv(dev);
  168. int data;
  169. int i;
  170. wrl(ep, REG_MIICMD, REG_MIICMD_READ | (phy_id << 5) | reg);
  171. for (i = 0; i < 10; i++) {
  172. if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
  173. break;
  174. msleep(1);
  175. }
  176. if (i == 10) {
  177. pr_info("mdio read timed out\n");
  178. data = 0xffff;
  179. } else {
  180. data = rdl(ep, REG_MIIDATA);
  181. }
  182. return data;
  183. }
  184. static void ep93xx_mdio_write(struct net_device *dev, int phy_id, int reg, int data)
  185. {
  186. struct ep93xx_priv *ep = netdev_priv(dev);
  187. int i;
  188. wrl(ep, REG_MIIDATA, data);
  189. wrl(ep, REG_MIICMD, REG_MIICMD_WRITE | (phy_id << 5) | reg);
  190. for (i = 0; i < 10; i++) {
  191. if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
  192. break;
  193. msleep(1);
  194. }
  195. if (i == 10)
  196. pr_info("mdio write timed out\n");
  197. }
  198. static int ep93xx_rx(struct net_device *dev, int processed, int budget)
  199. {
  200. struct ep93xx_priv *ep = netdev_priv(dev);
  201. while (processed < budget) {
  202. int entry;
  203. struct ep93xx_rstat *rstat;
  204. u32 rstat0;
  205. u32 rstat1;
  206. int length;
  207. struct sk_buff *skb;
  208. entry = ep->rx_pointer;
  209. rstat = ep->descs->rstat + entry;
  210. rstat0 = rstat->rstat0;
  211. rstat1 = rstat->rstat1;
  212. if (!(rstat0 & RSTAT0_RFP) || !(rstat1 & RSTAT1_RFP))
  213. break;
  214. rstat->rstat0 = 0;
  215. rstat->rstat1 = 0;
  216. if (!(rstat0 & RSTAT0_EOF))
  217. pr_crit("not end-of-frame %.8x %.8x\n", rstat0, rstat1);
  218. if (!(rstat0 & RSTAT0_EOB))
  219. pr_crit("not end-of-buffer %.8x %.8x\n", rstat0, rstat1);
  220. if ((rstat1 & RSTAT1_BUFFER_INDEX) >> 16 != entry)
  221. pr_crit("entry mismatch %.8x %.8x\n", rstat0, rstat1);
  222. if (!(rstat0 & RSTAT0_RWE)) {
  223. dev->stats.rx_errors++;
  224. if (rstat0 & RSTAT0_OE)
  225. dev->stats.rx_fifo_errors++;
  226. if (rstat0 & RSTAT0_FE)
  227. dev->stats.rx_frame_errors++;
  228. if (rstat0 & (RSTAT0_RUNT | RSTAT0_EDATA))
  229. dev->stats.rx_length_errors++;
  230. if (rstat0 & RSTAT0_CRCE)
  231. dev->stats.rx_crc_errors++;
  232. goto err;
  233. }
  234. length = rstat1 & RSTAT1_FRAME_LENGTH;
  235. if (length > MAX_PKT_SIZE) {
  236. pr_notice("invalid length %.8x %.8x\n", rstat0, rstat1);
  237. goto err;
  238. }
  239. /* Strip FCS. */
  240. if (rstat0 & RSTAT0_CRCI)
  241. length -= 4;
  242. skb = netdev_alloc_skb(dev, length + 2);
  243. if (likely(skb != NULL)) {
  244. struct ep93xx_rdesc *rxd = &ep->descs->rdesc[entry];
  245. skb_reserve(skb, 2);
  246. dma_sync_single_for_cpu(dev->dev.parent, rxd->buf_addr,
  247. length, DMA_FROM_DEVICE);
  248. skb_copy_to_linear_data(skb, ep->rx_buf[entry], length);
  249. dma_sync_single_for_device(dev->dev.parent,
  250. rxd->buf_addr, length,
  251. DMA_FROM_DEVICE);
  252. skb_put(skb, length);
  253. skb->protocol = eth_type_trans(skb, dev);
  254. netif_receive_skb(skb);
  255. dev->stats.rx_packets++;
  256. dev->stats.rx_bytes += length;
  257. } else {
  258. dev->stats.rx_dropped++;
  259. }
  260. err:
  261. ep->rx_pointer = (entry + 1) & (RX_QUEUE_ENTRIES - 1);
  262. processed++;
  263. }
  264. return processed;
  265. }
  266. static int ep93xx_have_more_rx(struct ep93xx_priv *ep)
  267. {
  268. struct ep93xx_rstat *rstat = ep->descs->rstat + ep->rx_pointer;
  269. return !!((rstat->rstat0 & RSTAT0_RFP) && (rstat->rstat1 & RSTAT1_RFP));
  270. }
  271. static int ep93xx_poll(struct napi_struct *napi, int budget)
  272. {
  273. struct ep93xx_priv *ep = container_of(napi, struct ep93xx_priv, napi);
  274. struct net_device *dev = ep->dev;
  275. int rx = 0;
  276. poll_some_more:
  277. rx = ep93xx_rx(dev, rx, budget);
  278. if (rx < budget) {
  279. int more = 0;
  280. spin_lock_irq(&ep->rx_lock);
  281. __napi_complete(napi);
  282. wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
  283. if (ep93xx_have_more_rx(ep)) {
  284. wrl(ep, REG_INTEN, REG_INTEN_TX);
  285. wrl(ep, REG_INTSTSP, REG_INTSTS_RX);
  286. more = 1;
  287. }
  288. spin_unlock_irq(&ep->rx_lock);
  289. if (more && napi_reschedule(napi))
  290. goto poll_some_more;
  291. }
  292. if (rx) {
  293. wrw(ep, REG_RXDENQ, rx);
  294. wrw(ep, REG_RXSTSENQ, rx);
  295. }
  296. return rx;
  297. }
  298. static int ep93xx_xmit(struct sk_buff *skb, struct net_device *dev)
  299. {
  300. struct ep93xx_priv *ep = netdev_priv(dev);
  301. struct ep93xx_tdesc *txd;
  302. int entry;
  303. if (unlikely(skb->len > MAX_PKT_SIZE)) {
  304. dev->stats.tx_dropped++;
  305. dev_kfree_skb(skb);
  306. return NETDEV_TX_OK;
  307. }
  308. entry = ep->tx_pointer;
  309. ep->tx_pointer = (ep->tx_pointer + 1) & (TX_QUEUE_ENTRIES - 1);
  310. txd = &ep->descs->tdesc[entry];
  311. txd->tdesc1 = TDESC1_EOF | (entry << 16) | (skb->len & 0xfff);
  312. dma_sync_single_for_cpu(dev->dev.parent, txd->buf_addr, skb->len,
  313. DMA_TO_DEVICE);
  314. skb_copy_and_csum_dev(skb, ep->tx_buf[entry]);
  315. dma_sync_single_for_device(dev->dev.parent, txd->buf_addr, skb->len,
  316. DMA_TO_DEVICE);
  317. dev_kfree_skb(skb);
  318. spin_lock_irq(&ep->tx_pending_lock);
  319. ep->tx_pending++;
  320. if (ep->tx_pending == TX_QUEUE_ENTRIES)
  321. netif_stop_queue(dev);
  322. spin_unlock_irq(&ep->tx_pending_lock);
  323. wrl(ep, REG_TXDENQ, 1);
  324. return NETDEV_TX_OK;
  325. }
  326. static void ep93xx_tx_complete(struct net_device *dev)
  327. {
  328. struct ep93xx_priv *ep = netdev_priv(dev);
  329. int wake;
  330. wake = 0;
  331. spin_lock(&ep->tx_pending_lock);
  332. while (1) {
  333. int entry;
  334. struct ep93xx_tstat *tstat;
  335. u32 tstat0;
  336. entry = ep->tx_clean_pointer;
  337. tstat = ep->descs->tstat + entry;
  338. tstat0 = tstat->tstat0;
  339. if (!(tstat0 & TSTAT0_TXFP))
  340. break;
  341. tstat->tstat0 = 0;
  342. if (tstat0 & TSTAT0_FA)
  343. pr_crit("frame aborted %.8x\n", tstat0);
  344. if ((tstat0 & TSTAT0_BUFFER_INDEX) != entry)
  345. pr_crit("entry mismatch %.8x\n", tstat0);
  346. if (tstat0 & TSTAT0_TXWE) {
  347. int length = ep->descs->tdesc[entry].tdesc1 & 0xfff;
  348. dev->stats.tx_packets++;
  349. dev->stats.tx_bytes += length;
  350. } else {
  351. dev->stats.tx_errors++;
  352. }
  353. if (tstat0 & TSTAT0_OW)
  354. dev->stats.tx_window_errors++;
  355. if (tstat0 & TSTAT0_TXU)
  356. dev->stats.tx_fifo_errors++;
  357. dev->stats.collisions += (tstat0 >> 16) & 0x1f;
  358. ep->tx_clean_pointer = (entry + 1) & (TX_QUEUE_ENTRIES - 1);
  359. if (ep->tx_pending == TX_QUEUE_ENTRIES)
  360. wake = 1;
  361. ep->tx_pending--;
  362. }
  363. spin_unlock(&ep->tx_pending_lock);
  364. if (wake)
  365. netif_wake_queue(dev);
  366. }
  367. static irqreturn_t ep93xx_irq(int irq, void *dev_id)
  368. {
  369. struct net_device *dev = dev_id;
  370. struct ep93xx_priv *ep = netdev_priv(dev);
  371. u32 status;
  372. status = rdl(ep, REG_INTSTSC);
  373. if (status == 0)
  374. return IRQ_NONE;
  375. if (status & REG_INTSTS_RX) {
  376. spin_lock(&ep->rx_lock);
  377. if (likely(napi_schedule_prep(&ep->napi))) {
  378. wrl(ep, REG_INTEN, REG_INTEN_TX);
  379. __napi_schedule(&ep->napi);
  380. }
  381. spin_unlock(&ep->rx_lock);
  382. }
  383. if (status & REG_INTSTS_TX)
  384. ep93xx_tx_complete(dev);
  385. return IRQ_HANDLED;
  386. }
  387. static void ep93xx_free_buffers(struct ep93xx_priv *ep)
  388. {
  389. struct device *dev = ep->dev->dev.parent;
  390. int i;
  391. for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
  392. dma_addr_t d;
  393. d = ep->descs->rdesc[i].buf_addr;
  394. if (d)
  395. dma_unmap_single(dev, d, PKT_BUF_SIZE, DMA_FROM_DEVICE);
  396. kfree(ep->rx_buf[i]);
  397. }
  398. for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
  399. dma_addr_t d;
  400. d = ep->descs->tdesc[i].buf_addr;
  401. if (d)
  402. dma_unmap_single(dev, d, PKT_BUF_SIZE, DMA_TO_DEVICE);
  403. kfree(ep->tx_buf[i]);
  404. }
  405. dma_free_coherent(dev, sizeof(struct ep93xx_descs), ep->descs,
  406. ep->descs_dma_addr);
  407. }
  408. static int ep93xx_alloc_buffers(struct ep93xx_priv *ep)
  409. {
  410. struct device *dev = ep->dev->dev.parent;
  411. int i;
  412. ep->descs = dma_alloc_coherent(dev, sizeof(struct ep93xx_descs),
  413. &ep->descs_dma_addr, GFP_KERNEL);
  414. if (ep->descs == NULL)
  415. return 1;
  416. for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
  417. void *buf;
  418. dma_addr_t d;
  419. buf = kmalloc(PKT_BUF_SIZE, GFP_KERNEL);
  420. if (buf == NULL)
  421. goto err;
  422. d = dma_map_single(dev, buf, PKT_BUF_SIZE, DMA_FROM_DEVICE);
  423. if (dma_mapping_error(dev, d)) {
  424. kfree(buf);
  425. goto err;
  426. }
  427. ep->rx_buf[i] = buf;
  428. ep->descs->rdesc[i].buf_addr = d;
  429. ep->descs->rdesc[i].rdesc1 = (i << 16) | PKT_BUF_SIZE;
  430. }
  431. for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
  432. void *buf;
  433. dma_addr_t d;
  434. buf = kmalloc(PKT_BUF_SIZE, GFP_KERNEL);
  435. if (buf == NULL)
  436. goto err;
  437. d = dma_map_single(dev, buf, PKT_BUF_SIZE, DMA_TO_DEVICE);
  438. if (dma_mapping_error(dev, d)) {
  439. kfree(buf);
  440. goto err;
  441. }
  442. ep->tx_buf[i] = buf;
  443. ep->descs->tdesc[i].buf_addr = d;
  444. }
  445. return 0;
  446. err:
  447. ep93xx_free_buffers(ep);
  448. return 1;
  449. }
  450. static int ep93xx_start_hw(struct net_device *dev)
  451. {
  452. struct ep93xx_priv *ep = netdev_priv(dev);
  453. unsigned long addr;
  454. int i;
  455. wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
  456. for (i = 0; i < 10; i++) {
  457. if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
  458. break;
  459. msleep(1);
  460. }
  461. if (i == 10) {
  462. pr_crit("hw failed to reset\n");
  463. return 1;
  464. }
  465. wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9));
  466. /* Does the PHY support preamble suppress? */
  467. if ((ep93xx_mdio_read(dev, ep->mii.phy_id, MII_BMSR) & 0x0040) != 0)
  468. wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9) | (1 << 8));
  469. /* Receive descriptor ring. */
  470. addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rdesc);
  471. wrl(ep, REG_RXDQBADD, addr);
  472. wrl(ep, REG_RXDCURADD, addr);
  473. wrw(ep, REG_RXDQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rdesc));
  474. /* Receive status ring. */
  475. addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rstat);
  476. wrl(ep, REG_RXSTSQBADD, addr);
  477. wrl(ep, REG_RXSTSQCURADD, addr);
  478. wrw(ep, REG_RXSTSQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rstat));
  479. /* Transmit descriptor ring. */
  480. addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tdesc);
  481. wrl(ep, REG_TXDQBADD, addr);
  482. wrl(ep, REG_TXDQCURADD, addr);
  483. wrw(ep, REG_TXDQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tdesc));
  484. /* Transmit status ring. */
  485. addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tstat);
  486. wrl(ep, REG_TXSTSQBADD, addr);
  487. wrl(ep, REG_TXSTSQCURADD, addr);
  488. wrw(ep, REG_TXSTSQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tstat));
  489. wrl(ep, REG_BMCTL, REG_BMCTL_ENABLE_TX | REG_BMCTL_ENABLE_RX);
  490. wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
  491. wrl(ep, REG_GIINTMSK, 0);
  492. for (i = 0; i < 10; i++) {
  493. if ((rdl(ep, REG_BMSTS) & REG_BMSTS_RX_ACTIVE) != 0)
  494. break;
  495. msleep(1);
  496. }
  497. if (i == 10) {
  498. pr_crit("hw failed to start\n");
  499. return 1;
  500. }
  501. wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES);
  502. wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES);
  503. wrb(ep, REG_INDAD0, dev->dev_addr[0]);
  504. wrb(ep, REG_INDAD1, dev->dev_addr[1]);
  505. wrb(ep, REG_INDAD2, dev->dev_addr[2]);
  506. wrb(ep, REG_INDAD3, dev->dev_addr[3]);
  507. wrb(ep, REG_INDAD4, dev->dev_addr[4]);
  508. wrb(ep, REG_INDAD5, dev->dev_addr[5]);
  509. wrl(ep, REG_AFP, 0);
  510. wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE);
  511. wrl(ep, REG_RXCTL, REG_RXCTL_DEFAULT);
  512. wrl(ep, REG_TXCTL, REG_TXCTL_ENABLE);
  513. return 0;
  514. }
  515. static void ep93xx_stop_hw(struct net_device *dev)
  516. {
  517. struct ep93xx_priv *ep = netdev_priv(dev);
  518. int i;
  519. wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
  520. for (i = 0; i < 10; i++) {
  521. if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
  522. break;
  523. msleep(1);
  524. }
  525. if (i == 10)
  526. pr_crit("hw failed to reset\n");
  527. }
  528. static int ep93xx_open(struct net_device *dev)
  529. {
  530. struct ep93xx_priv *ep = netdev_priv(dev);
  531. int err;
  532. if (ep93xx_alloc_buffers(ep))
  533. return -ENOMEM;
  534. napi_enable(&ep->napi);
  535. if (ep93xx_start_hw(dev)) {
  536. napi_disable(&ep->napi);
  537. ep93xx_free_buffers(ep);
  538. return -EIO;
  539. }
  540. spin_lock_init(&ep->rx_lock);
  541. ep->rx_pointer = 0;
  542. ep->tx_clean_pointer = 0;
  543. ep->tx_pointer = 0;
  544. spin_lock_init(&ep->tx_pending_lock);
  545. ep->tx_pending = 0;
  546. err = request_irq(ep->irq, ep93xx_irq, IRQF_SHARED, dev->name, dev);
  547. if (err) {
  548. napi_disable(&ep->napi);
  549. ep93xx_stop_hw(dev);
  550. ep93xx_free_buffers(ep);
  551. return err;
  552. }
  553. wrl(ep, REG_GIINTMSK, REG_GIINTMSK_ENABLE);
  554. netif_start_queue(dev);
  555. return 0;
  556. }
  557. static int ep93xx_close(struct net_device *dev)
  558. {
  559. struct ep93xx_priv *ep = netdev_priv(dev);
  560. napi_disable(&ep->napi);
  561. netif_stop_queue(dev);
  562. wrl(ep, REG_GIINTMSK, 0);
  563. free_irq(ep->irq, dev);
  564. ep93xx_stop_hw(dev);
  565. ep93xx_free_buffers(ep);
  566. return 0;
  567. }
  568. static int ep93xx_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  569. {
  570. struct ep93xx_priv *ep = netdev_priv(dev);
  571. struct mii_ioctl_data *data = if_mii(ifr);
  572. return generic_mii_ioctl(&ep->mii, data, cmd, NULL);
  573. }
  574. static void ep93xx_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  575. {
  576. strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
  577. strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
  578. }
  579. static int ep93xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  580. {
  581. struct ep93xx_priv *ep = netdev_priv(dev);
  582. return mii_ethtool_gset(&ep->mii, cmd);
  583. }
  584. static int ep93xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  585. {
  586. struct ep93xx_priv *ep = netdev_priv(dev);
  587. return mii_ethtool_sset(&ep->mii, cmd);
  588. }
  589. static int ep93xx_nway_reset(struct net_device *dev)
  590. {
  591. struct ep93xx_priv *ep = netdev_priv(dev);
  592. return mii_nway_restart(&ep->mii);
  593. }
  594. static u32 ep93xx_get_link(struct net_device *dev)
  595. {
  596. struct ep93xx_priv *ep = netdev_priv(dev);
  597. return mii_link_ok(&ep->mii);
  598. }
  599. static const struct ethtool_ops ep93xx_ethtool_ops = {
  600. .get_drvinfo = ep93xx_get_drvinfo,
  601. .get_settings = ep93xx_get_settings,
  602. .set_settings = ep93xx_set_settings,
  603. .nway_reset = ep93xx_nway_reset,
  604. .get_link = ep93xx_get_link,
  605. };
  606. static const struct net_device_ops ep93xx_netdev_ops = {
  607. .ndo_open = ep93xx_open,
  608. .ndo_stop = ep93xx_close,
  609. .ndo_start_xmit = ep93xx_xmit,
  610. .ndo_do_ioctl = ep93xx_ioctl,
  611. .ndo_validate_addr = eth_validate_addr,
  612. .ndo_change_mtu = eth_change_mtu,
  613. .ndo_set_mac_address = eth_mac_addr,
  614. };
  615. static struct net_device *ep93xx_dev_alloc(struct ep93xx_eth_data *data)
  616. {
  617. struct net_device *dev;
  618. dev = alloc_etherdev(sizeof(struct ep93xx_priv));
  619. if (dev == NULL)
  620. return NULL;
  621. memcpy(dev->dev_addr, data->dev_addr, ETH_ALEN);
  622. dev->ethtool_ops = &ep93xx_ethtool_ops;
  623. dev->netdev_ops = &ep93xx_netdev_ops;
  624. dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
  625. return dev;
  626. }
  627. static int ep93xx_eth_remove(struct platform_device *pdev)
  628. {
  629. struct net_device *dev;
  630. struct ep93xx_priv *ep;
  631. dev = platform_get_drvdata(pdev);
  632. if (dev == NULL)
  633. return 0;
  634. ep = netdev_priv(dev);
  635. /* @@@ Force down. */
  636. unregister_netdev(dev);
  637. ep93xx_free_buffers(ep);
  638. if (ep->base_addr != NULL)
  639. iounmap(ep->base_addr);
  640. if (ep->res != NULL) {
  641. release_resource(ep->res);
  642. kfree(ep->res);
  643. }
  644. free_netdev(dev);
  645. return 0;
  646. }
  647. static int ep93xx_eth_probe(struct platform_device *pdev)
  648. {
  649. struct ep93xx_eth_data *data;
  650. struct net_device *dev;
  651. struct ep93xx_priv *ep;
  652. struct resource *mem;
  653. int irq;
  654. int err;
  655. if (pdev == NULL)
  656. return -ENODEV;
  657. data = dev_get_platdata(&pdev->dev);
  658. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  659. irq = platform_get_irq(pdev, 0);
  660. if (!mem || irq < 0)
  661. return -ENXIO;
  662. dev = ep93xx_dev_alloc(data);
  663. if (dev == NULL) {
  664. err = -ENOMEM;
  665. goto err_out;
  666. }
  667. ep = netdev_priv(dev);
  668. ep->dev = dev;
  669. SET_NETDEV_DEV(dev, &pdev->dev);
  670. netif_napi_add(dev, &ep->napi, ep93xx_poll, 64);
  671. platform_set_drvdata(pdev, dev);
  672. ep->res = request_mem_region(mem->start, resource_size(mem),
  673. dev_name(&pdev->dev));
  674. if (ep->res == NULL) {
  675. dev_err(&pdev->dev, "Could not reserve memory region\n");
  676. err = -ENOMEM;
  677. goto err_out;
  678. }
  679. ep->base_addr = ioremap(mem->start, resource_size(mem));
  680. if (ep->base_addr == NULL) {
  681. dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
  682. err = -EIO;
  683. goto err_out;
  684. }
  685. ep->irq = irq;
  686. ep->mii.phy_id = data->phy_id;
  687. ep->mii.phy_id_mask = 0x1f;
  688. ep->mii.reg_num_mask = 0x1f;
  689. ep->mii.dev = dev;
  690. ep->mii.mdio_read = ep93xx_mdio_read;
  691. ep->mii.mdio_write = ep93xx_mdio_write;
  692. ep->mdc_divisor = 40; /* Max HCLK 100 MHz, min MDIO clk 2.5 MHz. */
  693. if (is_zero_ether_addr(dev->dev_addr))
  694. eth_hw_addr_random(dev);
  695. err = register_netdev(dev);
  696. if (err) {
  697. dev_err(&pdev->dev, "Failed to register netdev\n");
  698. goto err_out;
  699. }
  700. printk(KERN_INFO "%s: ep93xx on-chip ethernet, IRQ %d, %pM\n",
  701. dev->name, ep->irq, dev->dev_addr);
  702. return 0;
  703. err_out:
  704. ep93xx_eth_remove(pdev);
  705. return err;
  706. }
  707. static struct platform_driver ep93xx_eth_driver = {
  708. .probe = ep93xx_eth_probe,
  709. .remove = ep93xx_eth_remove,
  710. .driver = {
  711. .name = "ep93xx-eth",
  712. },
  713. };
  714. module_platform_driver(ep93xx_eth_driver);
  715. MODULE_LICENSE("GPL");
  716. MODULE_ALIAS("platform:ep93xx-eth");