ftmac100.c 31 KB

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  1. /*
  2. * Faraday FTMAC100 10/100 Ethernet
  3. *
  4. * (C) Copyright 2009-2011 Faraday Technology
  5. * Po-Yu Chuang <ratbert@faraday-tech.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  22. #include <linux/dma-mapping.h>
  23. #include <linux/etherdevice.h>
  24. #include <linux/ethtool.h>
  25. #include <linux/init.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/io.h>
  28. #include <linux/mii.h>
  29. #include <linux/module.h>
  30. #include <linux/netdevice.h>
  31. #include <linux/platform_device.h>
  32. #include "ftmac100.h"
  33. #define DRV_NAME "ftmac100"
  34. #define DRV_VERSION "0.2"
  35. #define RX_QUEUE_ENTRIES 128 /* must be power of 2 */
  36. #define TX_QUEUE_ENTRIES 16 /* must be power of 2 */
  37. #define MAX_PKT_SIZE 1518
  38. #define RX_BUF_SIZE 2044 /* must be smaller than 0x7ff */
  39. #if MAX_PKT_SIZE > 0x7ff
  40. #error invalid MAX_PKT_SIZE
  41. #endif
  42. #if RX_BUF_SIZE > 0x7ff || RX_BUF_SIZE > PAGE_SIZE
  43. #error invalid RX_BUF_SIZE
  44. #endif
  45. /******************************************************************************
  46. * private data
  47. *****************************************************************************/
  48. struct ftmac100_descs {
  49. struct ftmac100_rxdes rxdes[RX_QUEUE_ENTRIES];
  50. struct ftmac100_txdes txdes[TX_QUEUE_ENTRIES];
  51. };
  52. struct ftmac100 {
  53. struct resource *res;
  54. void __iomem *base;
  55. int irq;
  56. struct ftmac100_descs *descs;
  57. dma_addr_t descs_dma_addr;
  58. unsigned int rx_pointer;
  59. unsigned int tx_clean_pointer;
  60. unsigned int tx_pointer;
  61. unsigned int tx_pending;
  62. spinlock_t tx_lock;
  63. struct net_device *netdev;
  64. struct device *dev;
  65. struct napi_struct napi;
  66. struct mii_if_info mii;
  67. };
  68. static int ftmac100_alloc_rx_page(struct ftmac100 *priv,
  69. struct ftmac100_rxdes *rxdes, gfp_t gfp);
  70. /******************************************************************************
  71. * internal functions (hardware register access)
  72. *****************************************************************************/
  73. #define INT_MASK_ALL_ENABLED (FTMAC100_INT_RPKT_FINISH | \
  74. FTMAC100_INT_NORXBUF | \
  75. FTMAC100_INT_XPKT_OK | \
  76. FTMAC100_INT_XPKT_LOST | \
  77. FTMAC100_INT_RPKT_LOST | \
  78. FTMAC100_INT_AHB_ERR | \
  79. FTMAC100_INT_PHYSTS_CHG)
  80. #define INT_MASK_ALL_DISABLED 0
  81. static void ftmac100_enable_all_int(struct ftmac100 *priv)
  82. {
  83. iowrite32(INT_MASK_ALL_ENABLED, priv->base + FTMAC100_OFFSET_IMR);
  84. }
  85. static void ftmac100_disable_all_int(struct ftmac100 *priv)
  86. {
  87. iowrite32(INT_MASK_ALL_DISABLED, priv->base + FTMAC100_OFFSET_IMR);
  88. }
  89. static void ftmac100_set_rx_ring_base(struct ftmac100 *priv, dma_addr_t addr)
  90. {
  91. iowrite32(addr, priv->base + FTMAC100_OFFSET_RXR_BADR);
  92. }
  93. static void ftmac100_set_tx_ring_base(struct ftmac100 *priv, dma_addr_t addr)
  94. {
  95. iowrite32(addr, priv->base + FTMAC100_OFFSET_TXR_BADR);
  96. }
  97. static void ftmac100_txdma_start_polling(struct ftmac100 *priv)
  98. {
  99. iowrite32(1, priv->base + FTMAC100_OFFSET_TXPD);
  100. }
  101. static int ftmac100_reset(struct ftmac100 *priv)
  102. {
  103. struct net_device *netdev = priv->netdev;
  104. int i;
  105. /* NOTE: reset clears all registers */
  106. iowrite32(FTMAC100_MACCR_SW_RST, priv->base + FTMAC100_OFFSET_MACCR);
  107. for (i = 0; i < 5; i++) {
  108. unsigned int maccr;
  109. maccr = ioread32(priv->base + FTMAC100_OFFSET_MACCR);
  110. if (!(maccr & FTMAC100_MACCR_SW_RST)) {
  111. /*
  112. * FTMAC100_MACCR_SW_RST cleared does not indicate
  113. * that hardware reset completed (what the f*ck).
  114. * We still need to wait for a while.
  115. */
  116. udelay(500);
  117. return 0;
  118. }
  119. udelay(1000);
  120. }
  121. netdev_err(netdev, "software reset failed\n");
  122. return -EIO;
  123. }
  124. static void ftmac100_set_mac(struct ftmac100 *priv, const unsigned char *mac)
  125. {
  126. unsigned int maddr = mac[0] << 8 | mac[1];
  127. unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
  128. iowrite32(maddr, priv->base + FTMAC100_OFFSET_MAC_MADR);
  129. iowrite32(laddr, priv->base + FTMAC100_OFFSET_MAC_LADR);
  130. }
  131. #define MACCR_ENABLE_ALL (FTMAC100_MACCR_XMT_EN | \
  132. FTMAC100_MACCR_RCV_EN | \
  133. FTMAC100_MACCR_XDMA_EN | \
  134. FTMAC100_MACCR_RDMA_EN | \
  135. FTMAC100_MACCR_CRC_APD | \
  136. FTMAC100_MACCR_FULLDUP | \
  137. FTMAC100_MACCR_RX_RUNT | \
  138. FTMAC100_MACCR_RX_BROADPKT)
  139. static int ftmac100_start_hw(struct ftmac100 *priv)
  140. {
  141. struct net_device *netdev = priv->netdev;
  142. if (ftmac100_reset(priv))
  143. return -EIO;
  144. /* setup ring buffer base registers */
  145. ftmac100_set_rx_ring_base(priv,
  146. priv->descs_dma_addr +
  147. offsetof(struct ftmac100_descs, rxdes));
  148. ftmac100_set_tx_ring_base(priv,
  149. priv->descs_dma_addr +
  150. offsetof(struct ftmac100_descs, txdes));
  151. iowrite32(FTMAC100_APTC_RXPOLL_CNT(1), priv->base + FTMAC100_OFFSET_APTC);
  152. ftmac100_set_mac(priv, netdev->dev_addr);
  153. iowrite32(MACCR_ENABLE_ALL, priv->base + FTMAC100_OFFSET_MACCR);
  154. return 0;
  155. }
  156. static void ftmac100_stop_hw(struct ftmac100 *priv)
  157. {
  158. iowrite32(0, priv->base + FTMAC100_OFFSET_MACCR);
  159. }
  160. /******************************************************************************
  161. * internal functions (receive descriptor)
  162. *****************************************************************************/
  163. static bool ftmac100_rxdes_first_segment(struct ftmac100_rxdes *rxdes)
  164. {
  165. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_FRS);
  166. }
  167. static bool ftmac100_rxdes_last_segment(struct ftmac100_rxdes *rxdes)
  168. {
  169. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_LRS);
  170. }
  171. static bool ftmac100_rxdes_owned_by_dma(struct ftmac100_rxdes *rxdes)
  172. {
  173. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_RXDMA_OWN);
  174. }
  175. static void ftmac100_rxdes_set_dma_own(struct ftmac100_rxdes *rxdes)
  176. {
  177. /* clear status bits */
  178. rxdes->rxdes0 = cpu_to_le32(FTMAC100_RXDES0_RXDMA_OWN);
  179. }
  180. static bool ftmac100_rxdes_rx_error(struct ftmac100_rxdes *rxdes)
  181. {
  182. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_RX_ERR);
  183. }
  184. static bool ftmac100_rxdes_crc_error(struct ftmac100_rxdes *rxdes)
  185. {
  186. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_CRC_ERR);
  187. }
  188. static bool ftmac100_rxdes_frame_too_long(struct ftmac100_rxdes *rxdes)
  189. {
  190. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_FTL);
  191. }
  192. static bool ftmac100_rxdes_runt(struct ftmac100_rxdes *rxdes)
  193. {
  194. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_RUNT);
  195. }
  196. static bool ftmac100_rxdes_odd_nibble(struct ftmac100_rxdes *rxdes)
  197. {
  198. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_RX_ODD_NB);
  199. }
  200. static unsigned int ftmac100_rxdes_frame_length(struct ftmac100_rxdes *rxdes)
  201. {
  202. return le32_to_cpu(rxdes->rxdes0) & FTMAC100_RXDES0_RFL;
  203. }
  204. static bool ftmac100_rxdes_multicast(struct ftmac100_rxdes *rxdes)
  205. {
  206. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_MULTICAST);
  207. }
  208. static void ftmac100_rxdes_set_buffer_size(struct ftmac100_rxdes *rxdes,
  209. unsigned int size)
  210. {
  211. rxdes->rxdes1 &= cpu_to_le32(FTMAC100_RXDES1_EDORR);
  212. rxdes->rxdes1 |= cpu_to_le32(FTMAC100_RXDES1_RXBUF_SIZE(size));
  213. }
  214. static void ftmac100_rxdes_set_end_of_ring(struct ftmac100_rxdes *rxdes)
  215. {
  216. rxdes->rxdes1 |= cpu_to_le32(FTMAC100_RXDES1_EDORR);
  217. }
  218. static void ftmac100_rxdes_set_dma_addr(struct ftmac100_rxdes *rxdes,
  219. dma_addr_t addr)
  220. {
  221. rxdes->rxdes2 = cpu_to_le32(addr);
  222. }
  223. static dma_addr_t ftmac100_rxdes_get_dma_addr(struct ftmac100_rxdes *rxdes)
  224. {
  225. return le32_to_cpu(rxdes->rxdes2);
  226. }
  227. /*
  228. * rxdes3 is not used by hardware. We use it to keep track of page.
  229. * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
  230. */
  231. static void ftmac100_rxdes_set_page(struct ftmac100_rxdes *rxdes, struct page *page)
  232. {
  233. rxdes->rxdes3 = (unsigned int)page;
  234. }
  235. static struct page *ftmac100_rxdes_get_page(struct ftmac100_rxdes *rxdes)
  236. {
  237. return (struct page *)rxdes->rxdes3;
  238. }
  239. /******************************************************************************
  240. * internal functions (receive)
  241. *****************************************************************************/
  242. static int ftmac100_next_rx_pointer(int pointer)
  243. {
  244. return (pointer + 1) & (RX_QUEUE_ENTRIES - 1);
  245. }
  246. static void ftmac100_rx_pointer_advance(struct ftmac100 *priv)
  247. {
  248. priv->rx_pointer = ftmac100_next_rx_pointer(priv->rx_pointer);
  249. }
  250. static struct ftmac100_rxdes *ftmac100_current_rxdes(struct ftmac100 *priv)
  251. {
  252. return &priv->descs->rxdes[priv->rx_pointer];
  253. }
  254. static struct ftmac100_rxdes *
  255. ftmac100_rx_locate_first_segment(struct ftmac100 *priv)
  256. {
  257. struct ftmac100_rxdes *rxdes = ftmac100_current_rxdes(priv);
  258. while (!ftmac100_rxdes_owned_by_dma(rxdes)) {
  259. if (ftmac100_rxdes_first_segment(rxdes))
  260. return rxdes;
  261. ftmac100_rxdes_set_dma_own(rxdes);
  262. ftmac100_rx_pointer_advance(priv);
  263. rxdes = ftmac100_current_rxdes(priv);
  264. }
  265. return NULL;
  266. }
  267. static bool ftmac100_rx_packet_error(struct ftmac100 *priv,
  268. struct ftmac100_rxdes *rxdes)
  269. {
  270. struct net_device *netdev = priv->netdev;
  271. bool error = false;
  272. if (unlikely(ftmac100_rxdes_rx_error(rxdes))) {
  273. if (net_ratelimit())
  274. netdev_info(netdev, "rx err\n");
  275. netdev->stats.rx_errors++;
  276. error = true;
  277. }
  278. if (unlikely(ftmac100_rxdes_crc_error(rxdes))) {
  279. if (net_ratelimit())
  280. netdev_info(netdev, "rx crc err\n");
  281. netdev->stats.rx_crc_errors++;
  282. error = true;
  283. }
  284. if (unlikely(ftmac100_rxdes_frame_too_long(rxdes))) {
  285. if (net_ratelimit())
  286. netdev_info(netdev, "rx frame too long\n");
  287. netdev->stats.rx_length_errors++;
  288. error = true;
  289. } else if (unlikely(ftmac100_rxdes_runt(rxdes))) {
  290. if (net_ratelimit())
  291. netdev_info(netdev, "rx runt\n");
  292. netdev->stats.rx_length_errors++;
  293. error = true;
  294. } else if (unlikely(ftmac100_rxdes_odd_nibble(rxdes))) {
  295. if (net_ratelimit())
  296. netdev_info(netdev, "rx odd nibble\n");
  297. netdev->stats.rx_length_errors++;
  298. error = true;
  299. }
  300. return error;
  301. }
  302. static void ftmac100_rx_drop_packet(struct ftmac100 *priv)
  303. {
  304. struct net_device *netdev = priv->netdev;
  305. struct ftmac100_rxdes *rxdes = ftmac100_current_rxdes(priv);
  306. bool done = false;
  307. if (net_ratelimit())
  308. netdev_dbg(netdev, "drop packet %p\n", rxdes);
  309. do {
  310. if (ftmac100_rxdes_last_segment(rxdes))
  311. done = true;
  312. ftmac100_rxdes_set_dma_own(rxdes);
  313. ftmac100_rx_pointer_advance(priv);
  314. rxdes = ftmac100_current_rxdes(priv);
  315. } while (!done && !ftmac100_rxdes_owned_by_dma(rxdes));
  316. netdev->stats.rx_dropped++;
  317. }
  318. static bool ftmac100_rx_packet(struct ftmac100 *priv, int *processed)
  319. {
  320. struct net_device *netdev = priv->netdev;
  321. struct ftmac100_rxdes *rxdes;
  322. struct sk_buff *skb;
  323. struct page *page;
  324. dma_addr_t map;
  325. int length;
  326. rxdes = ftmac100_rx_locate_first_segment(priv);
  327. if (!rxdes)
  328. return false;
  329. if (unlikely(ftmac100_rx_packet_error(priv, rxdes))) {
  330. ftmac100_rx_drop_packet(priv);
  331. return true;
  332. }
  333. /*
  334. * It is impossible to get multi-segment packets
  335. * because we always provide big enough receive buffers.
  336. */
  337. if (unlikely(!ftmac100_rxdes_last_segment(rxdes)))
  338. BUG();
  339. /* start processing */
  340. skb = netdev_alloc_skb_ip_align(netdev, 128);
  341. if (unlikely(!skb)) {
  342. if (net_ratelimit())
  343. netdev_err(netdev, "rx skb alloc failed\n");
  344. ftmac100_rx_drop_packet(priv);
  345. return true;
  346. }
  347. if (unlikely(ftmac100_rxdes_multicast(rxdes)))
  348. netdev->stats.multicast++;
  349. map = ftmac100_rxdes_get_dma_addr(rxdes);
  350. dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
  351. length = ftmac100_rxdes_frame_length(rxdes);
  352. page = ftmac100_rxdes_get_page(rxdes);
  353. skb_fill_page_desc(skb, 0, page, 0, length);
  354. skb->len += length;
  355. skb->data_len += length;
  356. if (length > 128) {
  357. skb->truesize += PAGE_SIZE;
  358. /* We pull the minimum amount into linear part */
  359. __pskb_pull_tail(skb, ETH_HLEN);
  360. } else {
  361. /* Small frames are copied into linear part to free one page */
  362. __pskb_pull_tail(skb, length);
  363. }
  364. ftmac100_alloc_rx_page(priv, rxdes, GFP_ATOMIC);
  365. ftmac100_rx_pointer_advance(priv);
  366. skb->protocol = eth_type_trans(skb, netdev);
  367. netdev->stats.rx_packets++;
  368. netdev->stats.rx_bytes += skb->len;
  369. /* push packet to protocol stack */
  370. netif_receive_skb(skb);
  371. (*processed)++;
  372. return true;
  373. }
  374. /******************************************************************************
  375. * internal functions (transmit descriptor)
  376. *****************************************************************************/
  377. static void ftmac100_txdes_reset(struct ftmac100_txdes *txdes)
  378. {
  379. /* clear all except end of ring bit */
  380. txdes->txdes0 = 0;
  381. txdes->txdes1 &= cpu_to_le32(FTMAC100_TXDES1_EDOTR);
  382. txdes->txdes2 = 0;
  383. txdes->txdes3 = 0;
  384. }
  385. static bool ftmac100_txdes_owned_by_dma(struct ftmac100_txdes *txdes)
  386. {
  387. return txdes->txdes0 & cpu_to_le32(FTMAC100_TXDES0_TXDMA_OWN);
  388. }
  389. static void ftmac100_txdes_set_dma_own(struct ftmac100_txdes *txdes)
  390. {
  391. /*
  392. * Make sure dma own bit will not be set before any other
  393. * descriptor fields.
  394. */
  395. wmb();
  396. txdes->txdes0 |= cpu_to_le32(FTMAC100_TXDES0_TXDMA_OWN);
  397. }
  398. static bool ftmac100_txdes_excessive_collision(struct ftmac100_txdes *txdes)
  399. {
  400. return txdes->txdes0 & cpu_to_le32(FTMAC100_TXDES0_TXPKT_EXSCOL);
  401. }
  402. static bool ftmac100_txdes_late_collision(struct ftmac100_txdes *txdes)
  403. {
  404. return txdes->txdes0 & cpu_to_le32(FTMAC100_TXDES0_TXPKT_LATECOL);
  405. }
  406. static void ftmac100_txdes_set_end_of_ring(struct ftmac100_txdes *txdes)
  407. {
  408. txdes->txdes1 |= cpu_to_le32(FTMAC100_TXDES1_EDOTR);
  409. }
  410. static void ftmac100_txdes_set_first_segment(struct ftmac100_txdes *txdes)
  411. {
  412. txdes->txdes1 |= cpu_to_le32(FTMAC100_TXDES1_FTS);
  413. }
  414. static void ftmac100_txdes_set_last_segment(struct ftmac100_txdes *txdes)
  415. {
  416. txdes->txdes1 |= cpu_to_le32(FTMAC100_TXDES1_LTS);
  417. }
  418. static void ftmac100_txdes_set_txint(struct ftmac100_txdes *txdes)
  419. {
  420. txdes->txdes1 |= cpu_to_le32(FTMAC100_TXDES1_TXIC);
  421. }
  422. static void ftmac100_txdes_set_buffer_size(struct ftmac100_txdes *txdes,
  423. unsigned int len)
  424. {
  425. txdes->txdes1 |= cpu_to_le32(FTMAC100_TXDES1_TXBUF_SIZE(len));
  426. }
  427. static void ftmac100_txdes_set_dma_addr(struct ftmac100_txdes *txdes,
  428. dma_addr_t addr)
  429. {
  430. txdes->txdes2 = cpu_to_le32(addr);
  431. }
  432. static dma_addr_t ftmac100_txdes_get_dma_addr(struct ftmac100_txdes *txdes)
  433. {
  434. return le32_to_cpu(txdes->txdes2);
  435. }
  436. /*
  437. * txdes3 is not used by hardware. We use it to keep track of socket buffer.
  438. * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
  439. */
  440. static void ftmac100_txdes_set_skb(struct ftmac100_txdes *txdes, struct sk_buff *skb)
  441. {
  442. txdes->txdes3 = (unsigned int)skb;
  443. }
  444. static struct sk_buff *ftmac100_txdes_get_skb(struct ftmac100_txdes *txdes)
  445. {
  446. return (struct sk_buff *)txdes->txdes3;
  447. }
  448. /******************************************************************************
  449. * internal functions (transmit)
  450. *****************************************************************************/
  451. static int ftmac100_next_tx_pointer(int pointer)
  452. {
  453. return (pointer + 1) & (TX_QUEUE_ENTRIES - 1);
  454. }
  455. static void ftmac100_tx_pointer_advance(struct ftmac100 *priv)
  456. {
  457. priv->tx_pointer = ftmac100_next_tx_pointer(priv->tx_pointer);
  458. }
  459. static void ftmac100_tx_clean_pointer_advance(struct ftmac100 *priv)
  460. {
  461. priv->tx_clean_pointer = ftmac100_next_tx_pointer(priv->tx_clean_pointer);
  462. }
  463. static struct ftmac100_txdes *ftmac100_current_txdes(struct ftmac100 *priv)
  464. {
  465. return &priv->descs->txdes[priv->tx_pointer];
  466. }
  467. static struct ftmac100_txdes *ftmac100_current_clean_txdes(struct ftmac100 *priv)
  468. {
  469. return &priv->descs->txdes[priv->tx_clean_pointer];
  470. }
  471. static bool ftmac100_tx_complete_packet(struct ftmac100 *priv)
  472. {
  473. struct net_device *netdev = priv->netdev;
  474. struct ftmac100_txdes *txdes;
  475. struct sk_buff *skb;
  476. dma_addr_t map;
  477. if (priv->tx_pending == 0)
  478. return false;
  479. txdes = ftmac100_current_clean_txdes(priv);
  480. if (ftmac100_txdes_owned_by_dma(txdes))
  481. return false;
  482. skb = ftmac100_txdes_get_skb(txdes);
  483. map = ftmac100_txdes_get_dma_addr(txdes);
  484. if (unlikely(ftmac100_txdes_excessive_collision(txdes) ||
  485. ftmac100_txdes_late_collision(txdes))) {
  486. /*
  487. * packet transmitted to ethernet lost due to late collision
  488. * or excessive collision
  489. */
  490. netdev->stats.tx_aborted_errors++;
  491. } else {
  492. netdev->stats.tx_packets++;
  493. netdev->stats.tx_bytes += skb->len;
  494. }
  495. dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
  496. dev_kfree_skb(skb);
  497. ftmac100_txdes_reset(txdes);
  498. ftmac100_tx_clean_pointer_advance(priv);
  499. spin_lock(&priv->tx_lock);
  500. priv->tx_pending--;
  501. spin_unlock(&priv->tx_lock);
  502. netif_wake_queue(netdev);
  503. return true;
  504. }
  505. static void ftmac100_tx_complete(struct ftmac100 *priv)
  506. {
  507. while (ftmac100_tx_complete_packet(priv))
  508. ;
  509. }
  510. static int ftmac100_xmit(struct ftmac100 *priv, struct sk_buff *skb,
  511. dma_addr_t map)
  512. {
  513. struct net_device *netdev = priv->netdev;
  514. struct ftmac100_txdes *txdes;
  515. unsigned int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len;
  516. txdes = ftmac100_current_txdes(priv);
  517. ftmac100_tx_pointer_advance(priv);
  518. /* setup TX descriptor */
  519. ftmac100_txdes_set_skb(txdes, skb);
  520. ftmac100_txdes_set_dma_addr(txdes, map);
  521. ftmac100_txdes_set_first_segment(txdes);
  522. ftmac100_txdes_set_last_segment(txdes);
  523. ftmac100_txdes_set_txint(txdes);
  524. ftmac100_txdes_set_buffer_size(txdes, len);
  525. spin_lock(&priv->tx_lock);
  526. priv->tx_pending++;
  527. if (priv->tx_pending == TX_QUEUE_ENTRIES)
  528. netif_stop_queue(netdev);
  529. /* start transmit */
  530. ftmac100_txdes_set_dma_own(txdes);
  531. spin_unlock(&priv->tx_lock);
  532. ftmac100_txdma_start_polling(priv);
  533. return NETDEV_TX_OK;
  534. }
  535. /******************************************************************************
  536. * internal functions (buffer)
  537. *****************************************************************************/
  538. static int ftmac100_alloc_rx_page(struct ftmac100 *priv,
  539. struct ftmac100_rxdes *rxdes, gfp_t gfp)
  540. {
  541. struct net_device *netdev = priv->netdev;
  542. struct page *page;
  543. dma_addr_t map;
  544. page = alloc_page(gfp);
  545. if (!page) {
  546. if (net_ratelimit())
  547. netdev_err(netdev, "failed to allocate rx page\n");
  548. return -ENOMEM;
  549. }
  550. map = dma_map_page(priv->dev, page, 0, RX_BUF_SIZE, DMA_FROM_DEVICE);
  551. if (unlikely(dma_mapping_error(priv->dev, map))) {
  552. if (net_ratelimit())
  553. netdev_err(netdev, "failed to map rx page\n");
  554. __free_page(page);
  555. return -ENOMEM;
  556. }
  557. ftmac100_rxdes_set_page(rxdes, page);
  558. ftmac100_rxdes_set_dma_addr(rxdes, map);
  559. ftmac100_rxdes_set_buffer_size(rxdes, RX_BUF_SIZE);
  560. ftmac100_rxdes_set_dma_own(rxdes);
  561. return 0;
  562. }
  563. static void ftmac100_free_buffers(struct ftmac100 *priv)
  564. {
  565. int i;
  566. for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
  567. struct ftmac100_rxdes *rxdes = &priv->descs->rxdes[i];
  568. struct page *page = ftmac100_rxdes_get_page(rxdes);
  569. dma_addr_t map = ftmac100_rxdes_get_dma_addr(rxdes);
  570. if (!page)
  571. continue;
  572. dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
  573. __free_page(page);
  574. }
  575. for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
  576. struct ftmac100_txdes *txdes = &priv->descs->txdes[i];
  577. struct sk_buff *skb = ftmac100_txdes_get_skb(txdes);
  578. dma_addr_t map = ftmac100_txdes_get_dma_addr(txdes);
  579. if (!skb)
  580. continue;
  581. dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
  582. dev_kfree_skb(skb);
  583. }
  584. dma_free_coherent(priv->dev, sizeof(struct ftmac100_descs),
  585. priv->descs, priv->descs_dma_addr);
  586. }
  587. static int ftmac100_alloc_buffers(struct ftmac100 *priv)
  588. {
  589. int i;
  590. priv->descs = dma_zalloc_coherent(priv->dev,
  591. sizeof(struct ftmac100_descs),
  592. &priv->descs_dma_addr,
  593. GFP_KERNEL);
  594. if (!priv->descs)
  595. return -ENOMEM;
  596. /* initialize RX ring */
  597. ftmac100_rxdes_set_end_of_ring(&priv->descs->rxdes[RX_QUEUE_ENTRIES - 1]);
  598. for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
  599. struct ftmac100_rxdes *rxdes = &priv->descs->rxdes[i];
  600. if (ftmac100_alloc_rx_page(priv, rxdes, GFP_KERNEL))
  601. goto err;
  602. }
  603. /* initialize TX ring */
  604. ftmac100_txdes_set_end_of_ring(&priv->descs->txdes[TX_QUEUE_ENTRIES - 1]);
  605. return 0;
  606. err:
  607. ftmac100_free_buffers(priv);
  608. return -ENOMEM;
  609. }
  610. /******************************************************************************
  611. * struct mii_if_info functions
  612. *****************************************************************************/
  613. static int ftmac100_mdio_read(struct net_device *netdev, int phy_id, int reg)
  614. {
  615. struct ftmac100 *priv = netdev_priv(netdev);
  616. unsigned int phycr;
  617. int i;
  618. phycr = FTMAC100_PHYCR_PHYAD(phy_id) |
  619. FTMAC100_PHYCR_REGAD(reg) |
  620. FTMAC100_PHYCR_MIIRD;
  621. iowrite32(phycr, priv->base + FTMAC100_OFFSET_PHYCR);
  622. for (i = 0; i < 10; i++) {
  623. phycr = ioread32(priv->base + FTMAC100_OFFSET_PHYCR);
  624. if ((phycr & FTMAC100_PHYCR_MIIRD) == 0)
  625. return phycr & FTMAC100_PHYCR_MIIRDATA;
  626. udelay(100);
  627. }
  628. netdev_err(netdev, "mdio read timed out\n");
  629. return 0;
  630. }
  631. static void ftmac100_mdio_write(struct net_device *netdev, int phy_id, int reg,
  632. int data)
  633. {
  634. struct ftmac100 *priv = netdev_priv(netdev);
  635. unsigned int phycr;
  636. int i;
  637. phycr = FTMAC100_PHYCR_PHYAD(phy_id) |
  638. FTMAC100_PHYCR_REGAD(reg) |
  639. FTMAC100_PHYCR_MIIWR;
  640. data = FTMAC100_PHYWDATA_MIIWDATA(data);
  641. iowrite32(data, priv->base + FTMAC100_OFFSET_PHYWDATA);
  642. iowrite32(phycr, priv->base + FTMAC100_OFFSET_PHYCR);
  643. for (i = 0; i < 10; i++) {
  644. phycr = ioread32(priv->base + FTMAC100_OFFSET_PHYCR);
  645. if ((phycr & FTMAC100_PHYCR_MIIWR) == 0)
  646. return;
  647. udelay(100);
  648. }
  649. netdev_err(netdev, "mdio write timed out\n");
  650. }
  651. /******************************************************************************
  652. * struct ethtool_ops functions
  653. *****************************************************************************/
  654. static void ftmac100_get_drvinfo(struct net_device *netdev,
  655. struct ethtool_drvinfo *info)
  656. {
  657. strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
  658. strlcpy(info->version, DRV_VERSION, sizeof(info->version));
  659. strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info));
  660. }
  661. static int ftmac100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
  662. {
  663. struct ftmac100 *priv = netdev_priv(netdev);
  664. return mii_ethtool_gset(&priv->mii, cmd);
  665. }
  666. static int ftmac100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
  667. {
  668. struct ftmac100 *priv = netdev_priv(netdev);
  669. return mii_ethtool_sset(&priv->mii, cmd);
  670. }
  671. static int ftmac100_nway_reset(struct net_device *netdev)
  672. {
  673. struct ftmac100 *priv = netdev_priv(netdev);
  674. return mii_nway_restart(&priv->mii);
  675. }
  676. static u32 ftmac100_get_link(struct net_device *netdev)
  677. {
  678. struct ftmac100 *priv = netdev_priv(netdev);
  679. return mii_link_ok(&priv->mii);
  680. }
  681. static const struct ethtool_ops ftmac100_ethtool_ops = {
  682. .set_settings = ftmac100_set_settings,
  683. .get_settings = ftmac100_get_settings,
  684. .get_drvinfo = ftmac100_get_drvinfo,
  685. .nway_reset = ftmac100_nway_reset,
  686. .get_link = ftmac100_get_link,
  687. };
  688. /******************************************************************************
  689. * interrupt handler
  690. *****************************************************************************/
  691. static irqreturn_t ftmac100_interrupt(int irq, void *dev_id)
  692. {
  693. struct net_device *netdev = dev_id;
  694. struct ftmac100 *priv = netdev_priv(netdev);
  695. /* Disable interrupts for polling */
  696. ftmac100_disable_all_int(priv);
  697. if (likely(netif_running(netdev)))
  698. napi_schedule(&priv->napi);
  699. return IRQ_HANDLED;
  700. }
  701. /******************************************************************************
  702. * struct napi_struct functions
  703. *****************************************************************************/
  704. static int ftmac100_poll(struct napi_struct *napi, int budget)
  705. {
  706. struct ftmac100 *priv = container_of(napi, struct ftmac100, napi);
  707. struct net_device *netdev = priv->netdev;
  708. unsigned int status;
  709. bool completed = true;
  710. int rx = 0;
  711. status = ioread32(priv->base + FTMAC100_OFFSET_ISR);
  712. if (status & (FTMAC100_INT_RPKT_FINISH | FTMAC100_INT_NORXBUF)) {
  713. /*
  714. * FTMAC100_INT_RPKT_FINISH:
  715. * RX DMA has received packets into RX buffer successfully
  716. *
  717. * FTMAC100_INT_NORXBUF:
  718. * RX buffer unavailable
  719. */
  720. bool retry;
  721. do {
  722. retry = ftmac100_rx_packet(priv, &rx);
  723. } while (retry && rx < budget);
  724. if (retry && rx == budget)
  725. completed = false;
  726. }
  727. if (status & (FTMAC100_INT_XPKT_OK | FTMAC100_INT_XPKT_LOST)) {
  728. /*
  729. * FTMAC100_INT_XPKT_OK:
  730. * packet transmitted to ethernet successfully
  731. *
  732. * FTMAC100_INT_XPKT_LOST:
  733. * packet transmitted to ethernet lost due to late
  734. * collision or excessive collision
  735. */
  736. ftmac100_tx_complete(priv);
  737. }
  738. if (status & (FTMAC100_INT_NORXBUF | FTMAC100_INT_RPKT_LOST |
  739. FTMAC100_INT_AHB_ERR | FTMAC100_INT_PHYSTS_CHG)) {
  740. if (net_ratelimit())
  741. netdev_info(netdev, "[ISR] = 0x%x: %s%s%s%s\n", status,
  742. status & FTMAC100_INT_NORXBUF ? "NORXBUF " : "",
  743. status & FTMAC100_INT_RPKT_LOST ? "RPKT_LOST " : "",
  744. status & FTMAC100_INT_AHB_ERR ? "AHB_ERR " : "",
  745. status & FTMAC100_INT_PHYSTS_CHG ? "PHYSTS_CHG" : "");
  746. if (status & FTMAC100_INT_NORXBUF) {
  747. /* RX buffer unavailable */
  748. netdev->stats.rx_over_errors++;
  749. }
  750. if (status & FTMAC100_INT_RPKT_LOST) {
  751. /* received packet lost due to RX FIFO full */
  752. netdev->stats.rx_fifo_errors++;
  753. }
  754. if (status & FTMAC100_INT_PHYSTS_CHG) {
  755. /* PHY link status change */
  756. mii_check_link(&priv->mii);
  757. }
  758. }
  759. if (completed) {
  760. /* stop polling */
  761. napi_complete(napi);
  762. ftmac100_enable_all_int(priv);
  763. }
  764. return rx;
  765. }
  766. /******************************************************************************
  767. * struct net_device_ops functions
  768. *****************************************************************************/
  769. static int ftmac100_open(struct net_device *netdev)
  770. {
  771. struct ftmac100 *priv = netdev_priv(netdev);
  772. int err;
  773. err = ftmac100_alloc_buffers(priv);
  774. if (err) {
  775. netdev_err(netdev, "failed to allocate buffers\n");
  776. goto err_alloc;
  777. }
  778. err = request_irq(priv->irq, ftmac100_interrupt, 0, netdev->name, netdev);
  779. if (err) {
  780. netdev_err(netdev, "failed to request irq %d\n", priv->irq);
  781. goto err_irq;
  782. }
  783. priv->rx_pointer = 0;
  784. priv->tx_clean_pointer = 0;
  785. priv->tx_pointer = 0;
  786. priv->tx_pending = 0;
  787. err = ftmac100_start_hw(priv);
  788. if (err)
  789. goto err_hw;
  790. napi_enable(&priv->napi);
  791. netif_start_queue(netdev);
  792. ftmac100_enable_all_int(priv);
  793. return 0;
  794. err_hw:
  795. free_irq(priv->irq, netdev);
  796. err_irq:
  797. ftmac100_free_buffers(priv);
  798. err_alloc:
  799. return err;
  800. }
  801. static int ftmac100_stop(struct net_device *netdev)
  802. {
  803. struct ftmac100 *priv = netdev_priv(netdev);
  804. ftmac100_disable_all_int(priv);
  805. netif_stop_queue(netdev);
  806. napi_disable(&priv->napi);
  807. ftmac100_stop_hw(priv);
  808. free_irq(priv->irq, netdev);
  809. ftmac100_free_buffers(priv);
  810. return 0;
  811. }
  812. static int ftmac100_hard_start_xmit(struct sk_buff *skb, struct net_device *netdev)
  813. {
  814. struct ftmac100 *priv = netdev_priv(netdev);
  815. dma_addr_t map;
  816. if (unlikely(skb->len > MAX_PKT_SIZE)) {
  817. if (net_ratelimit())
  818. netdev_dbg(netdev, "tx packet too big\n");
  819. netdev->stats.tx_dropped++;
  820. dev_kfree_skb(skb);
  821. return NETDEV_TX_OK;
  822. }
  823. map = dma_map_single(priv->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
  824. if (unlikely(dma_mapping_error(priv->dev, map))) {
  825. /* drop packet */
  826. if (net_ratelimit())
  827. netdev_err(netdev, "map socket buffer failed\n");
  828. netdev->stats.tx_dropped++;
  829. dev_kfree_skb(skb);
  830. return NETDEV_TX_OK;
  831. }
  832. return ftmac100_xmit(priv, skb, map);
  833. }
  834. /* optional */
  835. static int ftmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
  836. {
  837. struct ftmac100 *priv = netdev_priv(netdev);
  838. struct mii_ioctl_data *data = if_mii(ifr);
  839. return generic_mii_ioctl(&priv->mii, data, cmd, NULL);
  840. }
  841. static const struct net_device_ops ftmac100_netdev_ops = {
  842. .ndo_open = ftmac100_open,
  843. .ndo_stop = ftmac100_stop,
  844. .ndo_start_xmit = ftmac100_hard_start_xmit,
  845. .ndo_set_mac_address = eth_mac_addr,
  846. .ndo_validate_addr = eth_validate_addr,
  847. .ndo_do_ioctl = ftmac100_do_ioctl,
  848. };
  849. /******************************************************************************
  850. * struct platform_driver functions
  851. *****************************************************************************/
  852. static int ftmac100_probe(struct platform_device *pdev)
  853. {
  854. struct resource *res;
  855. int irq;
  856. struct net_device *netdev;
  857. struct ftmac100 *priv;
  858. int err;
  859. if (!pdev)
  860. return -ENODEV;
  861. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  862. if (!res)
  863. return -ENXIO;
  864. irq = platform_get_irq(pdev, 0);
  865. if (irq < 0)
  866. return irq;
  867. /* setup net_device */
  868. netdev = alloc_etherdev(sizeof(*priv));
  869. if (!netdev) {
  870. err = -ENOMEM;
  871. goto err_alloc_etherdev;
  872. }
  873. SET_NETDEV_DEV(netdev, &pdev->dev);
  874. netdev->ethtool_ops = &ftmac100_ethtool_ops;
  875. netdev->netdev_ops = &ftmac100_netdev_ops;
  876. platform_set_drvdata(pdev, netdev);
  877. /* setup private data */
  878. priv = netdev_priv(netdev);
  879. priv->netdev = netdev;
  880. priv->dev = &pdev->dev;
  881. spin_lock_init(&priv->tx_lock);
  882. /* initialize NAPI */
  883. netif_napi_add(netdev, &priv->napi, ftmac100_poll, 64);
  884. /* map io memory */
  885. priv->res = request_mem_region(res->start, resource_size(res),
  886. dev_name(&pdev->dev));
  887. if (!priv->res) {
  888. dev_err(&pdev->dev, "Could not reserve memory region\n");
  889. err = -ENOMEM;
  890. goto err_req_mem;
  891. }
  892. priv->base = ioremap(res->start, resource_size(res));
  893. if (!priv->base) {
  894. dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
  895. err = -EIO;
  896. goto err_ioremap;
  897. }
  898. priv->irq = irq;
  899. /* initialize struct mii_if_info */
  900. priv->mii.phy_id = 0;
  901. priv->mii.phy_id_mask = 0x1f;
  902. priv->mii.reg_num_mask = 0x1f;
  903. priv->mii.dev = netdev;
  904. priv->mii.mdio_read = ftmac100_mdio_read;
  905. priv->mii.mdio_write = ftmac100_mdio_write;
  906. /* register network device */
  907. err = register_netdev(netdev);
  908. if (err) {
  909. dev_err(&pdev->dev, "Failed to register netdev\n");
  910. goto err_register_netdev;
  911. }
  912. netdev_info(netdev, "irq %d, mapped at %p\n", priv->irq, priv->base);
  913. if (!is_valid_ether_addr(netdev->dev_addr)) {
  914. eth_hw_addr_random(netdev);
  915. netdev_info(netdev, "generated random MAC address %pM\n",
  916. netdev->dev_addr);
  917. }
  918. return 0;
  919. err_register_netdev:
  920. iounmap(priv->base);
  921. err_ioremap:
  922. release_resource(priv->res);
  923. err_req_mem:
  924. netif_napi_del(&priv->napi);
  925. free_netdev(netdev);
  926. err_alloc_etherdev:
  927. return err;
  928. }
  929. static int __exit ftmac100_remove(struct platform_device *pdev)
  930. {
  931. struct net_device *netdev;
  932. struct ftmac100 *priv;
  933. netdev = platform_get_drvdata(pdev);
  934. priv = netdev_priv(netdev);
  935. unregister_netdev(netdev);
  936. iounmap(priv->base);
  937. release_resource(priv->res);
  938. netif_napi_del(&priv->napi);
  939. free_netdev(netdev);
  940. return 0;
  941. }
  942. static struct platform_driver ftmac100_driver = {
  943. .probe = ftmac100_probe,
  944. .remove = __exit_p(ftmac100_remove),
  945. .driver = {
  946. .name = DRV_NAME,
  947. },
  948. };
  949. /******************************************************************************
  950. * initialization / finalization
  951. *****************************************************************************/
  952. static int __init ftmac100_init(void)
  953. {
  954. pr_info("Loading version " DRV_VERSION " ...\n");
  955. return platform_driver_register(&ftmac100_driver);
  956. }
  957. static void __exit ftmac100_exit(void)
  958. {
  959. platform_driver_unregister(&ftmac100_driver);
  960. }
  961. module_init(ftmac100_init);
  962. module_exit(ftmac100_exit);
  963. MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
  964. MODULE_DESCRIPTION("FTMAC100 driver");
  965. MODULE_LICENSE("GPL");