hns_dsaf_gmac.c 24 KB

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  1. /*
  2. * Copyright (c) 2014-2015 Hisilicon Limited.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. */
  9. #include <linux/delay.h>
  10. #include <linux/of_mdio.h>
  11. #include "hns_dsaf_main.h"
  12. #include "hns_dsaf_mac.h"
  13. #include "hns_dsaf_gmac.h"
  14. static const struct mac_stats_string g_gmac_stats_string[] = {
  15. {"gmac_rx_octets_total_ok", MAC_STATS_FIELD_OFF(rx_good_bytes)},
  16. {"gmac_rx_octets_bad", MAC_STATS_FIELD_OFF(rx_bad_bytes)},
  17. {"gmac_rx_uc_pkts", MAC_STATS_FIELD_OFF(rx_uc_pkts)},
  18. {"gamc_rx_mc_pkts", MAC_STATS_FIELD_OFF(rx_mc_pkts)},
  19. {"gmac_rx_bc_pkts", MAC_STATS_FIELD_OFF(rx_bc_pkts)},
  20. {"gmac_rx_pkts_64octets", MAC_STATS_FIELD_OFF(rx_64bytes)},
  21. {"gmac_rx_pkts_65to127", MAC_STATS_FIELD_OFF(rx_65to127)},
  22. {"gmac_rx_pkts_128to255", MAC_STATS_FIELD_OFF(rx_128to255)},
  23. {"gmac_rx_pkts_256to511", MAC_STATS_FIELD_OFF(rx_256to511)},
  24. {"gmac_rx_pkts_512to1023", MAC_STATS_FIELD_OFF(rx_512to1023)},
  25. {"gmac_rx_pkts_1024to1518", MAC_STATS_FIELD_OFF(rx_1024to1518)},
  26. {"gmac_rx_pkts_1519tomax", MAC_STATS_FIELD_OFF(rx_1519tomax)},
  27. {"gmac_rx_fcs_errors", MAC_STATS_FIELD_OFF(rx_fcs_err)},
  28. {"gmac_rx_tagged", MAC_STATS_FIELD_OFF(rx_vlan_pkts)},
  29. {"gmac_rx_data_err", MAC_STATS_FIELD_OFF(rx_data_err)},
  30. {"gmac_rx_align_errors", MAC_STATS_FIELD_OFF(rx_align_err)},
  31. {"gmac_rx_long_errors", MAC_STATS_FIELD_OFF(rx_oversize)},
  32. {"gmac_rx_jabber_errors", MAC_STATS_FIELD_OFF(rx_jabber_err)},
  33. {"gmac_rx_pause_maccontrol", MAC_STATS_FIELD_OFF(rx_pfc_tc0)},
  34. {"gmac_rx_unknown_maccontrol", MAC_STATS_FIELD_OFF(rx_unknown_ctrl)},
  35. {"gmac_rx_very_long_err", MAC_STATS_FIELD_OFF(rx_long_err)},
  36. {"gmac_rx_runt_err", MAC_STATS_FIELD_OFF(rx_minto64)},
  37. {"gmac_rx_short_err", MAC_STATS_FIELD_OFF(rx_under_min)},
  38. {"gmac_rx_filt_pkt", MAC_STATS_FIELD_OFF(rx_filter_bytes)},
  39. {"gmac_rx_octets_total_filt", MAC_STATS_FIELD_OFF(rx_filter_pkts)},
  40. {"gmac_rx_overrun_cnt", MAC_STATS_FIELD_OFF(rx_fifo_overrun_err)},
  41. {"gmac_rx_length_err", MAC_STATS_FIELD_OFF(rx_len_err)},
  42. {"gmac_rx_fail_comma", MAC_STATS_FIELD_OFF(rx_comma_err)},
  43. {"gmac_tx_octets_ok", MAC_STATS_FIELD_OFF(tx_good_bytes)},
  44. {"gmac_tx_octets_bad", MAC_STATS_FIELD_OFF(tx_bad_bytes)},
  45. {"gmac_tx_uc_pkts", MAC_STATS_FIELD_OFF(tx_uc_pkts)},
  46. {"gmac_tx_mc_pkts", MAC_STATS_FIELD_OFF(tx_mc_pkts)},
  47. {"gmac_tx_bc_pkts", MAC_STATS_FIELD_OFF(tx_bc_pkts)},
  48. {"gmac_tx_pkts_64octets", MAC_STATS_FIELD_OFF(tx_64bytes)},
  49. {"gmac_tx_pkts_65to127", MAC_STATS_FIELD_OFF(tx_65to127)},
  50. {"gmac_tx_pkts_128to255", MAC_STATS_FIELD_OFF(tx_128to255)},
  51. {"gmac_tx_pkts_256to511", MAC_STATS_FIELD_OFF(tx_256to511)},
  52. {"gmac_tx_pkts_512to1023", MAC_STATS_FIELD_OFF(tx_512to1023)},
  53. {"gmac_tx_pkts_1024to1518", MAC_STATS_FIELD_OFF(tx_1024to1518)},
  54. {"gmac_tx_pkts_1519tomax", MAC_STATS_FIELD_OFF(tx_1519tomax)},
  55. {"gmac_tx_excessive_length_drop", MAC_STATS_FIELD_OFF(tx_jabber_err)},
  56. {"gmac_tx_underrun", MAC_STATS_FIELD_OFF(tx_underrun_err)},
  57. {"gmac_tx_tagged", MAC_STATS_FIELD_OFF(tx_vlan)},
  58. {"gmac_tx_crc_error", MAC_STATS_FIELD_OFF(tx_crc_err)},
  59. {"gmac_tx_pause_frames", MAC_STATS_FIELD_OFF(tx_pfc_tc0)}
  60. };
  61. static void hns_gmac_enable(void *mac_drv, enum mac_commom_mode mode)
  62. {
  63. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  64. /*enable GE rX/tX */
  65. if ((mode == MAC_COMM_MODE_TX) || (mode == MAC_COMM_MODE_RX_AND_TX))
  66. dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_TX_EN_B, 1);
  67. if ((mode == MAC_COMM_MODE_RX) || (mode == MAC_COMM_MODE_RX_AND_TX))
  68. dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_RX_EN_B, 1);
  69. }
  70. static void hns_gmac_disable(void *mac_drv, enum mac_commom_mode mode)
  71. {
  72. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  73. /*disable GE rX/tX */
  74. if ((mode == MAC_COMM_MODE_TX) || (mode == MAC_COMM_MODE_RX_AND_TX))
  75. dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_TX_EN_B, 0);
  76. if ((mode == MAC_COMM_MODE_RX) || (mode == MAC_COMM_MODE_RX_AND_TX))
  77. dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_RX_EN_B, 0);
  78. }
  79. /**
  80. *hns_gmac_get_en - get port enable
  81. *@mac_drv:mac device
  82. *@rx:rx enable
  83. *@tx:tx enable
  84. */
  85. static void hns_gmac_get_en(void *mac_drv, u32 *rx, u32 *tx)
  86. {
  87. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  88. u32 porten;
  89. porten = dsaf_read_dev(drv, GMAC_PORT_EN_REG);
  90. *tx = dsaf_get_bit(porten, GMAC_PORT_TX_EN_B);
  91. *rx = dsaf_get_bit(porten, GMAC_PORT_RX_EN_B);
  92. }
  93. static void hns_gmac_free(void *mac_drv)
  94. {
  95. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  96. struct dsaf_device *dsaf_dev
  97. = (struct dsaf_device *)dev_get_drvdata(drv->dev);
  98. u32 mac_id = drv->mac_id;
  99. hns_dsaf_ge_srst_by_port(dsaf_dev, mac_id, 0);
  100. }
  101. static void hns_gmac_set_tx_auto_pause_frames(void *mac_drv, u16 newval)
  102. {
  103. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  104. dsaf_set_dev_field(drv, GMAC_FC_TX_TIMER_REG, GMAC_FC_TX_TIMER_M,
  105. GMAC_FC_TX_TIMER_S, newval);
  106. }
  107. static void hns_gmac_get_tx_auto_pause_frames(void *mac_drv, u16 *newval)
  108. {
  109. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  110. *newval = dsaf_get_dev_field(drv, GMAC_FC_TX_TIMER_REG,
  111. GMAC_FC_TX_TIMER_M, GMAC_FC_TX_TIMER_S);
  112. }
  113. static void hns_gmac_set_rx_auto_pause_frames(void *mac_drv, u32 newval)
  114. {
  115. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  116. dsaf_set_dev_bit(drv, GMAC_PAUSE_EN_REG,
  117. GMAC_PAUSE_EN_RX_FDFC_B, !!newval);
  118. }
  119. static void hns_gmac_config_max_frame_length(void *mac_drv, u16 newval)
  120. {
  121. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  122. dsaf_set_dev_field(drv, GMAC_MAX_FRM_SIZE_REG, GMAC_MAX_FRM_SIZE_M,
  123. GMAC_MAX_FRM_SIZE_S, newval);
  124. dsaf_set_dev_field(drv, GAMC_RX_MAX_FRAME, GMAC_MAX_FRM_SIZE_M,
  125. GMAC_MAX_FRM_SIZE_S, newval);
  126. }
  127. static void hns_gmac_config_an_mode(void *mac_drv, u8 newval)
  128. {
  129. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  130. dsaf_set_dev_bit(drv, GMAC_TRANSMIT_CONTROL_REG,
  131. GMAC_TX_AN_EN_B, !!newval);
  132. }
  133. static void hns_gmac_tx_loop_pkt_dis(void *mac_drv)
  134. {
  135. u32 tx_loop_pkt_pri;
  136. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  137. tx_loop_pkt_pri = dsaf_read_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG);
  138. dsaf_set_bit(tx_loop_pkt_pri, GMAC_TX_LOOP_PKT_EN_B, 1);
  139. dsaf_set_bit(tx_loop_pkt_pri, GMAC_TX_LOOP_PKT_HIG_PRI_B, 0);
  140. dsaf_write_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG, tx_loop_pkt_pri);
  141. }
  142. static void hns_gmac_set_duplex_type(void *mac_drv, u8 newval)
  143. {
  144. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  145. dsaf_set_dev_bit(drv, GMAC_DUPLEX_TYPE_REG,
  146. GMAC_DUPLEX_TYPE_B, !!newval);
  147. }
  148. static void hns_gmac_get_duplex_type(void *mac_drv,
  149. enum hns_gmac_duplex_mdoe *duplex_mode)
  150. {
  151. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  152. *duplex_mode = (enum hns_gmac_duplex_mdoe)dsaf_get_dev_bit(
  153. drv, GMAC_DUPLEX_TYPE_REG, GMAC_DUPLEX_TYPE_B);
  154. }
  155. static void hns_gmac_get_port_mode(void *mac_drv, enum hns_port_mode *port_mode)
  156. {
  157. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  158. *port_mode = (enum hns_port_mode)dsaf_get_dev_field(
  159. drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S);
  160. }
  161. static void hns_gmac_port_mode_get(void *mac_drv,
  162. struct hns_gmac_port_mode_cfg *port_mode)
  163. {
  164. u32 tx_ctrl;
  165. u32 recv_ctrl;
  166. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  167. port_mode->port_mode = (enum hns_port_mode)dsaf_get_dev_field(
  168. drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S);
  169. tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG);
  170. recv_ctrl = dsaf_read_dev(drv, GMAC_RECV_CONTROL_REG);
  171. port_mode->max_frm_size =
  172. dsaf_get_dev_field(drv, GMAC_MAX_FRM_SIZE_REG,
  173. GMAC_MAX_FRM_SIZE_M, GMAC_MAX_FRM_SIZE_S);
  174. port_mode->short_runts_thr =
  175. dsaf_get_dev_field(drv, GMAC_SHORT_RUNTS_THR_REG,
  176. GMAC_SHORT_RUNTS_THR_M,
  177. GMAC_SHORT_RUNTS_THR_S);
  178. port_mode->pad_enable = dsaf_get_bit(tx_ctrl, GMAC_TX_PAD_EN_B);
  179. port_mode->crc_add = dsaf_get_bit(tx_ctrl, GMAC_TX_CRC_ADD_B);
  180. port_mode->an_enable = dsaf_get_bit(tx_ctrl, GMAC_TX_AN_EN_B);
  181. port_mode->runt_pkt_en =
  182. dsaf_get_bit(recv_ctrl, GMAC_RECV_CTRL_RUNT_PKT_EN_B);
  183. port_mode->strip_pad_en =
  184. dsaf_get_bit(recv_ctrl, GMAC_RECV_CTRL_STRIP_PAD_EN_B);
  185. }
  186. static void hns_gmac_pause_frm_cfg(void *mac_drv, u32 rx_pause_en,
  187. u32 tx_pause_en)
  188. {
  189. u32 pause_en;
  190. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  191. pause_en = dsaf_read_dev(drv, GMAC_PAUSE_EN_REG);
  192. dsaf_set_bit(pause_en, GMAC_PAUSE_EN_RX_FDFC_B, !!rx_pause_en);
  193. dsaf_set_bit(pause_en, GMAC_PAUSE_EN_TX_FDFC_B, !!tx_pause_en);
  194. dsaf_write_dev(drv, GMAC_PAUSE_EN_REG, pause_en);
  195. }
  196. static void hns_gmac_get_pausefrm_cfg(void *mac_drv, u32 *rx_pause_en,
  197. u32 *tx_pause_en)
  198. {
  199. u32 pause_en;
  200. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  201. pause_en = dsaf_read_dev(drv, GMAC_PAUSE_EN_REG);
  202. *rx_pause_en = dsaf_get_bit(pause_en, GMAC_PAUSE_EN_RX_FDFC_B);
  203. *tx_pause_en = dsaf_get_bit(pause_en, GMAC_PAUSE_EN_TX_FDFC_B);
  204. }
  205. static int hns_gmac_adjust_link(void *mac_drv, enum mac_speed speed,
  206. u32 full_duplex)
  207. {
  208. u32 tx_ctrl;
  209. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  210. dsaf_set_dev_bit(drv, GMAC_DUPLEX_TYPE_REG,
  211. GMAC_DUPLEX_TYPE_B, !!full_duplex);
  212. switch (speed) {
  213. case MAC_SPEED_10:
  214. dsaf_set_dev_field(
  215. drv, GMAC_PORT_MODE_REG,
  216. GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x6);
  217. break;
  218. case MAC_SPEED_100:
  219. dsaf_set_dev_field(
  220. drv, GMAC_PORT_MODE_REG,
  221. GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x7);
  222. break;
  223. case MAC_SPEED_1000:
  224. dsaf_set_dev_field(
  225. drv, GMAC_PORT_MODE_REG,
  226. GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x8);
  227. break;
  228. default:
  229. dev_err(drv->dev,
  230. "hns_gmac_adjust_link fail, speed%d mac%d\n",
  231. speed, drv->mac_id);
  232. return -EINVAL;
  233. }
  234. tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG);
  235. dsaf_set_bit(tx_ctrl, GMAC_TX_PAD_EN_B, 1);
  236. dsaf_set_bit(tx_ctrl, GMAC_TX_CRC_ADD_B, 1);
  237. dsaf_write_dev(drv, GMAC_TRANSMIT_CONTROL_REG, tx_ctrl);
  238. dsaf_set_dev_bit(drv, GMAC_MODE_CHANGE_EN_REG,
  239. GMAC_MODE_CHANGE_EB_B, 1);
  240. return 0;
  241. }
  242. static void hns_gmac_init(void *mac_drv)
  243. {
  244. u32 port;
  245. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  246. struct dsaf_device *dsaf_dev
  247. = (struct dsaf_device *)dev_get_drvdata(drv->dev);
  248. port = drv->mac_id;
  249. hns_dsaf_ge_srst_by_port(dsaf_dev, port, 0);
  250. mdelay(10);
  251. hns_dsaf_ge_srst_by_port(dsaf_dev, port, 1);
  252. mdelay(10);
  253. hns_gmac_disable(mac_drv, MAC_COMM_MODE_RX_AND_TX);
  254. hns_gmac_tx_loop_pkt_dis(mac_drv);
  255. }
  256. void hns_gmac_update_stats(void *mac_drv)
  257. {
  258. struct mac_hw_stats *hw_stats = NULL;
  259. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  260. hw_stats = &drv->mac_cb->hw_stats;
  261. /* RX */
  262. hw_stats->rx_good_bytes
  263. += dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_OK_REG);
  264. hw_stats->rx_bad_bytes
  265. += dsaf_read_dev(drv, GMAC_RX_OCTETS_BAD_REG);
  266. hw_stats->rx_uc_pkts += dsaf_read_dev(drv, GMAC_RX_UC_PKTS_REG);
  267. hw_stats->rx_mc_pkts += dsaf_read_dev(drv, GMAC_RX_MC_PKTS_REG);
  268. hw_stats->rx_bc_pkts += dsaf_read_dev(drv, GMAC_RX_BC_PKTS_REG);
  269. hw_stats->rx_64bytes
  270. += dsaf_read_dev(drv, GMAC_RX_PKTS_64OCTETS_REG);
  271. hw_stats->rx_65to127
  272. += dsaf_read_dev(drv, GMAC_RX_PKTS_65TO127OCTETS_REG);
  273. hw_stats->rx_128to255
  274. += dsaf_read_dev(drv, GMAC_RX_PKTS_128TO255OCTETS_REG);
  275. hw_stats->rx_256to511
  276. += dsaf_read_dev(drv, GMAC_RX_PKTS_255TO511OCTETS_REG);
  277. hw_stats->rx_512to1023
  278. += dsaf_read_dev(drv, GMAC_RX_PKTS_512TO1023OCTETS_REG);
  279. hw_stats->rx_1024to1518
  280. += dsaf_read_dev(drv, GMAC_RX_PKTS_1024TO1518OCTETS_REG);
  281. hw_stats->rx_1519tomax
  282. += dsaf_read_dev(drv, GMAC_RX_PKTS_1519TOMAXOCTETS_REG);
  283. hw_stats->rx_fcs_err += dsaf_read_dev(drv, GMAC_RX_FCS_ERRORS_REG);
  284. hw_stats->rx_vlan_pkts += dsaf_read_dev(drv, GMAC_RX_TAGGED_REG);
  285. hw_stats->rx_data_err += dsaf_read_dev(drv, GMAC_RX_DATA_ERR_REG);
  286. hw_stats->rx_align_err
  287. += dsaf_read_dev(drv, GMAC_RX_ALIGN_ERRORS_REG);
  288. hw_stats->rx_oversize
  289. += dsaf_read_dev(drv, GMAC_RX_LONG_ERRORS_REG);
  290. hw_stats->rx_jabber_err
  291. += dsaf_read_dev(drv, GMAC_RX_JABBER_ERRORS_REG);
  292. hw_stats->rx_pfc_tc0
  293. += dsaf_read_dev(drv, GMAC_RX_PAUSE_MACCTRL_FRAM_REG);
  294. hw_stats->rx_unknown_ctrl
  295. += dsaf_read_dev(drv, GMAC_RX_UNKNOWN_MACCTRL_FRAM_REG);
  296. hw_stats->rx_long_err
  297. += dsaf_read_dev(drv, GMAC_RX_VERY_LONG_ERR_CNT_REG);
  298. hw_stats->rx_minto64
  299. += dsaf_read_dev(drv, GMAC_RX_RUNT_ERR_CNT_REG);
  300. hw_stats->rx_under_min
  301. += dsaf_read_dev(drv, GMAC_RX_SHORT_ERR_CNT_REG);
  302. hw_stats->rx_filter_pkts
  303. += dsaf_read_dev(drv, GMAC_RX_FILT_PKT_CNT_REG);
  304. hw_stats->rx_filter_bytes
  305. += dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_FILT_REG);
  306. hw_stats->rx_fifo_overrun_err
  307. += dsaf_read_dev(drv, GMAC_RX_OVERRUN_CNT_REG);
  308. hw_stats->rx_len_err
  309. += dsaf_read_dev(drv, GMAC_RX_LENGTHFIELD_ERR_CNT_REG);
  310. hw_stats->rx_comma_err
  311. += dsaf_read_dev(drv, GMAC_RX_FAIL_COMMA_CNT_REG);
  312. /* TX */
  313. hw_stats->tx_good_bytes
  314. += dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_OK_REG);
  315. hw_stats->tx_bad_bytes
  316. += dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_BAD_REG);
  317. hw_stats->tx_uc_pkts += dsaf_read_dev(drv, GMAC_TX_UC_PKTS_REG);
  318. hw_stats->tx_mc_pkts += dsaf_read_dev(drv, GMAC_TX_MC_PKTS_REG);
  319. hw_stats->tx_bc_pkts += dsaf_read_dev(drv, GMAC_TX_BC_PKTS_REG);
  320. hw_stats->tx_64bytes
  321. += dsaf_read_dev(drv, GMAC_TX_PKTS_64OCTETS_REG);
  322. hw_stats->tx_65to127
  323. += dsaf_read_dev(drv, GMAC_TX_PKTS_65TO127OCTETS_REG);
  324. hw_stats->tx_128to255
  325. += dsaf_read_dev(drv, GMAC_TX_PKTS_128TO255OCTETS_REG);
  326. hw_stats->tx_256to511
  327. += dsaf_read_dev(drv, GMAC_TX_PKTS_255TO511OCTETS_REG);
  328. hw_stats->tx_512to1023
  329. += dsaf_read_dev(drv, GMAC_TX_PKTS_512TO1023OCTETS_REG);
  330. hw_stats->tx_1024to1518
  331. += dsaf_read_dev(drv, GMAC_TX_PKTS_1024TO1518OCTETS_REG);
  332. hw_stats->tx_1519tomax
  333. += dsaf_read_dev(drv, GMAC_TX_PKTS_1519TOMAXOCTETS_REG);
  334. hw_stats->tx_jabber_err
  335. += dsaf_read_dev(drv, GMAC_TX_EXCESSIVE_LENGTH_DROP_REG);
  336. hw_stats->tx_underrun_err
  337. += dsaf_read_dev(drv, GMAC_TX_UNDERRUN_REG);
  338. hw_stats->tx_vlan += dsaf_read_dev(drv, GMAC_TX_TAGGED_REG);
  339. hw_stats->tx_crc_err += dsaf_read_dev(drv, GMAC_TX_CRC_ERROR_REG);
  340. hw_stats->tx_pfc_tc0
  341. += dsaf_read_dev(drv, GMAC_TX_PAUSE_FRAMES_REG);
  342. }
  343. static void hns_gmac_set_mac_addr(void *mac_drv, char *mac_addr)
  344. {
  345. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  346. if (drv->mac_id >= DSAF_SERVICE_NW_NUM) {
  347. u32 high_val = mac_addr[1] | (mac_addr[0] << 8);
  348. u32 low_val = mac_addr[5] | (mac_addr[4] << 8)
  349. | (mac_addr[3] << 16) | (mac_addr[2] << 24);
  350. dsaf_write_dev(drv, GMAC_STATION_ADDR_LOW_2_REG, low_val);
  351. dsaf_write_dev(drv, GMAC_STATION_ADDR_HIGH_2_REG, high_val);
  352. }
  353. }
  354. static int hns_gmac_config_loopback(void *mac_drv, enum hnae_loop loop_mode,
  355. u8 enable)
  356. {
  357. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  358. switch (loop_mode) {
  359. case MAC_INTERNALLOOP_MAC:
  360. dsaf_set_dev_bit(drv, GMAC_LOOP_REG, GMAC_LP_REG_CF2MI_LP_EN_B,
  361. !!enable);
  362. break;
  363. default:
  364. dev_err(drv->dev, "loop_mode error\n");
  365. return -EINVAL;
  366. }
  367. return 0;
  368. }
  369. static void hns_gmac_config_pad_and_crc(void *mac_drv, u8 newval)
  370. {
  371. u32 tx_ctrl;
  372. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  373. tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG);
  374. dsaf_set_bit(tx_ctrl, GMAC_TX_PAD_EN_B, !!newval);
  375. dsaf_set_bit(tx_ctrl, GMAC_TX_CRC_ADD_B, !!newval);
  376. dsaf_write_dev(drv, GMAC_TRANSMIT_CONTROL_REG, tx_ctrl);
  377. }
  378. static void hns_gmac_get_id(void *mac_drv, u8 *mac_id)
  379. {
  380. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  381. *mac_id = drv->mac_id;
  382. }
  383. static void hns_gmac_get_info(void *mac_drv, struct mac_info *mac_info)
  384. {
  385. enum hns_gmac_duplex_mdoe duplex;
  386. enum hns_port_mode speed;
  387. u32 rx_pause;
  388. u32 tx_pause;
  389. u32 rx;
  390. u32 tx;
  391. u16 fc_tx_timer;
  392. struct hns_gmac_port_mode_cfg port_mode = { GMAC_10M_MII, 0 };
  393. hns_gmac_port_mode_get(mac_drv, &port_mode);
  394. mac_info->pad_and_crc_en = port_mode.crc_add && port_mode.pad_enable;
  395. mac_info->auto_neg = port_mode.an_enable;
  396. hns_gmac_get_tx_auto_pause_frames(mac_drv, &fc_tx_timer);
  397. mac_info->tx_pause_time = fc_tx_timer;
  398. hns_gmac_get_en(mac_drv, &rx, &tx);
  399. mac_info->port_en = rx && tx;
  400. hns_gmac_get_duplex_type(mac_drv, &duplex);
  401. mac_info->duplex = duplex;
  402. hns_gmac_get_port_mode(mac_drv, &speed);
  403. switch (speed) {
  404. case GMAC_10M_SGMII:
  405. mac_info->speed = MAC_SPEED_10;
  406. break;
  407. case GMAC_100M_SGMII:
  408. mac_info->speed = MAC_SPEED_100;
  409. break;
  410. case GMAC_1000M_SGMII:
  411. mac_info->speed = MAC_SPEED_1000;
  412. break;
  413. default:
  414. mac_info->speed = 0;
  415. break;
  416. }
  417. hns_gmac_get_pausefrm_cfg(mac_drv, &rx_pause, &tx_pause);
  418. mac_info->rx_pause_en = rx_pause;
  419. mac_info->tx_pause_en = tx_pause;
  420. }
  421. static void hns_gmac_autoneg_stat(void *mac_drv, u32 *enable)
  422. {
  423. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  424. *enable = dsaf_get_dev_bit(drv, GMAC_TRANSMIT_CONTROL_REG,
  425. GMAC_TX_AN_EN_B);
  426. }
  427. static void hns_gmac_get_link_status(void *mac_drv, u32 *link_stat)
  428. {
  429. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  430. *link_stat = dsaf_get_dev_bit(drv, GMAC_AN_NEG_STATE_REG,
  431. GMAC_AN_NEG_STAT_RX_SYNC_OK_B);
  432. }
  433. static void hns_gmac_get_regs(void *mac_drv, void *data)
  434. {
  435. u32 *regs = data;
  436. int i;
  437. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  438. /* base config registers */
  439. regs[0] = dsaf_read_dev(drv, GMAC_DUPLEX_TYPE_REG);
  440. regs[1] = dsaf_read_dev(drv, GMAC_FD_FC_TYPE_REG);
  441. regs[2] = dsaf_read_dev(drv, GMAC_FC_TX_TIMER_REG);
  442. regs[3] = dsaf_read_dev(drv, GMAC_FD_FC_ADDR_LOW_REG);
  443. regs[4] = dsaf_read_dev(drv, GMAC_FD_FC_ADDR_HIGH_REG);
  444. regs[5] = dsaf_read_dev(drv, GMAC_IPG_TX_TIMER_REG);
  445. regs[6] = dsaf_read_dev(drv, GMAC_PAUSE_THR_REG);
  446. regs[7] = dsaf_read_dev(drv, GMAC_MAX_FRM_SIZE_REG);
  447. regs[8] = dsaf_read_dev(drv, GMAC_PORT_MODE_REG);
  448. regs[9] = dsaf_read_dev(drv, GMAC_PORT_EN_REG);
  449. regs[10] = dsaf_read_dev(drv, GMAC_PAUSE_EN_REG);
  450. regs[11] = dsaf_read_dev(drv, GMAC_SHORT_RUNTS_THR_REG);
  451. regs[12] = dsaf_read_dev(drv, GMAC_AN_NEG_STATE_REG);
  452. regs[13] = dsaf_read_dev(drv, GMAC_TX_LOCAL_PAGE_REG);
  453. regs[14] = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG);
  454. regs[15] = dsaf_read_dev(drv, GMAC_REC_FILT_CONTROL_REG);
  455. regs[16] = dsaf_read_dev(drv, GMAC_PTP_CONFIG_REG);
  456. /* rx static registers */
  457. regs[17] = dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_OK_REG);
  458. regs[18] = dsaf_read_dev(drv, GMAC_RX_OCTETS_BAD_REG);
  459. regs[19] = dsaf_read_dev(drv, GMAC_RX_UC_PKTS_REG);
  460. regs[20] = dsaf_read_dev(drv, GMAC_RX_MC_PKTS_REG);
  461. regs[21] = dsaf_read_dev(drv, GMAC_RX_BC_PKTS_REG);
  462. regs[22] = dsaf_read_dev(drv, GMAC_RX_PKTS_64OCTETS_REG);
  463. regs[23] = dsaf_read_dev(drv, GMAC_RX_PKTS_65TO127OCTETS_REG);
  464. regs[24] = dsaf_read_dev(drv, GMAC_RX_PKTS_128TO255OCTETS_REG);
  465. regs[25] = dsaf_read_dev(drv, GMAC_RX_PKTS_255TO511OCTETS_REG);
  466. regs[26] = dsaf_read_dev(drv, GMAC_RX_PKTS_512TO1023OCTETS_REG);
  467. regs[27] = dsaf_read_dev(drv, GMAC_RX_PKTS_1024TO1518OCTETS_REG);
  468. regs[28] = dsaf_read_dev(drv, GMAC_RX_PKTS_1519TOMAXOCTETS_REG);
  469. regs[29] = dsaf_read_dev(drv, GMAC_RX_FCS_ERRORS_REG);
  470. regs[30] = dsaf_read_dev(drv, GMAC_RX_TAGGED_REG);
  471. regs[31] = dsaf_read_dev(drv, GMAC_RX_DATA_ERR_REG);
  472. regs[32] = dsaf_read_dev(drv, GMAC_RX_ALIGN_ERRORS_REG);
  473. regs[33] = dsaf_read_dev(drv, GMAC_RX_LONG_ERRORS_REG);
  474. regs[34] = dsaf_read_dev(drv, GMAC_RX_JABBER_ERRORS_REG);
  475. regs[35] = dsaf_read_dev(drv, GMAC_RX_PAUSE_MACCTRL_FRAM_REG);
  476. regs[36] = dsaf_read_dev(drv, GMAC_RX_UNKNOWN_MACCTRL_FRAM_REG);
  477. regs[37] = dsaf_read_dev(drv, GMAC_RX_VERY_LONG_ERR_CNT_REG);
  478. regs[38] = dsaf_read_dev(drv, GMAC_RX_RUNT_ERR_CNT_REG);
  479. regs[39] = dsaf_read_dev(drv, GMAC_RX_SHORT_ERR_CNT_REG);
  480. regs[40] = dsaf_read_dev(drv, GMAC_RX_FILT_PKT_CNT_REG);
  481. regs[41] = dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_FILT_REG);
  482. /* tx static registers */
  483. regs[42] = dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_OK_REG);
  484. regs[43] = dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_BAD_REG);
  485. regs[44] = dsaf_read_dev(drv, GMAC_TX_UC_PKTS_REG);
  486. regs[45] = dsaf_read_dev(drv, GMAC_TX_MC_PKTS_REG);
  487. regs[46] = dsaf_read_dev(drv, GMAC_TX_BC_PKTS_REG);
  488. regs[47] = dsaf_read_dev(drv, GMAC_TX_PKTS_64OCTETS_REG);
  489. regs[48] = dsaf_read_dev(drv, GMAC_TX_PKTS_65TO127OCTETS_REG);
  490. regs[49] = dsaf_read_dev(drv, GMAC_TX_PKTS_128TO255OCTETS_REG);
  491. regs[50] = dsaf_read_dev(drv, GMAC_TX_PKTS_255TO511OCTETS_REG);
  492. regs[51] = dsaf_read_dev(drv, GMAC_TX_PKTS_512TO1023OCTETS_REG);
  493. regs[52] = dsaf_read_dev(drv, GMAC_TX_PKTS_1024TO1518OCTETS_REG);
  494. regs[53] = dsaf_read_dev(drv, GMAC_TX_PKTS_1519TOMAXOCTETS_REG);
  495. regs[54] = dsaf_read_dev(drv, GMAC_TX_EXCESSIVE_LENGTH_DROP_REG);
  496. regs[55] = dsaf_read_dev(drv, GMAC_TX_UNDERRUN_REG);
  497. regs[56] = dsaf_read_dev(drv, GMAC_TX_TAGGED_REG);
  498. regs[57] = dsaf_read_dev(drv, GMAC_TX_CRC_ERROR_REG);
  499. regs[58] = dsaf_read_dev(drv, GMAC_TX_PAUSE_FRAMES_REG);
  500. regs[59] = dsaf_read_dev(drv, GAMC_RX_MAX_FRAME);
  501. regs[60] = dsaf_read_dev(drv, GMAC_LINE_LOOP_BACK_REG);
  502. regs[61] = dsaf_read_dev(drv, GMAC_CF_CRC_STRIP_REG);
  503. regs[62] = dsaf_read_dev(drv, GMAC_MODE_CHANGE_EN_REG);
  504. regs[63] = dsaf_read_dev(drv, GMAC_SIXTEEN_BIT_CNTR_REG);
  505. regs[64] = dsaf_read_dev(drv, GMAC_LD_LINK_COUNTER_REG);
  506. regs[65] = dsaf_read_dev(drv, GMAC_LOOP_REG);
  507. regs[66] = dsaf_read_dev(drv, GMAC_RECV_CONTROL_REG);
  508. regs[67] = dsaf_read_dev(drv, GMAC_VLAN_CODE_REG);
  509. regs[68] = dsaf_read_dev(drv, GMAC_RX_OVERRUN_CNT_REG);
  510. regs[69] = dsaf_read_dev(drv, GMAC_RX_LENGTHFIELD_ERR_CNT_REG);
  511. regs[70] = dsaf_read_dev(drv, GMAC_RX_FAIL_COMMA_CNT_REG);
  512. regs[71] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_0_REG);
  513. regs[72] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_0_REG);
  514. regs[73] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_1_REG);
  515. regs[74] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_1_REG);
  516. regs[75] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_2_REG);
  517. regs[76] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_2_REG);
  518. regs[77] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_3_REG);
  519. regs[78] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_3_REG);
  520. regs[79] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_4_REG);
  521. regs[80] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_4_REG);
  522. regs[81] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_5_REG);
  523. regs[82] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_5_REG);
  524. regs[83] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_MSK_0_REG);
  525. regs[84] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_MSK_0_REG);
  526. regs[85] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_MSK_1_REG);
  527. regs[86] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_MSK_1_REG);
  528. regs[87] = dsaf_read_dev(drv, GMAC_MAC_SKIP_LEN_REG);
  529. regs[88] = dsaf_read_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG);
  530. /* mark end of mac regs */
  531. for (i = 89; i < 96; i++)
  532. regs[i] = 0xaaaaaaaa;
  533. }
  534. static void hns_gmac_get_stats(void *mac_drv, u64 *data)
  535. {
  536. u32 i;
  537. u64 *buf = data;
  538. struct mac_driver *drv = (struct mac_driver *)mac_drv;
  539. struct mac_hw_stats *hw_stats = NULL;
  540. hw_stats = &drv->mac_cb->hw_stats;
  541. for (i = 0; i < ARRAY_SIZE(g_gmac_stats_string); i++) {
  542. buf[i] = DSAF_STATS_READ(hw_stats,
  543. g_gmac_stats_string[i].offset);
  544. }
  545. }
  546. static void hns_gmac_get_strings(u32 stringset, u8 *data)
  547. {
  548. char *buff = (char *)data;
  549. u32 i;
  550. if (stringset != ETH_SS_STATS)
  551. return;
  552. for (i = 0; i < ARRAY_SIZE(g_gmac_stats_string); i++) {
  553. snprintf(buff, ETH_GSTRING_LEN, g_gmac_stats_string[i].desc);
  554. buff = buff + ETH_GSTRING_LEN;
  555. }
  556. }
  557. static int hns_gmac_get_sset_count(int stringset)
  558. {
  559. if (stringset == ETH_SS_STATS)
  560. return ARRAY_SIZE(g_gmac_stats_string);
  561. return 0;
  562. }
  563. static int hns_gmac_get_regs_count(void)
  564. {
  565. return ETH_GMAC_DUMP_NUM;
  566. }
  567. void *hns_gmac_config(struct hns_mac_cb *mac_cb, struct mac_params *mac_param)
  568. {
  569. struct mac_driver *mac_drv;
  570. mac_drv = devm_kzalloc(mac_cb->dev, sizeof(*mac_drv), GFP_KERNEL);
  571. if (!mac_drv)
  572. return NULL;
  573. mac_drv->mac_init = hns_gmac_init;
  574. mac_drv->mac_enable = hns_gmac_enable;
  575. mac_drv->mac_disable = hns_gmac_disable;
  576. mac_drv->mac_free = hns_gmac_free;
  577. mac_drv->adjust_link = hns_gmac_adjust_link;
  578. mac_drv->set_tx_auto_pause_frames = hns_gmac_set_tx_auto_pause_frames;
  579. mac_drv->config_max_frame_length = hns_gmac_config_max_frame_length;
  580. mac_drv->mac_pausefrm_cfg = hns_gmac_pause_frm_cfg;
  581. mac_drv->mac_id = mac_param->mac_id;
  582. mac_drv->mac_mode = mac_param->mac_mode;
  583. mac_drv->io_base = mac_param->vaddr;
  584. mac_drv->dev = mac_param->dev;
  585. mac_drv->mac_cb = mac_cb;
  586. mac_drv->set_mac_addr = hns_gmac_set_mac_addr;
  587. mac_drv->set_an_mode = hns_gmac_config_an_mode;
  588. mac_drv->config_loopback = hns_gmac_config_loopback;
  589. mac_drv->config_pad_and_crc = hns_gmac_config_pad_and_crc;
  590. mac_drv->config_half_duplex = hns_gmac_set_duplex_type;
  591. mac_drv->set_rx_ignore_pause_frames = hns_gmac_set_rx_auto_pause_frames;
  592. mac_drv->mac_get_id = hns_gmac_get_id;
  593. mac_drv->get_info = hns_gmac_get_info;
  594. mac_drv->autoneg_stat = hns_gmac_autoneg_stat;
  595. mac_drv->get_pause_enable = hns_gmac_get_pausefrm_cfg;
  596. mac_drv->get_link_status = hns_gmac_get_link_status;
  597. mac_drv->get_regs = hns_gmac_get_regs;
  598. mac_drv->get_regs_count = hns_gmac_get_regs_count;
  599. mac_drv->get_ethtool_stats = hns_gmac_get_stats;
  600. mac_drv->get_sset_count = hns_gmac_get_sset_count;
  601. mac_drv->get_strings = hns_gmac_get_strings;
  602. mac_drv->update_stats = hns_gmac_update_stats;
  603. return (void *)mac_drv;
  604. }