i40e_dcb.c 26 KB

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  1. /*******************************************************************************
  2. *
  3. * Intel Ethernet Controller XL710 Family Linux Driver
  4. * Copyright(c) 2013 - 2014 Intel Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along
  16. * with this program. If not, see <http://www.gnu.org/licenses/>.
  17. *
  18. * The full GNU General Public License is included in this distribution in
  19. * the file called "COPYING".
  20. *
  21. * Contact Information:
  22. * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24. *
  25. ******************************************************************************/
  26. #include "i40e_adminq.h"
  27. #include "i40e_prototype.h"
  28. #include "i40e_dcb.h"
  29. /**
  30. * i40e_get_dcbx_status
  31. * @hw: pointer to the hw struct
  32. * @status: Embedded DCBX Engine Status
  33. *
  34. * Get the DCBX status from the Firmware
  35. **/
  36. i40e_status i40e_get_dcbx_status(struct i40e_hw *hw, u16 *status)
  37. {
  38. u32 reg;
  39. if (!status)
  40. return I40E_ERR_PARAM;
  41. reg = rd32(hw, I40E_PRTDCB_GENS);
  42. *status = (u16)((reg & I40E_PRTDCB_GENS_DCBX_STATUS_MASK) >>
  43. I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT);
  44. return 0;
  45. }
  46. /**
  47. * i40e_parse_ieee_etscfg_tlv
  48. * @tlv: IEEE 802.1Qaz ETS CFG TLV
  49. * @dcbcfg: Local store to update ETS CFG data
  50. *
  51. * Parses IEEE 802.1Qaz ETS CFG TLV
  52. **/
  53. static void i40e_parse_ieee_etscfg_tlv(struct i40e_lldp_org_tlv *tlv,
  54. struct i40e_dcbx_config *dcbcfg)
  55. {
  56. struct i40e_dcb_ets_config *etscfg;
  57. u8 *buf = tlv->tlvinfo;
  58. u16 offset = 0;
  59. u8 priority;
  60. int i;
  61. /* First Octet post subtype
  62. * --------------------------
  63. * |will-|CBS | Re- | Max |
  64. * |ing | |served| TCs |
  65. * --------------------------
  66. * |1bit | 1bit|3 bits|3bits|
  67. */
  68. etscfg = &dcbcfg->etscfg;
  69. etscfg->willing = (u8)((buf[offset] & I40E_IEEE_ETS_WILLING_MASK) >>
  70. I40E_IEEE_ETS_WILLING_SHIFT);
  71. etscfg->cbs = (u8)((buf[offset] & I40E_IEEE_ETS_CBS_MASK) >>
  72. I40E_IEEE_ETS_CBS_SHIFT);
  73. etscfg->maxtcs = (u8)((buf[offset] & I40E_IEEE_ETS_MAXTC_MASK) >>
  74. I40E_IEEE_ETS_MAXTC_SHIFT);
  75. /* Move offset to Priority Assignment Table */
  76. offset++;
  77. /* Priority Assignment Table (4 octets)
  78. * Octets:| 1 | 2 | 3 | 4 |
  79. * -----------------------------------------
  80. * |pri0|pri1|pri2|pri3|pri4|pri5|pri6|pri7|
  81. * -----------------------------------------
  82. * Bits:|7 4|3 0|7 4|3 0|7 4|3 0|7 4|3 0|
  83. * -----------------------------------------
  84. */
  85. for (i = 0; i < 4; i++) {
  86. priority = (u8)((buf[offset] & I40E_IEEE_ETS_PRIO_1_MASK) >>
  87. I40E_IEEE_ETS_PRIO_1_SHIFT);
  88. etscfg->prioritytable[i * 2] = priority;
  89. priority = (u8)((buf[offset] & I40E_IEEE_ETS_PRIO_0_MASK) >>
  90. I40E_IEEE_ETS_PRIO_0_SHIFT);
  91. etscfg->prioritytable[i * 2 + 1] = priority;
  92. offset++;
  93. }
  94. /* TC Bandwidth Table (8 octets)
  95. * Octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
  96. * ---------------------------------
  97. * |tc0|tc1|tc2|tc3|tc4|tc5|tc6|tc7|
  98. * ---------------------------------
  99. */
  100. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
  101. etscfg->tcbwtable[i] = buf[offset++];
  102. /* TSA Assignment Table (8 octets)
  103. * Octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
  104. * ---------------------------------
  105. * |tc0|tc1|tc2|tc3|tc4|tc5|tc6|tc7|
  106. * ---------------------------------
  107. */
  108. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
  109. etscfg->tsatable[i] = buf[offset++];
  110. }
  111. /**
  112. * i40e_parse_ieee_etsrec_tlv
  113. * @tlv: IEEE 802.1Qaz ETS REC TLV
  114. * @dcbcfg: Local store to update ETS REC data
  115. *
  116. * Parses IEEE 802.1Qaz ETS REC TLV
  117. **/
  118. static void i40e_parse_ieee_etsrec_tlv(struct i40e_lldp_org_tlv *tlv,
  119. struct i40e_dcbx_config *dcbcfg)
  120. {
  121. u8 *buf = tlv->tlvinfo;
  122. u16 offset = 0;
  123. u8 priority;
  124. int i;
  125. /* Move offset to priority table */
  126. offset++;
  127. /* Priority Assignment Table (4 octets)
  128. * Octets:| 1 | 2 | 3 | 4 |
  129. * -----------------------------------------
  130. * |pri0|pri1|pri2|pri3|pri4|pri5|pri6|pri7|
  131. * -----------------------------------------
  132. * Bits:|7 4|3 0|7 4|3 0|7 4|3 0|7 4|3 0|
  133. * -----------------------------------------
  134. */
  135. for (i = 0; i < 4; i++) {
  136. priority = (u8)((buf[offset] & I40E_IEEE_ETS_PRIO_1_MASK) >>
  137. I40E_IEEE_ETS_PRIO_1_SHIFT);
  138. dcbcfg->etsrec.prioritytable[i*2] = priority;
  139. priority = (u8)((buf[offset] & I40E_IEEE_ETS_PRIO_0_MASK) >>
  140. I40E_IEEE_ETS_PRIO_0_SHIFT);
  141. dcbcfg->etsrec.prioritytable[i*2 + 1] = priority;
  142. offset++;
  143. }
  144. /* TC Bandwidth Table (8 octets)
  145. * Octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
  146. * ---------------------------------
  147. * |tc0|tc1|tc2|tc3|tc4|tc5|tc6|tc7|
  148. * ---------------------------------
  149. */
  150. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
  151. dcbcfg->etsrec.tcbwtable[i] = buf[offset++];
  152. /* TSA Assignment Table (8 octets)
  153. * Octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
  154. * ---------------------------------
  155. * |tc0|tc1|tc2|tc3|tc4|tc5|tc6|tc7|
  156. * ---------------------------------
  157. */
  158. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
  159. dcbcfg->etsrec.tsatable[i] = buf[offset++];
  160. }
  161. /**
  162. * i40e_parse_ieee_pfccfg_tlv
  163. * @tlv: IEEE 802.1Qaz PFC CFG TLV
  164. * @dcbcfg: Local store to update PFC CFG data
  165. *
  166. * Parses IEEE 802.1Qaz PFC CFG TLV
  167. **/
  168. static void i40e_parse_ieee_pfccfg_tlv(struct i40e_lldp_org_tlv *tlv,
  169. struct i40e_dcbx_config *dcbcfg)
  170. {
  171. u8 *buf = tlv->tlvinfo;
  172. /* ----------------------------------------
  173. * |will-|MBC | Re- | PFC | PFC Enable |
  174. * |ing | |served| cap | |
  175. * -----------------------------------------
  176. * |1bit | 1bit|2 bits|4bits| 1 octet |
  177. */
  178. dcbcfg->pfc.willing = (u8)((buf[0] & I40E_IEEE_PFC_WILLING_MASK) >>
  179. I40E_IEEE_PFC_WILLING_SHIFT);
  180. dcbcfg->pfc.mbc = (u8)((buf[0] & I40E_IEEE_PFC_MBC_MASK) >>
  181. I40E_IEEE_PFC_MBC_SHIFT);
  182. dcbcfg->pfc.pfccap = (u8)((buf[0] & I40E_IEEE_PFC_CAP_MASK) >>
  183. I40E_IEEE_PFC_CAP_SHIFT);
  184. dcbcfg->pfc.pfcenable = buf[1];
  185. }
  186. /**
  187. * i40e_parse_ieee_app_tlv
  188. * @tlv: IEEE 802.1Qaz APP TLV
  189. * @dcbcfg: Local store to update APP PRIO data
  190. *
  191. * Parses IEEE 802.1Qaz APP PRIO TLV
  192. **/
  193. static void i40e_parse_ieee_app_tlv(struct i40e_lldp_org_tlv *tlv,
  194. struct i40e_dcbx_config *dcbcfg)
  195. {
  196. u16 typelength;
  197. u16 offset = 0;
  198. u16 length;
  199. int i = 0;
  200. u8 *buf;
  201. typelength = ntohs(tlv->typelength);
  202. length = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >>
  203. I40E_LLDP_TLV_LEN_SHIFT);
  204. buf = tlv->tlvinfo;
  205. /* The App priority table starts 5 octets after TLV header */
  206. length -= (sizeof(tlv->ouisubtype) + 1);
  207. /* Move offset to App Priority Table */
  208. offset++;
  209. /* Application Priority Table (3 octets)
  210. * Octets:| 1 | 2 | 3 |
  211. * -----------------------------------------
  212. * |Priority|Rsrvd| Sel | Protocol ID |
  213. * -----------------------------------------
  214. * Bits:|23 21|20 19|18 16|15 0|
  215. * -----------------------------------------
  216. */
  217. while (offset < length) {
  218. dcbcfg->app[i].priority = (u8)((buf[offset] &
  219. I40E_IEEE_APP_PRIO_MASK) >>
  220. I40E_IEEE_APP_PRIO_SHIFT);
  221. dcbcfg->app[i].selector = (u8)((buf[offset] &
  222. I40E_IEEE_APP_SEL_MASK) >>
  223. I40E_IEEE_APP_SEL_SHIFT);
  224. dcbcfg->app[i].protocolid = (buf[offset + 1] << 0x8) |
  225. buf[offset + 2];
  226. /* Move to next app */
  227. offset += 3;
  228. i++;
  229. if (i >= I40E_DCBX_MAX_APPS)
  230. break;
  231. }
  232. dcbcfg->numapps = i;
  233. }
  234. /**
  235. * i40e_parse_ieee_etsrec_tlv
  236. * @tlv: IEEE 802.1Qaz TLV
  237. * @dcbcfg: Local store to update ETS REC data
  238. *
  239. * Get the TLV subtype and send it to parsing function
  240. * based on the subtype value
  241. **/
  242. static void i40e_parse_ieee_tlv(struct i40e_lldp_org_tlv *tlv,
  243. struct i40e_dcbx_config *dcbcfg)
  244. {
  245. u32 ouisubtype;
  246. u8 subtype;
  247. ouisubtype = ntohl(tlv->ouisubtype);
  248. subtype = (u8)((ouisubtype & I40E_LLDP_TLV_SUBTYPE_MASK) >>
  249. I40E_LLDP_TLV_SUBTYPE_SHIFT);
  250. switch (subtype) {
  251. case I40E_IEEE_SUBTYPE_ETS_CFG:
  252. i40e_parse_ieee_etscfg_tlv(tlv, dcbcfg);
  253. break;
  254. case I40E_IEEE_SUBTYPE_ETS_REC:
  255. i40e_parse_ieee_etsrec_tlv(tlv, dcbcfg);
  256. break;
  257. case I40E_IEEE_SUBTYPE_PFC_CFG:
  258. i40e_parse_ieee_pfccfg_tlv(tlv, dcbcfg);
  259. break;
  260. case I40E_IEEE_SUBTYPE_APP_PRI:
  261. i40e_parse_ieee_app_tlv(tlv, dcbcfg);
  262. break;
  263. default:
  264. break;
  265. }
  266. }
  267. /**
  268. * i40e_parse_cee_pgcfg_tlv
  269. * @tlv: CEE DCBX PG CFG TLV
  270. * @dcbcfg: Local store to update ETS CFG data
  271. *
  272. * Parses CEE DCBX PG CFG TLV
  273. **/
  274. static void i40e_parse_cee_pgcfg_tlv(struct i40e_cee_feat_tlv *tlv,
  275. struct i40e_dcbx_config *dcbcfg)
  276. {
  277. struct i40e_dcb_ets_config *etscfg;
  278. u8 *buf = tlv->tlvinfo;
  279. u16 offset = 0;
  280. u8 priority;
  281. int i;
  282. etscfg = &dcbcfg->etscfg;
  283. if (tlv->en_will_err & I40E_CEE_FEAT_TLV_WILLING_MASK)
  284. etscfg->willing = 1;
  285. etscfg->cbs = 0;
  286. /* Priority Group Table (4 octets)
  287. * Octets:| 1 | 2 | 3 | 4 |
  288. * -----------------------------------------
  289. * |pri0|pri1|pri2|pri3|pri4|pri5|pri6|pri7|
  290. * -----------------------------------------
  291. * Bits:|7 4|3 0|7 4|3 0|7 4|3 0|7 4|3 0|
  292. * -----------------------------------------
  293. */
  294. for (i = 0; i < 4; i++) {
  295. priority = (u8)((buf[offset] & I40E_CEE_PGID_PRIO_1_MASK) >>
  296. I40E_CEE_PGID_PRIO_1_SHIFT);
  297. etscfg->prioritytable[i * 2] = priority;
  298. priority = (u8)((buf[offset] & I40E_CEE_PGID_PRIO_0_MASK) >>
  299. I40E_CEE_PGID_PRIO_0_SHIFT);
  300. etscfg->prioritytable[i * 2 + 1] = priority;
  301. offset++;
  302. }
  303. /* PG Percentage Table (8 octets)
  304. * Octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
  305. * ---------------------------------
  306. * |pg0|pg1|pg2|pg3|pg4|pg5|pg6|pg7|
  307. * ---------------------------------
  308. */
  309. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
  310. etscfg->tcbwtable[i] = buf[offset++];
  311. /* Number of TCs supported (1 octet) */
  312. etscfg->maxtcs = buf[offset];
  313. }
  314. /**
  315. * i40e_parse_cee_pfccfg_tlv
  316. * @tlv: CEE DCBX PFC CFG TLV
  317. * @dcbcfg: Local store to update PFC CFG data
  318. *
  319. * Parses CEE DCBX PFC CFG TLV
  320. **/
  321. static void i40e_parse_cee_pfccfg_tlv(struct i40e_cee_feat_tlv *tlv,
  322. struct i40e_dcbx_config *dcbcfg)
  323. {
  324. u8 *buf = tlv->tlvinfo;
  325. if (tlv->en_will_err & I40E_CEE_FEAT_TLV_WILLING_MASK)
  326. dcbcfg->pfc.willing = 1;
  327. /* ------------------------
  328. * | PFC Enable | PFC TCs |
  329. * ------------------------
  330. * | 1 octet | 1 octet |
  331. */
  332. dcbcfg->pfc.pfcenable = buf[0];
  333. dcbcfg->pfc.pfccap = buf[1];
  334. }
  335. /**
  336. * i40e_parse_cee_app_tlv
  337. * @tlv: CEE DCBX APP TLV
  338. * @dcbcfg: Local store to update APP PRIO data
  339. *
  340. * Parses CEE DCBX APP PRIO TLV
  341. **/
  342. static void i40e_parse_cee_app_tlv(struct i40e_cee_feat_tlv *tlv,
  343. struct i40e_dcbx_config *dcbcfg)
  344. {
  345. u16 length, typelength, offset = 0;
  346. struct i40e_cee_app_prio *app;
  347. u8 i, up, selector;
  348. typelength = ntohs(tlv->hdr.typelen);
  349. length = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >>
  350. I40E_LLDP_TLV_LEN_SHIFT);
  351. dcbcfg->numapps = length / sizeof(*app);
  352. if (!dcbcfg->numapps)
  353. return;
  354. for (i = 0; i < dcbcfg->numapps; i++) {
  355. app = (struct i40e_cee_app_prio *)(tlv->tlvinfo + offset);
  356. for (up = 0; up < I40E_MAX_USER_PRIORITY; up++) {
  357. if (app->prio_map & BIT(up))
  358. break;
  359. }
  360. dcbcfg->app[i].priority = up;
  361. /* Get Selector from lower 2 bits, and convert to IEEE */
  362. selector = (app->upper_oui_sel & I40E_CEE_APP_SELECTOR_MASK);
  363. if (selector == I40E_CEE_APP_SEL_ETHTYPE)
  364. dcbcfg->app[i].selector = I40E_APP_SEL_ETHTYPE;
  365. else if (selector == I40E_CEE_APP_SEL_TCPIP)
  366. dcbcfg->app[i].selector = I40E_APP_SEL_TCPIP;
  367. else
  368. /* Keep selector as it is for unknown types */
  369. dcbcfg->app[i].selector = selector;
  370. dcbcfg->app[i].protocolid = ntohs(app->protocol);
  371. /* Move to next app */
  372. offset += sizeof(*app);
  373. }
  374. }
  375. /**
  376. * i40e_parse_cee_tlv
  377. * @tlv: CEE DCBX TLV
  378. * @dcbcfg: Local store to update DCBX config data
  379. *
  380. * Get the TLV subtype and send it to parsing function
  381. * based on the subtype value
  382. **/
  383. static void i40e_parse_cee_tlv(struct i40e_lldp_org_tlv *tlv,
  384. struct i40e_dcbx_config *dcbcfg)
  385. {
  386. u16 len, tlvlen, sublen, typelength;
  387. struct i40e_cee_feat_tlv *sub_tlv;
  388. u8 subtype, feat_tlv_count = 0;
  389. u32 ouisubtype;
  390. ouisubtype = ntohl(tlv->ouisubtype);
  391. subtype = (u8)((ouisubtype & I40E_LLDP_TLV_SUBTYPE_MASK) >>
  392. I40E_LLDP_TLV_SUBTYPE_SHIFT);
  393. /* Return if not CEE DCBX */
  394. if (subtype != I40E_CEE_DCBX_TYPE)
  395. return;
  396. typelength = ntohs(tlv->typelength);
  397. tlvlen = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >>
  398. I40E_LLDP_TLV_LEN_SHIFT);
  399. len = sizeof(tlv->typelength) + sizeof(ouisubtype) +
  400. sizeof(struct i40e_cee_ctrl_tlv);
  401. /* Return if no CEE DCBX Feature TLVs */
  402. if (tlvlen <= len)
  403. return;
  404. sub_tlv = (struct i40e_cee_feat_tlv *)((char *)tlv + len);
  405. while (feat_tlv_count < I40E_CEE_MAX_FEAT_TYPE) {
  406. typelength = ntohs(sub_tlv->hdr.typelen);
  407. sublen = (u16)((typelength &
  408. I40E_LLDP_TLV_LEN_MASK) >>
  409. I40E_LLDP_TLV_LEN_SHIFT);
  410. subtype = (u8)((typelength & I40E_LLDP_TLV_TYPE_MASK) >>
  411. I40E_LLDP_TLV_TYPE_SHIFT);
  412. switch (subtype) {
  413. case I40E_CEE_SUBTYPE_PG_CFG:
  414. i40e_parse_cee_pgcfg_tlv(sub_tlv, dcbcfg);
  415. break;
  416. case I40E_CEE_SUBTYPE_PFC_CFG:
  417. i40e_parse_cee_pfccfg_tlv(sub_tlv, dcbcfg);
  418. break;
  419. case I40E_CEE_SUBTYPE_APP_PRI:
  420. i40e_parse_cee_app_tlv(sub_tlv, dcbcfg);
  421. break;
  422. default:
  423. return; /* Invalid Sub-type return */
  424. }
  425. feat_tlv_count++;
  426. /* Move to next sub TLV */
  427. sub_tlv = (struct i40e_cee_feat_tlv *)((char *)sub_tlv +
  428. sizeof(sub_tlv->hdr.typelen) +
  429. sublen);
  430. }
  431. }
  432. /**
  433. * i40e_parse_org_tlv
  434. * @tlv: Organization specific TLV
  435. * @dcbcfg: Local store to update ETS REC data
  436. *
  437. * Currently only IEEE 802.1Qaz TLV is supported, all others
  438. * will be returned
  439. **/
  440. static void i40e_parse_org_tlv(struct i40e_lldp_org_tlv *tlv,
  441. struct i40e_dcbx_config *dcbcfg)
  442. {
  443. u32 ouisubtype;
  444. u32 oui;
  445. ouisubtype = ntohl(tlv->ouisubtype);
  446. oui = (u32)((ouisubtype & I40E_LLDP_TLV_OUI_MASK) >>
  447. I40E_LLDP_TLV_OUI_SHIFT);
  448. switch (oui) {
  449. case I40E_IEEE_8021QAZ_OUI:
  450. i40e_parse_ieee_tlv(tlv, dcbcfg);
  451. break;
  452. case I40E_CEE_DCBX_OUI:
  453. i40e_parse_cee_tlv(tlv, dcbcfg);
  454. break;
  455. default:
  456. break;
  457. }
  458. }
  459. /**
  460. * i40e_lldp_to_dcb_config
  461. * @lldpmib: LLDPDU to be parsed
  462. * @dcbcfg: store for LLDPDU data
  463. *
  464. * Parse DCB configuration from the LLDPDU
  465. **/
  466. i40e_status i40e_lldp_to_dcb_config(u8 *lldpmib,
  467. struct i40e_dcbx_config *dcbcfg)
  468. {
  469. i40e_status ret = 0;
  470. struct i40e_lldp_org_tlv *tlv;
  471. u16 type;
  472. u16 length;
  473. u16 typelength;
  474. u16 offset = 0;
  475. if (!lldpmib || !dcbcfg)
  476. return I40E_ERR_PARAM;
  477. /* set to the start of LLDPDU */
  478. lldpmib += ETH_HLEN;
  479. tlv = (struct i40e_lldp_org_tlv *)lldpmib;
  480. while (1) {
  481. typelength = ntohs(tlv->typelength);
  482. type = (u16)((typelength & I40E_LLDP_TLV_TYPE_MASK) >>
  483. I40E_LLDP_TLV_TYPE_SHIFT);
  484. length = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >>
  485. I40E_LLDP_TLV_LEN_SHIFT);
  486. offset += sizeof(typelength) + length;
  487. /* END TLV or beyond LLDPDU size */
  488. if ((type == I40E_TLV_TYPE_END) || (offset > I40E_LLDPDU_SIZE))
  489. break;
  490. switch (type) {
  491. case I40E_TLV_TYPE_ORG:
  492. i40e_parse_org_tlv(tlv, dcbcfg);
  493. break;
  494. default:
  495. break;
  496. }
  497. /* Move to next TLV */
  498. tlv = (struct i40e_lldp_org_tlv *)((char *)tlv +
  499. sizeof(tlv->typelength) +
  500. length);
  501. }
  502. return ret;
  503. }
  504. /**
  505. * i40e_aq_get_dcb_config
  506. * @hw: pointer to the hw struct
  507. * @mib_type: mib type for the query
  508. * @bridgetype: bridge type for the query (remote)
  509. * @dcbcfg: store for LLDPDU data
  510. *
  511. * Query DCB configuration from the Firmware
  512. **/
  513. i40e_status i40e_aq_get_dcb_config(struct i40e_hw *hw, u8 mib_type,
  514. u8 bridgetype,
  515. struct i40e_dcbx_config *dcbcfg)
  516. {
  517. i40e_status ret = 0;
  518. struct i40e_virt_mem mem;
  519. u8 *lldpmib;
  520. /* Allocate the LLDPDU */
  521. ret = i40e_allocate_virt_mem(hw, &mem, I40E_LLDPDU_SIZE);
  522. if (ret)
  523. return ret;
  524. lldpmib = (u8 *)mem.va;
  525. ret = i40e_aq_get_lldp_mib(hw, bridgetype, mib_type,
  526. (void *)lldpmib, I40E_LLDPDU_SIZE,
  527. NULL, NULL, NULL);
  528. if (ret)
  529. goto free_mem;
  530. /* Parse LLDP MIB to get dcb configuration */
  531. ret = i40e_lldp_to_dcb_config(lldpmib, dcbcfg);
  532. free_mem:
  533. i40e_free_virt_mem(hw, &mem);
  534. return ret;
  535. }
  536. /**
  537. * i40e_cee_to_dcb_v1_config
  538. * @cee_cfg: pointer to CEE v1 response configuration struct
  539. * @dcbcfg: DCB configuration struct
  540. *
  541. * Convert CEE v1 configuration from firmware to DCB configuration
  542. **/
  543. static void i40e_cee_to_dcb_v1_config(
  544. struct i40e_aqc_get_cee_dcb_cfg_v1_resp *cee_cfg,
  545. struct i40e_dcbx_config *dcbcfg)
  546. {
  547. u16 status, tlv_status = le16_to_cpu(cee_cfg->tlv_status);
  548. u16 app_prio = le16_to_cpu(cee_cfg->oper_app_prio);
  549. u8 i, tc, err;
  550. /* CEE PG data to ETS config */
  551. dcbcfg->etscfg.maxtcs = cee_cfg->oper_num_tc;
  552. for (i = 0; i < 4; i++) {
  553. tc = (u8)((cee_cfg->oper_prio_tc[i] &
  554. I40E_CEE_PGID_PRIO_1_MASK) >>
  555. I40E_CEE_PGID_PRIO_1_SHIFT);
  556. dcbcfg->etscfg.prioritytable[i*2] = tc;
  557. tc = (u8)((cee_cfg->oper_prio_tc[i] &
  558. I40E_CEE_PGID_PRIO_0_MASK) >>
  559. I40E_CEE_PGID_PRIO_0_SHIFT);
  560. dcbcfg->etscfg.prioritytable[i*2 + 1] = tc;
  561. }
  562. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
  563. dcbcfg->etscfg.tcbwtable[i] = cee_cfg->oper_tc_bw[i];
  564. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
  565. if (dcbcfg->etscfg.prioritytable[i] == I40E_CEE_PGID_STRICT) {
  566. /* Map it to next empty TC */
  567. dcbcfg->etscfg.prioritytable[i] =
  568. cee_cfg->oper_num_tc - 1;
  569. dcbcfg->etscfg.tsatable[i] = I40E_IEEE_TSA_STRICT;
  570. } else {
  571. dcbcfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
  572. }
  573. }
  574. /* CEE PFC data to ETS config */
  575. dcbcfg->pfc.pfcenable = cee_cfg->oper_pfc_en;
  576. dcbcfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
  577. status = (tlv_status & I40E_AQC_CEE_APP_STATUS_MASK) >>
  578. I40E_AQC_CEE_APP_STATUS_SHIFT;
  579. err = (status & I40E_TLV_STATUS_ERR) ? 1 : 0;
  580. /* Add APPs if Error is False */
  581. if (!err) {
  582. /* CEE operating configuration supports FCoE/iSCSI/FIP only */
  583. dcbcfg->numapps = I40E_CEE_OPER_MAX_APPS;
  584. /* FCoE APP */
  585. dcbcfg->app[0].priority =
  586. (app_prio & I40E_AQC_CEE_APP_FCOE_MASK) >>
  587. I40E_AQC_CEE_APP_FCOE_SHIFT;
  588. dcbcfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
  589. dcbcfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
  590. /* iSCSI APP */
  591. dcbcfg->app[1].priority =
  592. (app_prio & I40E_AQC_CEE_APP_ISCSI_MASK) >>
  593. I40E_AQC_CEE_APP_ISCSI_SHIFT;
  594. dcbcfg->app[1].selector = I40E_APP_SEL_TCPIP;
  595. dcbcfg->app[1].protocolid = I40E_APP_PROTOID_ISCSI;
  596. /* FIP APP */
  597. dcbcfg->app[2].priority =
  598. (app_prio & I40E_AQC_CEE_APP_FIP_MASK) >>
  599. I40E_AQC_CEE_APP_FIP_SHIFT;
  600. dcbcfg->app[2].selector = I40E_APP_SEL_ETHTYPE;
  601. dcbcfg->app[2].protocolid = I40E_APP_PROTOID_FIP;
  602. }
  603. }
  604. /**
  605. * i40e_cee_to_dcb_config
  606. * @cee_cfg: pointer to CEE configuration struct
  607. * @dcbcfg: DCB configuration struct
  608. *
  609. * Convert CEE configuration from firmware to DCB configuration
  610. **/
  611. static void i40e_cee_to_dcb_config(
  612. struct i40e_aqc_get_cee_dcb_cfg_resp *cee_cfg,
  613. struct i40e_dcbx_config *dcbcfg)
  614. {
  615. u32 status, tlv_status = le32_to_cpu(cee_cfg->tlv_status);
  616. u16 app_prio = le16_to_cpu(cee_cfg->oper_app_prio);
  617. u8 i, tc, err, sync, oper;
  618. /* CEE PG data to ETS config */
  619. dcbcfg->etscfg.maxtcs = cee_cfg->oper_num_tc;
  620. /* Note that the FW creates the oper_prio_tc nibbles reversed
  621. * from those in the CEE Priority Group sub-TLV.
  622. */
  623. for (i = 0; i < 4; i++) {
  624. tc = (u8)((cee_cfg->oper_prio_tc[i] &
  625. I40E_CEE_PGID_PRIO_0_MASK) >>
  626. I40E_CEE_PGID_PRIO_0_SHIFT);
  627. dcbcfg->etscfg.prioritytable[i * 2] = tc;
  628. tc = (u8)((cee_cfg->oper_prio_tc[i] &
  629. I40E_CEE_PGID_PRIO_1_MASK) >>
  630. I40E_CEE_PGID_PRIO_1_SHIFT);
  631. dcbcfg->etscfg.prioritytable[i * 2 + 1] = tc;
  632. }
  633. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
  634. dcbcfg->etscfg.tcbwtable[i] = cee_cfg->oper_tc_bw[i];
  635. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
  636. if (dcbcfg->etscfg.prioritytable[i] == I40E_CEE_PGID_STRICT) {
  637. /* Map it to next empty TC */
  638. dcbcfg->etscfg.prioritytable[i] =
  639. cee_cfg->oper_num_tc - 1;
  640. dcbcfg->etscfg.tsatable[i] = I40E_IEEE_TSA_STRICT;
  641. } else {
  642. dcbcfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
  643. }
  644. }
  645. /* CEE PFC data to ETS config */
  646. dcbcfg->pfc.pfcenable = cee_cfg->oper_pfc_en;
  647. dcbcfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
  648. i = 0;
  649. status = (tlv_status & I40E_AQC_CEE_FCOE_STATUS_MASK) >>
  650. I40E_AQC_CEE_FCOE_STATUS_SHIFT;
  651. err = (status & I40E_TLV_STATUS_ERR) ? 1 : 0;
  652. sync = (status & I40E_TLV_STATUS_SYNC) ? 1 : 0;
  653. oper = (status & I40E_TLV_STATUS_OPER) ? 1 : 0;
  654. /* Add FCoE APP if Error is False and Oper/Sync is True */
  655. if (!err && sync && oper) {
  656. /* FCoE APP */
  657. dcbcfg->app[i].priority =
  658. (app_prio & I40E_AQC_CEE_APP_FCOE_MASK) >>
  659. I40E_AQC_CEE_APP_FCOE_SHIFT;
  660. dcbcfg->app[i].selector = I40E_APP_SEL_ETHTYPE;
  661. dcbcfg->app[i].protocolid = I40E_APP_PROTOID_FCOE;
  662. i++;
  663. }
  664. status = (tlv_status & I40E_AQC_CEE_ISCSI_STATUS_MASK) >>
  665. I40E_AQC_CEE_ISCSI_STATUS_SHIFT;
  666. err = (status & I40E_TLV_STATUS_ERR) ? 1 : 0;
  667. sync = (status & I40E_TLV_STATUS_SYNC) ? 1 : 0;
  668. oper = (status & I40E_TLV_STATUS_OPER) ? 1 : 0;
  669. /* Add iSCSI APP if Error is False and Oper/Sync is True */
  670. if (!err && sync && oper) {
  671. /* iSCSI APP */
  672. dcbcfg->app[i].priority =
  673. (app_prio & I40E_AQC_CEE_APP_ISCSI_MASK) >>
  674. I40E_AQC_CEE_APP_ISCSI_SHIFT;
  675. dcbcfg->app[i].selector = I40E_APP_SEL_TCPIP;
  676. dcbcfg->app[i].protocolid = I40E_APP_PROTOID_ISCSI;
  677. i++;
  678. }
  679. status = (tlv_status & I40E_AQC_CEE_FIP_STATUS_MASK) >>
  680. I40E_AQC_CEE_FIP_STATUS_SHIFT;
  681. err = (status & I40E_TLV_STATUS_ERR) ? 1 : 0;
  682. sync = (status & I40E_TLV_STATUS_SYNC) ? 1 : 0;
  683. oper = (status & I40E_TLV_STATUS_OPER) ? 1 : 0;
  684. /* Add FIP APP if Error is False and Oper/Sync is True */
  685. if (!err && sync && oper) {
  686. /* FIP APP */
  687. dcbcfg->app[i].priority =
  688. (app_prio & I40E_AQC_CEE_APP_FIP_MASK) >>
  689. I40E_AQC_CEE_APP_FIP_SHIFT;
  690. dcbcfg->app[i].selector = I40E_APP_SEL_ETHTYPE;
  691. dcbcfg->app[i].protocolid = I40E_APP_PROTOID_FIP;
  692. i++;
  693. }
  694. dcbcfg->numapps = i;
  695. }
  696. /**
  697. * i40e_get_ieee_dcb_config
  698. * @hw: pointer to the hw struct
  699. *
  700. * Get IEEE mode DCB configuration from the Firmware
  701. **/
  702. static i40e_status i40e_get_ieee_dcb_config(struct i40e_hw *hw)
  703. {
  704. i40e_status ret = 0;
  705. /* IEEE mode */
  706. hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
  707. /* Get Local DCB Config */
  708. ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
  709. &hw->local_dcbx_config);
  710. if (ret)
  711. goto out;
  712. /* Get Remote DCB Config */
  713. ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
  714. I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
  715. &hw->remote_dcbx_config);
  716. /* Don't treat ENOENT as an error for Remote MIBs */
  717. if (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT)
  718. ret = 0;
  719. out:
  720. return ret;
  721. }
  722. /**
  723. * i40e_get_dcb_config
  724. * @hw: pointer to the hw struct
  725. *
  726. * Get DCB configuration from the Firmware
  727. **/
  728. i40e_status i40e_get_dcb_config(struct i40e_hw *hw)
  729. {
  730. i40e_status ret = 0;
  731. struct i40e_aqc_get_cee_dcb_cfg_resp cee_cfg;
  732. struct i40e_aqc_get_cee_dcb_cfg_v1_resp cee_v1_cfg;
  733. /* If Firmware version < v4.33 IEEE only */
  734. if (((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver < 33)) ||
  735. (hw->aq.fw_maj_ver < 4))
  736. return i40e_get_ieee_dcb_config(hw);
  737. /* If Firmware version == v4.33 use old CEE struct */
  738. if ((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver == 33)) {
  739. ret = i40e_aq_get_cee_dcb_config(hw, &cee_v1_cfg,
  740. sizeof(cee_v1_cfg), NULL);
  741. if (!ret) {
  742. /* CEE mode */
  743. hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_CEE;
  744. hw->local_dcbx_config.tlv_status =
  745. le16_to_cpu(cee_v1_cfg.tlv_status);
  746. i40e_cee_to_dcb_v1_config(&cee_v1_cfg,
  747. &hw->local_dcbx_config);
  748. }
  749. } else {
  750. ret = i40e_aq_get_cee_dcb_config(hw, &cee_cfg,
  751. sizeof(cee_cfg), NULL);
  752. if (!ret) {
  753. /* CEE mode */
  754. hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_CEE;
  755. hw->local_dcbx_config.tlv_status =
  756. le32_to_cpu(cee_cfg.tlv_status);
  757. i40e_cee_to_dcb_config(&cee_cfg,
  758. &hw->local_dcbx_config);
  759. }
  760. }
  761. /* CEE mode not enabled try querying IEEE data */
  762. if (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT)
  763. return i40e_get_ieee_dcb_config(hw);
  764. if (ret)
  765. goto out;
  766. /* Get CEE DCB Desired Config */
  767. ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
  768. &hw->desired_dcbx_config);
  769. if (ret)
  770. goto out;
  771. /* Get Remote DCB Config */
  772. ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
  773. I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
  774. &hw->remote_dcbx_config);
  775. /* Don't treat ENOENT as an error for Remote MIBs */
  776. if (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT)
  777. ret = 0;
  778. out:
  779. return ret;
  780. }
  781. /**
  782. * i40e_init_dcb
  783. * @hw: pointer to the hw struct
  784. *
  785. * Update DCB configuration from the Firmware
  786. **/
  787. i40e_status i40e_init_dcb(struct i40e_hw *hw)
  788. {
  789. i40e_status ret = 0;
  790. struct i40e_lldp_variables lldp_cfg;
  791. u8 adminstatus = 0;
  792. if (!hw->func_caps.dcb)
  793. return ret;
  794. /* Read LLDP NVM area */
  795. ret = i40e_read_lldp_cfg(hw, &lldp_cfg);
  796. if (ret)
  797. return ret;
  798. /* Get the LLDP AdminStatus for the current port */
  799. adminstatus = lldp_cfg.adminstatus >> (hw->port * 4);
  800. adminstatus &= 0xF;
  801. /* LLDP agent disabled */
  802. if (!adminstatus) {
  803. hw->dcbx_status = I40E_DCBX_STATUS_DISABLED;
  804. return ret;
  805. }
  806. /* Get DCBX status */
  807. ret = i40e_get_dcbx_status(hw, &hw->dcbx_status);
  808. if (ret)
  809. return ret;
  810. /* Check the DCBX Status */
  811. switch (hw->dcbx_status) {
  812. case I40E_DCBX_STATUS_DONE:
  813. case I40E_DCBX_STATUS_IN_PROGRESS:
  814. /* Get current DCBX configuration */
  815. ret = i40e_get_dcb_config(hw);
  816. if (ret)
  817. return ret;
  818. break;
  819. case I40E_DCBX_STATUS_DISABLED:
  820. return ret;
  821. case I40E_DCBX_STATUS_NOT_STARTED:
  822. case I40E_DCBX_STATUS_MULTIPLE_PEERS:
  823. default:
  824. break;
  825. }
  826. /* Configure the LLDP MIB change event */
  827. ret = i40e_aq_cfg_lldp_mib_change_event(hw, true, NULL);
  828. if (ret)
  829. return ret;
  830. return ret;
  831. }
  832. /**
  833. * i40e_read_lldp_cfg - read LLDP Configuration data from NVM
  834. * @hw: pointer to the HW structure
  835. * @lldp_cfg: pointer to hold lldp configuration variables
  836. *
  837. * Reads the LLDP configuration data from NVM
  838. **/
  839. i40e_status i40e_read_lldp_cfg(struct i40e_hw *hw,
  840. struct i40e_lldp_variables *lldp_cfg)
  841. {
  842. i40e_status ret = 0;
  843. u32 offset = (2 * I40E_NVM_LLDP_CFG_PTR);
  844. if (!lldp_cfg)
  845. return I40E_ERR_PARAM;
  846. ret = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
  847. if (ret)
  848. goto err_lldp_cfg;
  849. ret = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR, offset,
  850. sizeof(struct i40e_lldp_variables),
  851. (u8 *)lldp_cfg,
  852. true, NULL);
  853. i40e_release_nvm(hw);
  854. err_lldp_cfg:
  855. return ret;
  856. }