ixgbe_fcoe.c 29 KB

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  1. /*******************************************************************************
  2. Intel 10 Gigabit PCI Express Linux driver
  3. Copyright(c) 1999 - 2014 Intel Corporation.
  4. This program is free software; you can redistribute it and/or modify it
  5. under the terms and conditions of the GNU General Public License,
  6. version 2, as published by the Free Software Foundation.
  7. This program is distributed in the hope it will be useful, but WITHOUT
  8. ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  9. FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  10. more details.
  11. You should have received a copy of the GNU General Public License along with
  12. this program; if not, write to the Free Software Foundation, Inc.,
  13. 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  14. The full GNU General Public License is included in this distribution in
  15. the file called "COPYING".
  16. Contact Information:
  17. Linux NICS <linux.nics@intel.com>
  18. e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  19. Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  20. *******************************************************************************/
  21. #include "ixgbe.h"
  22. #include <linux/if_ether.h>
  23. #include <linux/gfp.h>
  24. #include <linux/if_vlan.h>
  25. #include <scsi/scsi_cmnd.h>
  26. #include <scsi/scsi_device.h>
  27. #include <scsi/fc/fc_fs.h>
  28. #include <scsi/fc/fc_fcoe.h>
  29. #include <scsi/libfc.h>
  30. #include <scsi/libfcoe.h>
  31. /**
  32. * ixgbe_fcoe_clear_ddp - clear the given ddp context
  33. * @ddp: ptr to the ixgbe_fcoe_ddp
  34. *
  35. * Returns : none
  36. *
  37. */
  38. static inline void ixgbe_fcoe_clear_ddp(struct ixgbe_fcoe_ddp *ddp)
  39. {
  40. ddp->len = 0;
  41. ddp->err = 1;
  42. ddp->udl = NULL;
  43. ddp->udp = 0UL;
  44. ddp->sgl = NULL;
  45. ddp->sgc = 0;
  46. }
  47. /**
  48. * ixgbe_fcoe_ddp_put - free the ddp context for a given xid
  49. * @netdev: the corresponding net_device
  50. * @xid: the xid that corresponding ddp will be freed
  51. *
  52. * This is the implementation of net_device_ops.ndo_fcoe_ddp_done
  53. * and it is expected to be called by ULD, i.e., FCP layer of libfc
  54. * to release the corresponding ddp context when the I/O is done.
  55. *
  56. * Returns : data length already ddp-ed in bytes
  57. */
  58. int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid)
  59. {
  60. int len;
  61. struct ixgbe_fcoe *fcoe;
  62. struct ixgbe_adapter *adapter;
  63. struct ixgbe_fcoe_ddp *ddp;
  64. struct ixgbe_hw *hw;
  65. u32 fcbuff;
  66. if (!netdev)
  67. return 0;
  68. if (xid >= IXGBE_FCOE_DDP_MAX)
  69. return 0;
  70. adapter = netdev_priv(netdev);
  71. fcoe = &adapter->fcoe;
  72. ddp = &fcoe->ddp[xid];
  73. if (!ddp->udl)
  74. return 0;
  75. hw = &adapter->hw;
  76. len = ddp->len;
  77. /* if no error then skip ddp context invalidation */
  78. if (!ddp->err)
  79. goto skip_ddpinv;
  80. if (hw->mac.type == ixgbe_mac_X550) {
  81. /* X550 does not require DDP FCoE lock */
  82. IXGBE_WRITE_REG(hw, IXGBE_FCDFC(0, xid), 0);
  83. IXGBE_WRITE_REG(hw, IXGBE_FCDFC(3, xid),
  84. (xid | IXGBE_FCFLTRW_WE));
  85. /* program FCBUFF */
  86. IXGBE_WRITE_REG(hw, IXGBE_FCDDC(2, xid), 0);
  87. /* program FCDMARW */
  88. IXGBE_WRITE_REG(hw, IXGBE_FCDDC(3, xid),
  89. (xid | IXGBE_FCDMARW_WE));
  90. /* read FCBUFF to check context invalidated */
  91. IXGBE_WRITE_REG(hw, IXGBE_FCDDC(3, xid),
  92. (xid | IXGBE_FCDMARW_RE));
  93. fcbuff = IXGBE_READ_REG(hw, IXGBE_FCDDC(2, xid));
  94. } else {
  95. /* other hardware requires DDP FCoE lock */
  96. spin_lock_bh(&fcoe->lock);
  97. IXGBE_WRITE_REG(hw, IXGBE_FCFLT, 0);
  98. IXGBE_WRITE_REG(hw, IXGBE_FCFLTRW,
  99. (xid | IXGBE_FCFLTRW_WE));
  100. IXGBE_WRITE_REG(hw, IXGBE_FCBUFF, 0);
  101. IXGBE_WRITE_REG(hw, IXGBE_FCDMARW,
  102. (xid | IXGBE_FCDMARW_WE));
  103. /* guaranteed to be invalidated after 100us */
  104. IXGBE_WRITE_REG(hw, IXGBE_FCDMARW,
  105. (xid | IXGBE_FCDMARW_RE));
  106. fcbuff = IXGBE_READ_REG(hw, IXGBE_FCBUFF);
  107. spin_unlock_bh(&fcoe->lock);
  108. }
  109. if (fcbuff & IXGBE_FCBUFF_VALID)
  110. usleep_range(100, 150);
  111. skip_ddpinv:
  112. if (ddp->sgl)
  113. dma_unmap_sg(&adapter->pdev->dev, ddp->sgl, ddp->sgc,
  114. DMA_FROM_DEVICE);
  115. if (ddp->pool) {
  116. dma_pool_free(ddp->pool, ddp->udl, ddp->udp);
  117. ddp->pool = NULL;
  118. }
  119. ixgbe_fcoe_clear_ddp(ddp);
  120. return len;
  121. }
  122. /**
  123. * ixgbe_fcoe_ddp_setup - called to set up ddp context
  124. * @netdev: the corresponding net_device
  125. * @xid: the exchange id requesting ddp
  126. * @sgl: the scatter-gather list for this request
  127. * @sgc: the number of scatter-gather items
  128. *
  129. * Returns : 1 for success and 0 for no ddp
  130. */
  131. static int ixgbe_fcoe_ddp_setup(struct net_device *netdev, u16 xid,
  132. struct scatterlist *sgl, unsigned int sgc,
  133. int target_mode)
  134. {
  135. struct ixgbe_adapter *adapter;
  136. struct ixgbe_hw *hw;
  137. struct ixgbe_fcoe *fcoe;
  138. struct ixgbe_fcoe_ddp *ddp;
  139. struct ixgbe_fcoe_ddp_pool *ddp_pool;
  140. struct scatterlist *sg;
  141. unsigned int i, j, dmacount;
  142. unsigned int len;
  143. static const unsigned int bufflen = IXGBE_FCBUFF_MIN;
  144. unsigned int firstoff = 0;
  145. unsigned int lastsize;
  146. unsigned int thisoff = 0;
  147. unsigned int thislen = 0;
  148. u32 fcbuff, fcdmarw, fcfltrw, fcrxctl;
  149. dma_addr_t addr = 0;
  150. if (!netdev || !sgl)
  151. return 0;
  152. adapter = netdev_priv(netdev);
  153. if (xid >= IXGBE_FCOE_DDP_MAX) {
  154. e_warn(drv, "xid=0x%x out-of-range\n", xid);
  155. return 0;
  156. }
  157. /* no DDP if we are already down or resetting */
  158. if (test_bit(__IXGBE_DOWN, &adapter->state) ||
  159. test_bit(__IXGBE_RESETTING, &adapter->state))
  160. return 0;
  161. fcoe = &adapter->fcoe;
  162. ddp = &fcoe->ddp[xid];
  163. if (ddp->sgl) {
  164. e_err(drv, "xid 0x%x w/ non-null sgl=%p nents=%d\n",
  165. xid, ddp->sgl, ddp->sgc);
  166. return 0;
  167. }
  168. ixgbe_fcoe_clear_ddp(ddp);
  169. if (!fcoe->ddp_pool) {
  170. e_warn(drv, "No ddp_pool resources allocated\n");
  171. return 0;
  172. }
  173. ddp_pool = per_cpu_ptr(fcoe->ddp_pool, get_cpu());
  174. if (!ddp_pool->pool) {
  175. e_warn(drv, "xid=0x%x no ddp pool for fcoe\n", xid);
  176. goto out_noddp;
  177. }
  178. /* setup dma from scsi command sgl */
  179. dmacount = dma_map_sg(&adapter->pdev->dev, sgl, sgc, DMA_FROM_DEVICE);
  180. if (dmacount == 0) {
  181. e_err(drv, "xid 0x%x DMA map error\n", xid);
  182. goto out_noddp;
  183. }
  184. /* alloc the udl from per cpu ddp pool */
  185. ddp->udl = dma_pool_alloc(ddp_pool->pool, GFP_ATOMIC, &ddp->udp);
  186. if (!ddp->udl) {
  187. e_err(drv, "failed allocated ddp context\n");
  188. goto out_noddp_unmap;
  189. }
  190. ddp->pool = ddp_pool->pool;
  191. ddp->sgl = sgl;
  192. ddp->sgc = sgc;
  193. j = 0;
  194. for_each_sg(sgl, sg, dmacount, i) {
  195. addr = sg_dma_address(sg);
  196. len = sg_dma_len(sg);
  197. while (len) {
  198. /* max number of buffers allowed in one DDP context */
  199. if (j >= IXGBE_BUFFCNT_MAX) {
  200. ddp_pool->noddp++;
  201. goto out_noddp_free;
  202. }
  203. /* get the offset of length of current buffer */
  204. thisoff = addr & ((dma_addr_t)bufflen - 1);
  205. thislen = min((bufflen - thisoff), len);
  206. /*
  207. * all but the 1st buffer (j == 0)
  208. * must be aligned on bufflen
  209. */
  210. if ((j != 0) && (thisoff))
  211. goto out_noddp_free;
  212. /*
  213. * all but the last buffer
  214. * ((i == (dmacount - 1)) && (thislen == len))
  215. * must end at bufflen
  216. */
  217. if (((i != (dmacount - 1)) || (thislen != len))
  218. && ((thislen + thisoff) != bufflen))
  219. goto out_noddp_free;
  220. ddp->udl[j] = (u64)(addr - thisoff);
  221. /* only the first buffer may have none-zero offset */
  222. if (j == 0)
  223. firstoff = thisoff;
  224. len -= thislen;
  225. addr += thislen;
  226. j++;
  227. }
  228. }
  229. /* only the last buffer may have non-full bufflen */
  230. lastsize = thisoff + thislen;
  231. /*
  232. * lastsize can not be buffer len.
  233. * If it is then adding another buffer with lastsize = 1.
  234. */
  235. if (lastsize == bufflen) {
  236. if (j >= IXGBE_BUFFCNT_MAX) {
  237. ddp_pool->noddp_ext_buff++;
  238. goto out_noddp_free;
  239. }
  240. ddp->udl[j] = (u64)(fcoe->extra_ddp_buffer_dma);
  241. j++;
  242. lastsize = 1;
  243. }
  244. put_cpu();
  245. fcbuff = (IXGBE_FCBUFF_4KB << IXGBE_FCBUFF_BUFFSIZE_SHIFT);
  246. fcbuff |= ((j & 0xff) << IXGBE_FCBUFF_BUFFCNT_SHIFT);
  247. fcbuff |= (firstoff << IXGBE_FCBUFF_OFFSET_SHIFT);
  248. /* Set WRCONTX bit to allow DDP for target */
  249. if (target_mode)
  250. fcbuff |= (IXGBE_FCBUFF_WRCONTX);
  251. fcbuff |= (IXGBE_FCBUFF_VALID);
  252. fcdmarw = xid;
  253. fcdmarw |= IXGBE_FCDMARW_WE;
  254. fcdmarw |= (lastsize << IXGBE_FCDMARW_LASTSIZE_SHIFT);
  255. fcfltrw = xid;
  256. fcfltrw |= IXGBE_FCFLTRW_WE;
  257. /* program DMA context */
  258. hw = &adapter->hw;
  259. /* turn on last frame indication for target mode as FCP_RSPtarget is
  260. * supposed to send FCP_RSP when it is done. */
  261. if (target_mode && !test_bit(__IXGBE_FCOE_TARGET, &fcoe->mode)) {
  262. set_bit(__IXGBE_FCOE_TARGET, &fcoe->mode);
  263. fcrxctl = IXGBE_READ_REG(hw, IXGBE_FCRXCTRL);
  264. fcrxctl |= IXGBE_FCRXCTRL_LASTSEQH;
  265. IXGBE_WRITE_REG(hw, IXGBE_FCRXCTRL, fcrxctl);
  266. }
  267. if (hw->mac.type == ixgbe_mac_X550) {
  268. /* X550 does not require DDP lock */
  269. IXGBE_WRITE_REG(hw, IXGBE_FCDDC(0, xid),
  270. ddp->udp & DMA_BIT_MASK(32));
  271. IXGBE_WRITE_REG(hw, IXGBE_FCDDC(1, xid), (u64)ddp->udp >> 32);
  272. IXGBE_WRITE_REG(hw, IXGBE_FCDDC(2, xid), fcbuff);
  273. IXGBE_WRITE_REG(hw, IXGBE_FCDDC(3, xid), fcdmarw);
  274. /* program filter context */
  275. IXGBE_WRITE_REG(hw, IXGBE_FCDFC(0, xid), IXGBE_FCFLT_VALID);
  276. IXGBE_WRITE_REG(hw, IXGBE_FCDFC(1, xid), 0);
  277. IXGBE_WRITE_REG(hw, IXGBE_FCDFC(3, xid), fcfltrw);
  278. } else {
  279. /* DDP lock for indirect DDP context access */
  280. spin_lock_bh(&fcoe->lock);
  281. IXGBE_WRITE_REG(hw, IXGBE_FCPTRL, ddp->udp & DMA_BIT_MASK(32));
  282. IXGBE_WRITE_REG(hw, IXGBE_FCPTRH, (u64)ddp->udp >> 32);
  283. IXGBE_WRITE_REG(hw, IXGBE_FCBUFF, fcbuff);
  284. IXGBE_WRITE_REG(hw, IXGBE_FCDMARW, fcdmarw);
  285. /* program filter context */
  286. IXGBE_WRITE_REG(hw, IXGBE_FCPARAM, 0);
  287. IXGBE_WRITE_REG(hw, IXGBE_FCFLT, IXGBE_FCFLT_VALID);
  288. IXGBE_WRITE_REG(hw, IXGBE_FCFLTRW, fcfltrw);
  289. spin_unlock_bh(&fcoe->lock);
  290. }
  291. return 1;
  292. out_noddp_free:
  293. dma_pool_free(ddp->pool, ddp->udl, ddp->udp);
  294. ixgbe_fcoe_clear_ddp(ddp);
  295. out_noddp_unmap:
  296. dma_unmap_sg(&adapter->pdev->dev, sgl, sgc, DMA_FROM_DEVICE);
  297. out_noddp:
  298. put_cpu();
  299. return 0;
  300. }
  301. /**
  302. * ixgbe_fcoe_ddp_get - called to set up ddp context in initiator mode
  303. * @netdev: the corresponding net_device
  304. * @xid: the exchange id requesting ddp
  305. * @sgl: the scatter-gather list for this request
  306. * @sgc: the number of scatter-gather items
  307. *
  308. * This is the implementation of net_device_ops.ndo_fcoe_ddp_setup
  309. * and is expected to be called from ULD, e.g., FCP layer of libfc
  310. * to set up ddp for the corresponding xid of the given sglist for
  311. * the corresponding I/O.
  312. *
  313. * Returns : 1 for success and 0 for no ddp
  314. */
  315. int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
  316. struct scatterlist *sgl, unsigned int sgc)
  317. {
  318. return ixgbe_fcoe_ddp_setup(netdev, xid, sgl, sgc, 0);
  319. }
  320. /**
  321. * ixgbe_fcoe_ddp_target - called to set up ddp context in target mode
  322. * @netdev: the corresponding net_device
  323. * @xid: the exchange id requesting ddp
  324. * @sgl: the scatter-gather list for this request
  325. * @sgc: the number of scatter-gather items
  326. *
  327. * This is the implementation of net_device_ops.ndo_fcoe_ddp_target
  328. * and is expected to be called from ULD, e.g., FCP layer of libfc
  329. * to set up ddp for the corresponding xid of the given sglist for
  330. * the corresponding I/O. The DDP in target mode is a write I/O request
  331. * from the initiator.
  332. *
  333. * Returns : 1 for success and 0 for no ddp
  334. */
  335. int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
  336. struct scatterlist *sgl, unsigned int sgc)
  337. {
  338. return ixgbe_fcoe_ddp_setup(netdev, xid, sgl, sgc, 1);
  339. }
  340. /**
  341. * ixgbe_fcoe_ddp - check ddp status and mark it done
  342. * @adapter: ixgbe adapter
  343. * @rx_desc: advanced rx descriptor
  344. * @skb: the skb holding the received data
  345. *
  346. * This checks ddp status.
  347. *
  348. * Returns : < 0 indicates an error or not a FCiE ddp, 0 indicates
  349. * not passing the skb to ULD, > 0 indicates is the length of data
  350. * being ddped.
  351. */
  352. int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
  353. union ixgbe_adv_rx_desc *rx_desc,
  354. struct sk_buff *skb)
  355. {
  356. int rc = -EINVAL;
  357. struct ixgbe_fcoe *fcoe;
  358. struct ixgbe_fcoe_ddp *ddp;
  359. struct fc_frame_header *fh;
  360. struct fcoe_crc_eof *crc;
  361. __le32 fcerr = ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_FCERR);
  362. __le32 ddp_err;
  363. int ddp_max;
  364. u32 fctl;
  365. u16 xid;
  366. if (fcerr == cpu_to_le32(IXGBE_FCERR_BADCRC))
  367. skb->ip_summed = CHECKSUM_NONE;
  368. else
  369. skb->ip_summed = CHECKSUM_UNNECESSARY;
  370. if (eth_hdr(skb)->h_proto == htons(ETH_P_8021Q))
  371. fh = (struct fc_frame_header *)(skb->data +
  372. sizeof(struct vlan_hdr) + sizeof(struct fcoe_hdr));
  373. else
  374. fh = (struct fc_frame_header *)(skb->data +
  375. sizeof(struct fcoe_hdr));
  376. fctl = ntoh24(fh->fh_f_ctl);
  377. if (fctl & FC_FC_EX_CTX)
  378. xid = be16_to_cpu(fh->fh_ox_id);
  379. else
  380. xid = be16_to_cpu(fh->fh_rx_id);
  381. ddp_max = IXGBE_FCOE_DDP_MAX;
  382. /* X550 has different DDP Max limit */
  383. if (adapter->hw.mac.type == ixgbe_mac_X550)
  384. ddp_max = IXGBE_FCOE_DDP_MAX_X550;
  385. if (xid >= ddp_max)
  386. return -EINVAL;
  387. fcoe = &adapter->fcoe;
  388. ddp = &fcoe->ddp[xid];
  389. if (!ddp->udl)
  390. return -EINVAL;
  391. ddp_err = ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_FCEOFE |
  392. IXGBE_RXDADV_ERR_FCERR);
  393. if (ddp_err)
  394. return -EINVAL;
  395. switch (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_FCSTAT)) {
  396. /* return 0 to bypass going to ULD for DDPed data */
  397. case cpu_to_le32(IXGBE_RXDADV_STAT_FCSTAT_DDP):
  398. /* update length of DDPed data */
  399. ddp->len = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
  400. rc = 0;
  401. break;
  402. /* unmap the sg list when FCPRSP is received */
  403. case cpu_to_le32(IXGBE_RXDADV_STAT_FCSTAT_FCPRSP):
  404. dma_unmap_sg(&adapter->pdev->dev, ddp->sgl,
  405. ddp->sgc, DMA_FROM_DEVICE);
  406. ddp->err = ddp_err;
  407. ddp->sgl = NULL;
  408. ddp->sgc = 0;
  409. /* fall through */
  410. /* if DDP length is present pass it through to ULD */
  411. case cpu_to_le32(IXGBE_RXDADV_STAT_FCSTAT_NODDP):
  412. /* update length of DDPed data */
  413. ddp->len = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
  414. if (ddp->len)
  415. rc = ddp->len;
  416. break;
  417. /* no match will return as an error */
  418. case cpu_to_le32(IXGBE_RXDADV_STAT_FCSTAT_NOMTCH):
  419. default:
  420. break;
  421. }
  422. /* In target mode, check the last data frame of the sequence.
  423. * For DDP in target mode, data is already DDPed but the header
  424. * indication of the last data frame ould allow is to tell if we
  425. * got all the data and the ULP can send FCP_RSP back, as this is
  426. * not a full fcoe frame, we fill the trailer here so it won't be
  427. * dropped by the ULP stack.
  428. */
  429. if ((fh->fh_r_ctl == FC_RCTL_DD_SOL_DATA) &&
  430. (fctl & FC_FC_END_SEQ)) {
  431. skb_linearize(skb);
  432. crc = (struct fcoe_crc_eof *)skb_put(skb, sizeof(*crc));
  433. crc->fcoe_eof = FC_EOF_T;
  434. }
  435. return rc;
  436. }
  437. /**
  438. * ixgbe_fso - ixgbe FCoE Sequence Offload (FSO)
  439. * @tx_ring: tx desc ring
  440. * @first: first tx_buffer structure containing skb, tx_flags, and protocol
  441. * @hdr_len: hdr_len to be returned
  442. *
  443. * This sets up large send offload for FCoE
  444. *
  445. * Returns : 0 indicates success, < 0 for error
  446. */
  447. int ixgbe_fso(struct ixgbe_ring *tx_ring,
  448. struct ixgbe_tx_buffer *first,
  449. u8 *hdr_len)
  450. {
  451. struct sk_buff *skb = first->skb;
  452. struct fc_frame_header *fh;
  453. u32 vlan_macip_lens;
  454. u32 fcoe_sof_eof = 0;
  455. u32 mss_l4len_idx;
  456. u8 sof, eof;
  457. if (skb_is_gso(skb) && (skb_shinfo(skb)->gso_type != SKB_GSO_FCOE)) {
  458. dev_err(tx_ring->dev, "Wrong gso type %d:expecting SKB_GSO_FCOE\n",
  459. skb_shinfo(skb)->gso_type);
  460. return -EINVAL;
  461. }
  462. /* resets the header to point fcoe/fc */
  463. skb_set_network_header(skb, skb->mac_len);
  464. skb_set_transport_header(skb, skb->mac_len +
  465. sizeof(struct fcoe_hdr));
  466. /* sets up SOF and ORIS */
  467. sof = ((struct fcoe_hdr *)skb_network_header(skb))->fcoe_sof;
  468. switch (sof) {
  469. case FC_SOF_I2:
  470. fcoe_sof_eof = IXGBE_ADVTXD_FCOEF_ORIS;
  471. break;
  472. case FC_SOF_I3:
  473. fcoe_sof_eof = IXGBE_ADVTXD_FCOEF_SOF |
  474. IXGBE_ADVTXD_FCOEF_ORIS;
  475. break;
  476. case FC_SOF_N2:
  477. break;
  478. case FC_SOF_N3:
  479. fcoe_sof_eof = IXGBE_ADVTXD_FCOEF_SOF;
  480. break;
  481. default:
  482. dev_warn(tx_ring->dev, "unknown sof = 0x%x\n", sof);
  483. return -EINVAL;
  484. }
  485. /* the first byte of the last dword is EOF */
  486. skb_copy_bits(skb, skb->len - 4, &eof, 1);
  487. /* sets up EOF and ORIE */
  488. switch (eof) {
  489. case FC_EOF_N:
  490. fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_N;
  491. break;
  492. case FC_EOF_T:
  493. /* lso needs ORIE */
  494. if (skb_is_gso(skb))
  495. fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_N |
  496. IXGBE_ADVTXD_FCOEF_ORIE;
  497. else
  498. fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_T;
  499. break;
  500. case FC_EOF_NI:
  501. fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_NI;
  502. break;
  503. case FC_EOF_A:
  504. fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_A;
  505. break;
  506. default:
  507. dev_warn(tx_ring->dev, "unknown eof = 0x%x\n", eof);
  508. return -EINVAL;
  509. }
  510. /* sets up PARINC indicating data offset */
  511. fh = (struct fc_frame_header *)skb_transport_header(skb);
  512. if (fh->fh_f_ctl[2] & FC_FC_REL_OFF)
  513. fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_PARINC;
  514. /* include trailer in headlen as it is replicated per frame */
  515. *hdr_len = sizeof(struct fcoe_crc_eof);
  516. /* hdr_len includes fc_hdr if FCoE LSO is enabled */
  517. if (skb_is_gso(skb)) {
  518. *hdr_len += skb_transport_offset(skb) +
  519. sizeof(struct fc_frame_header);
  520. /* update gso_segs and bytecount */
  521. first->gso_segs = DIV_ROUND_UP(skb->len - *hdr_len,
  522. skb_shinfo(skb)->gso_size);
  523. first->bytecount += (first->gso_segs - 1) * *hdr_len;
  524. first->tx_flags |= IXGBE_TX_FLAGS_TSO;
  525. }
  526. /* set flag indicating FCOE to ixgbe_tx_map call */
  527. first->tx_flags |= IXGBE_TX_FLAGS_FCOE | IXGBE_TX_FLAGS_CC;
  528. /* mss_l4len_id: use 0 for FSO as TSO, no need for L4LEN */
  529. mss_l4len_idx = skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
  530. /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
  531. vlan_macip_lens = skb_transport_offset(skb) +
  532. sizeof(struct fc_frame_header);
  533. vlan_macip_lens |= (skb_transport_offset(skb) - 4)
  534. << IXGBE_ADVTXD_MACLEN_SHIFT;
  535. vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
  536. /* write context desc */
  537. ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fcoe_sof_eof,
  538. IXGBE_ADVTXT_TUCMD_FCOE, mss_l4len_idx);
  539. return 0;
  540. }
  541. static void ixgbe_fcoe_dma_pool_free(struct ixgbe_fcoe *fcoe, unsigned int cpu)
  542. {
  543. struct ixgbe_fcoe_ddp_pool *ddp_pool;
  544. ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
  545. if (ddp_pool->pool)
  546. dma_pool_destroy(ddp_pool->pool);
  547. ddp_pool->pool = NULL;
  548. }
  549. static int ixgbe_fcoe_dma_pool_alloc(struct ixgbe_fcoe *fcoe,
  550. struct device *dev,
  551. unsigned int cpu)
  552. {
  553. struct ixgbe_fcoe_ddp_pool *ddp_pool;
  554. struct dma_pool *pool;
  555. char pool_name[32];
  556. snprintf(pool_name, 32, "ixgbe_fcoe_ddp_%u", cpu);
  557. pool = dma_pool_create(pool_name, dev, IXGBE_FCPTR_MAX,
  558. IXGBE_FCPTR_ALIGN, PAGE_SIZE);
  559. if (!pool)
  560. return -ENOMEM;
  561. ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
  562. ddp_pool->pool = pool;
  563. ddp_pool->noddp = 0;
  564. ddp_pool->noddp_ext_buff = 0;
  565. return 0;
  566. }
  567. /**
  568. * ixgbe_configure_fcoe - configures registers for fcoe at start
  569. * @adapter: ptr to ixgbe adapter
  570. *
  571. * This sets up FCoE related registers
  572. *
  573. * Returns : none
  574. */
  575. void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter)
  576. {
  577. struct ixgbe_ring_feature *fcoe = &adapter->ring_feature[RING_F_FCOE];
  578. struct ixgbe_hw *hw = &adapter->hw;
  579. int i, fcoe_q, fcoe_i, fcoe_q_h = 0;
  580. int fcreta_size;
  581. u32 etqf;
  582. /* Minimal functionality for FCoE requires at least CRC offloads */
  583. if (!(adapter->netdev->features & NETIF_F_FCOE_CRC))
  584. return;
  585. /* Enable L2 EtherType filter for FCoE, needed for FCoE CRC and DDP */
  586. etqf = ETH_P_FCOE | IXGBE_ETQF_FCOE | IXGBE_ETQF_FILTER_EN;
  587. if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
  588. etqf |= IXGBE_ETQF_POOL_ENABLE;
  589. etqf |= VMDQ_P(0) << IXGBE_ETQF_POOL_SHIFT;
  590. }
  591. IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FCOE), etqf);
  592. IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FCOE), 0);
  593. /* leave registers un-configured if FCoE is disabled */
  594. if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
  595. return;
  596. /* Use one or more Rx queues for FCoE by redirection table */
  597. fcreta_size = IXGBE_FCRETA_SIZE;
  598. if (adapter->hw.mac.type == ixgbe_mac_X550)
  599. fcreta_size = IXGBE_FCRETA_SIZE_X550;
  600. for (i = 0; i < fcreta_size; i++) {
  601. if (adapter->hw.mac.type == ixgbe_mac_X550) {
  602. int fcoe_i_h = fcoe->offset + ((i + fcreta_size) %
  603. fcoe->indices);
  604. fcoe_q_h = adapter->rx_ring[fcoe_i_h]->reg_idx;
  605. fcoe_q_h = (fcoe_q_h << IXGBE_FCRETA_ENTRY_HIGH_SHIFT) &
  606. IXGBE_FCRETA_ENTRY_HIGH_MASK;
  607. }
  608. fcoe_i = fcoe->offset + (i % fcoe->indices);
  609. fcoe_i &= IXGBE_FCRETA_ENTRY_MASK;
  610. fcoe_q = adapter->rx_ring[fcoe_i]->reg_idx;
  611. fcoe_q |= fcoe_q_h;
  612. IXGBE_WRITE_REG(hw, IXGBE_FCRETA(i), fcoe_q);
  613. }
  614. IXGBE_WRITE_REG(hw, IXGBE_FCRECTL, IXGBE_FCRECTL_ENA);
  615. /* Enable L2 EtherType filter for FIP */
  616. etqf = ETH_P_FIP | IXGBE_ETQF_FILTER_EN;
  617. if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
  618. etqf |= IXGBE_ETQF_POOL_ENABLE;
  619. etqf |= VMDQ_P(0) << IXGBE_ETQF_POOL_SHIFT;
  620. }
  621. IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FIP), etqf);
  622. /* Send FIP frames to the first FCoE queue */
  623. fcoe_q = adapter->rx_ring[fcoe->offset]->reg_idx;
  624. IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FIP),
  625. IXGBE_ETQS_QUEUE_EN |
  626. (fcoe_q << IXGBE_ETQS_RX_QUEUE_SHIFT));
  627. /* Configure FCoE Rx control */
  628. IXGBE_WRITE_REG(hw, IXGBE_FCRXCTRL,
  629. IXGBE_FCRXCTRL_FCCRCBO |
  630. (FC_FCOE_VER << IXGBE_FCRXCTRL_FCOEVER_SHIFT));
  631. }
  632. /**
  633. * ixgbe_free_fcoe_ddp_resources - release all fcoe ddp context resources
  634. * @adapter : ixgbe adapter
  635. *
  636. * Cleans up outstanding ddp context resources
  637. *
  638. * Returns : none
  639. */
  640. void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter)
  641. {
  642. struct ixgbe_fcoe *fcoe = &adapter->fcoe;
  643. int cpu, i, ddp_max;
  644. /* do nothing if no DDP pools were allocated */
  645. if (!fcoe->ddp_pool)
  646. return;
  647. ddp_max = IXGBE_FCOE_DDP_MAX;
  648. /* X550 has different DDP Max limit */
  649. if (adapter->hw.mac.type == ixgbe_mac_X550)
  650. ddp_max = IXGBE_FCOE_DDP_MAX_X550;
  651. for (i = 0; i < ddp_max; i++)
  652. ixgbe_fcoe_ddp_put(adapter->netdev, i);
  653. for_each_possible_cpu(cpu)
  654. ixgbe_fcoe_dma_pool_free(fcoe, cpu);
  655. dma_unmap_single(&adapter->pdev->dev,
  656. fcoe->extra_ddp_buffer_dma,
  657. IXGBE_FCBUFF_MIN,
  658. DMA_FROM_DEVICE);
  659. kfree(fcoe->extra_ddp_buffer);
  660. fcoe->extra_ddp_buffer = NULL;
  661. fcoe->extra_ddp_buffer_dma = 0;
  662. }
  663. /**
  664. * ixgbe_setup_fcoe_ddp_resources - setup all fcoe ddp context resources
  665. * @adapter: ixgbe adapter
  666. *
  667. * Sets up ddp context resouces
  668. *
  669. * Returns : 0 indicates success or -EINVAL on failure
  670. */
  671. int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter)
  672. {
  673. struct ixgbe_fcoe *fcoe = &adapter->fcoe;
  674. struct device *dev = &adapter->pdev->dev;
  675. void *buffer;
  676. dma_addr_t dma;
  677. unsigned int cpu;
  678. /* do nothing if no DDP pools were allocated */
  679. if (!fcoe->ddp_pool)
  680. return 0;
  681. /* Extra buffer to be shared by all DDPs for HW work around */
  682. buffer = kmalloc(IXGBE_FCBUFF_MIN, GFP_ATOMIC);
  683. if (!buffer)
  684. return -ENOMEM;
  685. dma = dma_map_single(dev, buffer, IXGBE_FCBUFF_MIN, DMA_FROM_DEVICE);
  686. if (dma_mapping_error(dev, dma)) {
  687. e_err(drv, "failed to map extra DDP buffer\n");
  688. kfree(buffer);
  689. return -ENOMEM;
  690. }
  691. fcoe->extra_ddp_buffer = buffer;
  692. fcoe->extra_ddp_buffer_dma = dma;
  693. /* allocate pci pool for each cpu */
  694. for_each_possible_cpu(cpu) {
  695. int err = ixgbe_fcoe_dma_pool_alloc(fcoe, dev, cpu);
  696. if (!err)
  697. continue;
  698. e_err(drv, "failed to alloc DDP pool on cpu:%d\n", cpu);
  699. ixgbe_free_fcoe_ddp_resources(adapter);
  700. return -ENOMEM;
  701. }
  702. return 0;
  703. }
  704. static int ixgbe_fcoe_ddp_enable(struct ixgbe_adapter *adapter)
  705. {
  706. struct ixgbe_fcoe *fcoe = &adapter->fcoe;
  707. if (!(adapter->flags & IXGBE_FLAG_FCOE_CAPABLE))
  708. return -EINVAL;
  709. fcoe->ddp_pool = alloc_percpu(struct ixgbe_fcoe_ddp_pool);
  710. if (!fcoe->ddp_pool) {
  711. e_err(drv, "failed to allocate percpu DDP resources\n");
  712. return -ENOMEM;
  713. }
  714. adapter->netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1;
  715. /* X550 has different DDP Max limit */
  716. if (adapter->hw.mac.type == ixgbe_mac_X550)
  717. adapter->netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX_X550 - 1;
  718. return 0;
  719. }
  720. static void ixgbe_fcoe_ddp_disable(struct ixgbe_adapter *adapter)
  721. {
  722. struct ixgbe_fcoe *fcoe = &adapter->fcoe;
  723. adapter->netdev->fcoe_ddp_xid = 0;
  724. if (!fcoe->ddp_pool)
  725. return;
  726. free_percpu(fcoe->ddp_pool);
  727. fcoe->ddp_pool = NULL;
  728. }
  729. /**
  730. * ixgbe_fcoe_enable - turn on FCoE offload feature
  731. * @netdev: the corresponding netdev
  732. *
  733. * Turns on FCoE offload feature in 82599.
  734. *
  735. * Returns : 0 indicates success or -EINVAL on failure
  736. */
  737. int ixgbe_fcoe_enable(struct net_device *netdev)
  738. {
  739. struct ixgbe_adapter *adapter = netdev_priv(netdev);
  740. struct ixgbe_fcoe *fcoe = &adapter->fcoe;
  741. atomic_inc(&fcoe->refcnt);
  742. if (!(adapter->flags & IXGBE_FLAG_FCOE_CAPABLE))
  743. return -EINVAL;
  744. if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
  745. return -EINVAL;
  746. e_info(drv, "Enabling FCoE offload features.\n");
  747. if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
  748. e_warn(probe, "Enabling FCoE on PF will disable legacy VFs\n");
  749. if (netif_running(netdev))
  750. netdev->netdev_ops->ndo_stop(netdev);
  751. /* Allocate per CPU memory to track DDP pools */
  752. ixgbe_fcoe_ddp_enable(adapter);
  753. /* enable FCoE and notify stack */
  754. adapter->flags |= IXGBE_FLAG_FCOE_ENABLED;
  755. netdev->features |= NETIF_F_FCOE_MTU;
  756. netdev_features_change(netdev);
  757. /* release existing queues and reallocate them */
  758. ixgbe_clear_interrupt_scheme(adapter);
  759. ixgbe_init_interrupt_scheme(adapter);
  760. if (netif_running(netdev))
  761. netdev->netdev_ops->ndo_open(netdev);
  762. return 0;
  763. }
  764. /**
  765. * ixgbe_fcoe_disable - turn off FCoE offload feature
  766. * @netdev: the corresponding netdev
  767. *
  768. * Turns off FCoE offload feature in 82599.
  769. *
  770. * Returns : 0 indicates success or -EINVAL on failure
  771. */
  772. int ixgbe_fcoe_disable(struct net_device *netdev)
  773. {
  774. struct ixgbe_adapter *adapter = netdev_priv(netdev);
  775. if (!atomic_dec_and_test(&adapter->fcoe.refcnt))
  776. return -EINVAL;
  777. if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
  778. return -EINVAL;
  779. e_info(drv, "Disabling FCoE offload features.\n");
  780. if (netif_running(netdev))
  781. netdev->netdev_ops->ndo_stop(netdev);
  782. /* Free per CPU memory to track DDP pools */
  783. ixgbe_fcoe_ddp_disable(adapter);
  784. /* disable FCoE and notify stack */
  785. adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
  786. netdev->features &= ~NETIF_F_FCOE_MTU;
  787. netdev_features_change(netdev);
  788. /* release existing queues and reallocate them */
  789. ixgbe_clear_interrupt_scheme(adapter);
  790. ixgbe_init_interrupt_scheme(adapter);
  791. if (netif_running(netdev))
  792. netdev->netdev_ops->ndo_open(netdev);
  793. return 0;
  794. }
  795. /**
  796. * ixgbe_fcoe_get_wwn - get world wide name for the node or the port
  797. * @netdev : ixgbe adapter
  798. * @wwn : the world wide name
  799. * @type: the type of world wide name
  800. *
  801. * Returns the node or port world wide name if both the prefix and the san
  802. * mac address are valid, then the wwn is formed based on the NAA-2 for
  803. * IEEE Extended name identifier (ref. to T10 FC-LS Spec., Sec. 15.3).
  804. *
  805. * Returns : 0 on success
  806. */
  807. int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type)
  808. {
  809. u16 prefix = 0xffff;
  810. struct ixgbe_adapter *adapter = netdev_priv(netdev);
  811. struct ixgbe_mac_info *mac = &adapter->hw.mac;
  812. switch (type) {
  813. case NETDEV_FCOE_WWNN:
  814. prefix = mac->wwnn_prefix;
  815. break;
  816. case NETDEV_FCOE_WWPN:
  817. prefix = mac->wwpn_prefix;
  818. break;
  819. default:
  820. break;
  821. }
  822. if ((prefix != 0xffff) &&
  823. is_valid_ether_addr(mac->san_addr)) {
  824. *wwn = ((u64) prefix << 48) |
  825. ((u64) mac->san_addr[0] << 40) |
  826. ((u64) mac->san_addr[1] << 32) |
  827. ((u64) mac->san_addr[2] << 24) |
  828. ((u64) mac->san_addr[3] << 16) |
  829. ((u64) mac->san_addr[4] << 8) |
  830. ((u64) mac->san_addr[5]);
  831. return 0;
  832. }
  833. return -EINVAL;
  834. }
  835. /**
  836. * ixgbe_fcoe_get_hbainfo - get FCoE HBA information
  837. * @netdev : ixgbe adapter
  838. * @info : HBA information
  839. *
  840. * Returns ixgbe HBA information
  841. *
  842. * Returns : 0 on success
  843. */
  844. int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
  845. struct netdev_fcoe_hbainfo *info)
  846. {
  847. struct ixgbe_adapter *adapter = netdev_priv(netdev);
  848. struct ixgbe_hw *hw = &adapter->hw;
  849. int i, pos;
  850. u8 buf[8];
  851. if (!info)
  852. return -EINVAL;
  853. /* Don't return information on unsupported devices */
  854. if (hw->mac.type != ixgbe_mac_82599EB &&
  855. hw->mac.type != ixgbe_mac_X540)
  856. return -EINVAL;
  857. /* Manufacturer */
  858. snprintf(info->manufacturer, sizeof(info->manufacturer),
  859. "Intel Corporation");
  860. /* Serial Number */
  861. /* Get the PCI-e Device Serial Number Capability */
  862. pos = pci_find_ext_capability(adapter->pdev, PCI_EXT_CAP_ID_DSN);
  863. if (pos) {
  864. pos += 4;
  865. for (i = 0; i < 8; i++)
  866. pci_read_config_byte(adapter->pdev, pos + i, &buf[i]);
  867. snprintf(info->serial_number, sizeof(info->serial_number),
  868. "%02X%02X%02X%02X%02X%02X%02X%02X",
  869. buf[7], buf[6], buf[5], buf[4],
  870. buf[3], buf[2], buf[1], buf[0]);
  871. } else
  872. snprintf(info->serial_number, sizeof(info->serial_number),
  873. "Unknown");
  874. /* Hardware Version */
  875. snprintf(info->hardware_version,
  876. sizeof(info->hardware_version),
  877. "Rev %d", hw->revision_id);
  878. /* Driver Name/Version */
  879. snprintf(info->driver_version,
  880. sizeof(info->driver_version),
  881. "%s v%s",
  882. ixgbe_driver_name,
  883. ixgbe_driver_version);
  884. /* Firmware Version */
  885. snprintf(info->firmware_version,
  886. sizeof(info->firmware_version),
  887. "0x%08x",
  888. (adapter->eeprom_verh << 16) |
  889. adapter->eeprom_verl);
  890. /* Model */
  891. if (hw->mac.type == ixgbe_mac_82599EB) {
  892. snprintf(info->model,
  893. sizeof(info->model),
  894. "Intel 82599");
  895. } else {
  896. snprintf(info->model,
  897. sizeof(info->model),
  898. "Intel X540");
  899. }
  900. /* Model Description */
  901. snprintf(info->model_description,
  902. sizeof(info->model_description),
  903. "%s",
  904. ixgbe_default_device_descr);
  905. return 0;
  906. }
  907. /**
  908. * ixgbe_fcoe_get_tc - get the current TC that fcoe is mapped to
  909. * @adapter - pointer to the device adapter structure
  910. *
  911. * Return : TC that FCoE is mapped to
  912. */
  913. u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter)
  914. {
  915. #ifdef CONFIG_IXGBE_DCB
  916. return netdev_get_prio_tc_map(adapter->netdev, adapter->fcoe.up);
  917. #else
  918. return 0;
  919. #endif
  920. }