ixgbe_x550.c 68 KB

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  1. /*******************************************************************************
  2. *
  3. * Intel 10 Gigabit PCI Express Linux driver
  4. * Copyright(c) 1999 - 2015 Intel Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * The full GNU General Public License is included in this distribution in
  16. * the file called "COPYING".
  17. *
  18. * Contact Information:
  19. * Linux NICS <linux.nics@intel.com>
  20. * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  21. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  22. *
  23. ******************************************************************************/
  24. #include "ixgbe_x540.h"
  25. #include "ixgbe_type.h"
  26. #include "ixgbe_common.h"
  27. #include "ixgbe_phy.h"
  28. static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw)
  29. {
  30. struct ixgbe_mac_info *mac = &hw->mac;
  31. struct ixgbe_phy_info *phy = &hw->phy;
  32. /* Start with X540 invariants, since so simular */
  33. ixgbe_get_invariants_X540(hw);
  34. if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
  35. phy->ops.set_phy_power = NULL;
  36. return 0;
  37. }
  38. /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
  39. * @hw: pointer to hardware structure
  40. **/
  41. static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
  42. {
  43. u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
  44. if (hw->bus.lan_id) {
  45. esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
  46. esdp |= IXGBE_ESDP_SDP1_DIR;
  47. }
  48. esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
  49. IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
  50. IXGBE_WRITE_FLUSH(hw);
  51. }
  52. /**
  53. * ixgbe_read_cs4227 - Read CS4227 register
  54. * @hw: pointer to hardware structure
  55. * @reg: register number to write
  56. * @value: pointer to receive value read
  57. *
  58. * Returns status code
  59. */
  60. static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  61. {
  62. return hw->phy.ops.read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg,
  63. value);
  64. }
  65. /**
  66. * ixgbe_write_cs4227 - Write CS4227 register
  67. * @hw: pointer to hardware structure
  68. * @reg: register number to write
  69. * @value: value to write to register
  70. *
  71. * Returns status code
  72. */
  73. static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
  74. {
  75. return hw->phy.ops.write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg,
  76. value);
  77. }
  78. /**
  79. * ixgbe_check_cs4227_reg - Perform diag on a CS4227 register
  80. * @hw: pointer to hardware structure
  81. * @reg: the register to check
  82. *
  83. * Performs a diagnostic on a register in the CS4227 chip. Returns an error
  84. * if it is not operating correctly.
  85. * This function assumes that the caller has acquired the proper semaphore.
  86. */
  87. static s32 ixgbe_check_cs4227_reg(struct ixgbe_hw *hw, u16 reg)
  88. {
  89. s32 status;
  90. u32 retry;
  91. u16 reg_val;
  92. reg_val = (IXGBE_CS4227_EDC_MODE_DIAG << 1) | 1;
  93. status = ixgbe_write_cs4227(hw, reg, reg_val);
  94. if (status)
  95. return status;
  96. for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
  97. msleep(IXGBE_CS4227_CHECK_DELAY);
  98. reg_val = 0xFFFF;
  99. ixgbe_read_cs4227(hw, reg, &reg_val);
  100. if (!reg_val)
  101. break;
  102. }
  103. if (reg_val) {
  104. hw_err(hw, "CS4227 reg 0x%04X failed diagnostic\n", reg);
  105. return status;
  106. }
  107. return 0;
  108. }
  109. /**
  110. * ixgbe_get_cs4227_status - Return CS4227 status
  111. * @hw: pointer to hardware structure
  112. *
  113. * Performs a diagnostic on the CS4227 chip. Returns an error if it is
  114. * not operating correctly.
  115. * This function assumes that the caller has acquired the proper semaphore.
  116. */
  117. static s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
  118. {
  119. s32 status;
  120. u16 value = 0;
  121. /* Exit if the diagnostic has already been performed. */
  122. status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
  123. if (status)
  124. return status;
  125. if (value == IXGBE_CS4227_RESET_COMPLETE)
  126. return 0;
  127. /* Check port 0. */
  128. status = ixgbe_check_cs4227_reg(hw, IXGBE_CS4227_LINE_SPARE24_LSB);
  129. if (status)
  130. return status;
  131. status = ixgbe_check_cs4227_reg(hw, IXGBE_CS4227_HOST_SPARE24_LSB);
  132. if (status)
  133. return status;
  134. /* Check port 1. */
  135. status = ixgbe_check_cs4227_reg(hw, IXGBE_CS4227_LINE_SPARE24_LSB +
  136. (1 << 12));
  137. if (status)
  138. return status;
  139. return ixgbe_check_cs4227_reg(hw, IXGBE_CS4227_HOST_SPARE24_LSB +
  140. (1 << 12));
  141. }
  142. /**
  143. * ixgbe_read_pe - Read register from port expander
  144. * @hw: pointer to hardware structure
  145. * @reg: register number to read
  146. * @value: pointer to receive read value
  147. *
  148. * Returns status code
  149. */
  150. static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
  151. {
  152. s32 status;
  153. status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value);
  154. if (status)
  155. hw_err(hw, "port expander access failed with %d\n", status);
  156. return status;
  157. }
  158. /**
  159. * ixgbe_write_pe - Write register to port expander
  160. * @hw: pointer to hardware structure
  161. * @reg: register number to write
  162. * @value: value to write
  163. *
  164. * Returns status code
  165. */
  166. static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
  167. {
  168. s32 status;
  169. status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE,
  170. value);
  171. if (status)
  172. hw_err(hw, "port expander access failed with %d\n", status);
  173. return status;
  174. }
  175. /**
  176. * ixgbe_reset_cs4227 - Reset CS4227 using port expander
  177. * @hw: pointer to hardware structure
  178. *
  179. * This function assumes that the caller has acquired the proper semaphore.
  180. * Returns error code
  181. */
  182. static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
  183. {
  184. s32 status;
  185. u32 retry;
  186. u16 value;
  187. u8 reg;
  188. /* Trigger hard reset. */
  189. status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
  190. if (status)
  191. return status;
  192. reg |= IXGBE_PE_BIT1;
  193. status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
  194. if (status)
  195. return status;
  196. status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
  197. if (status)
  198. return status;
  199. reg &= ~IXGBE_PE_BIT1;
  200. status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
  201. if (status)
  202. return status;
  203. status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
  204. if (status)
  205. return status;
  206. reg &= ~IXGBE_PE_BIT1;
  207. status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
  208. if (status)
  209. return status;
  210. usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100);
  211. status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
  212. if (status)
  213. return status;
  214. reg |= IXGBE_PE_BIT1;
  215. status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
  216. if (status)
  217. return status;
  218. /* Wait for the reset to complete. */
  219. msleep(IXGBE_CS4227_RESET_DELAY);
  220. for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
  221. status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
  222. &value);
  223. if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK)
  224. break;
  225. msleep(IXGBE_CS4227_CHECK_DELAY);
  226. }
  227. if (retry == IXGBE_CS4227_RETRIES) {
  228. hw_err(hw, "CS4227 reset did not complete\n");
  229. return IXGBE_ERR_PHY;
  230. }
  231. status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
  232. if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
  233. hw_err(hw, "CS4227 EEPROM did not load successfully\n");
  234. return IXGBE_ERR_PHY;
  235. }
  236. return 0;
  237. }
  238. /**
  239. * ixgbe_check_cs4227 - Check CS4227 and reset as needed
  240. * @hw: pointer to hardware structure
  241. */
  242. static void ixgbe_check_cs4227(struct ixgbe_hw *hw)
  243. {
  244. u32 swfw_mask = hw->phy.phy_semaphore_mask;
  245. s32 status;
  246. u16 value;
  247. u8 retry;
  248. for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
  249. status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
  250. if (status) {
  251. hw_err(hw, "semaphore failed with %d\n", status);
  252. msleep(IXGBE_CS4227_CHECK_DELAY);
  253. continue;
  254. }
  255. /* Get status of reset flow. */
  256. status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
  257. if (!status && value == IXGBE_CS4227_RESET_COMPLETE)
  258. goto out;
  259. if (status || value != IXGBE_CS4227_RESET_PENDING)
  260. break;
  261. /* Reset is pending. Wait and check again. */
  262. hw->mac.ops.release_swfw_sync(hw, swfw_mask);
  263. msleep(IXGBE_CS4227_CHECK_DELAY);
  264. }
  265. /* If still pending, assume other instance failed. */
  266. if (retry == IXGBE_CS4227_RETRIES) {
  267. status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
  268. if (status) {
  269. hw_err(hw, "semaphore failed with %d\n", status);
  270. return;
  271. }
  272. }
  273. /* Reset the CS4227. */
  274. status = ixgbe_reset_cs4227(hw);
  275. if (status) {
  276. hw_err(hw, "CS4227 reset failed: %d", status);
  277. goto out;
  278. }
  279. /* Reset takes so long, temporarily release semaphore in case the
  280. * other driver instance is waiting for the reset indication.
  281. */
  282. ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
  283. IXGBE_CS4227_RESET_PENDING);
  284. hw->mac.ops.release_swfw_sync(hw, swfw_mask);
  285. usleep_range(10000, 12000);
  286. status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
  287. if (status) {
  288. hw_err(hw, "semaphore failed with %d", status);
  289. return;
  290. }
  291. /* Is the CS4227 working correctly? */
  292. status = ixgbe_get_cs4227_status(hw);
  293. if (status) {
  294. hw_err(hw, "CS4227 status failed: %d", status);
  295. goto out;
  296. }
  297. /* Record completion for next time. */
  298. status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
  299. IXGBE_CS4227_RESET_COMPLETE);
  300. out:
  301. hw->mac.ops.release_swfw_sync(hw, swfw_mask);
  302. msleep(hw->eeprom.semaphore_delay);
  303. }
  304. /** ixgbe_identify_phy_x550em - Get PHY type based on device id
  305. * @hw: pointer to hardware structure
  306. *
  307. * Returns error code
  308. */
  309. static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
  310. {
  311. switch (hw->device_id) {
  312. case IXGBE_DEV_ID_X550EM_X_SFP:
  313. /* set up for CS4227 usage */
  314. hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
  315. ixgbe_setup_mux_ctl(hw);
  316. ixgbe_check_cs4227(hw);
  317. return ixgbe_identify_module_generic(hw);
  318. case IXGBE_DEV_ID_X550EM_X_KX4:
  319. hw->phy.type = ixgbe_phy_x550em_kx4;
  320. break;
  321. case IXGBE_DEV_ID_X550EM_X_KR:
  322. hw->phy.type = ixgbe_phy_x550em_kr;
  323. break;
  324. case IXGBE_DEV_ID_X550EM_X_1G_T:
  325. case IXGBE_DEV_ID_X550EM_X_10G_T:
  326. return ixgbe_identify_phy_generic(hw);
  327. default:
  328. break;
  329. }
  330. return 0;
  331. }
  332. static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
  333. u32 device_type, u16 *phy_data)
  334. {
  335. return IXGBE_NOT_IMPLEMENTED;
  336. }
  337. static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
  338. u32 device_type, u16 phy_data)
  339. {
  340. return IXGBE_NOT_IMPLEMENTED;
  341. }
  342. /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
  343. * @hw: pointer to hardware structure
  344. *
  345. * Initializes the EEPROM parameters ixgbe_eeprom_info within the
  346. * ixgbe_hw struct in order to set up EEPROM access.
  347. **/
  348. static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
  349. {
  350. struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  351. u32 eec;
  352. u16 eeprom_size;
  353. if (eeprom->type == ixgbe_eeprom_uninitialized) {
  354. eeprom->semaphore_delay = 10;
  355. eeprom->type = ixgbe_flash;
  356. eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
  357. eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
  358. IXGBE_EEC_SIZE_SHIFT);
  359. eeprom->word_size = 1 << (eeprom_size +
  360. IXGBE_EEPROM_WORD_SIZE_SHIFT);
  361. hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
  362. eeprom->type, eeprom->word_size);
  363. }
  364. return 0;
  365. }
  366. /**
  367. * ixgbe_iosf_wait - Wait for IOSF command completion
  368. * @hw: pointer to hardware structure
  369. * @ctrl: pointer to location to receive final IOSF control value
  370. *
  371. * Return: failing status on timeout
  372. *
  373. * Note: ctrl can be NULL if the IOSF control register value is not needed
  374. */
  375. static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
  376. {
  377. u32 i, command;
  378. /* Check every 10 usec to see if the address cycle completed.
  379. * The SB IOSF BUSY bit will clear when the operation is
  380. * complete.
  381. */
  382. for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
  383. command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
  384. if (!(command & IXGBE_SB_IOSF_CTRL_BUSY))
  385. break;
  386. usleep_range(10, 20);
  387. }
  388. if (ctrl)
  389. *ctrl = command;
  390. if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
  391. hw_dbg(hw, "IOSF wait timed out\n");
  392. return IXGBE_ERR_PHY;
  393. }
  394. return 0;
  395. }
  396. /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the
  397. * IOSF device
  398. * @hw: pointer to hardware structure
  399. * @reg_addr: 32 bit PHY register to write
  400. * @device_type: 3 bit device type
  401. * @phy_data: Pointer to read data from the register
  402. **/
  403. static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
  404. u32 device_type, u32 *data)
  405. {
  406. u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
  407. u32 command, error;
  408. s32 ret;
  409. ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
  410. if (ret)
  411. return ret;
  412. ret = ixgbe_iosf_wait(hw, NULL);
  413. if (ret)
  414. goto out;
  415. command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
  416. (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
  417. /* Write IOSF control register */
  418. IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
  419. ret = ixgbe_iosf_wait(hw, &command);
  420. if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
  421. error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
  422. IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
  423. hw_dbg(hw, "Failed to read, error %x\n", error);
  424. return IXGBE_ERR_PHY;
  425. }
  426. if (!ret)
  427. *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
  428. out:
  429. hw->mac.ops.release_swfw_sync(hw, gssr);
  430. return ret;
  431. }
  432. /** ixgbe_read_ee_hostif_data_X550 - Read EEPROM word using a host interface
  433. * command assuming that the semaphore is already obtained.
  434. * @hw: pointer to hardware structure
  435. * @offset: offset of word in the EEPROM to read
  436. * @data: word read from the EEPROM
  437. *
  438. * Reads a 16 bit word from the EEPROM using the hostif.
  439. **/
  440. static s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
  441. u16 *data)
  442. {
  443. s32 status;
  444. struct ixgbe_hic_read_shadow_ram buffer;
  445. buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
  446. buffer.hdr.req.buf_lenh = 0;
  447. buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
  448. buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
  449. /* convert offset from words to bytes */
  450. buffer.address = cpu_to_be32(offset * 2);
  451. /* one word */
  452. buffer.length = cpu_to_be16(sizeof(u16));
  453. status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
  454. sizeof(buffer),
  455. IXGBE_HI_COMMAND_TIMEOUT, false);
  456. if (status)
  457. return status;
  458. *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
  459. FW_NVM_DATA_OFFSET);
  460. return 0;
  461. }
  462. /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
  463. * @hw: pointer to hardware structure
  464. * @offset: offset of word in the EEPROM to read
  465. * @words: number of words
  466. * @data: word(s) read from the EEPROM
  467. *
  468. * Reads a 16 bit word(s) from the EEPROM using the hostif.
  469. **/
  470. static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
  471. u16 offset, u16 words, u16 *data)
  472. {
  473. struct ixgbe_hic_read_shadow_ram buffer;
  474. u32 current_word = 0;
  475. u16 words_to_read;
  476. s32 status;
  477. u32 i;
  478. /* Take semaphore for the entire operation. */
  479. status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
  480. if (status) {
  481. hw_dbg(hw, "EEPROM read buffer - semaphore failed\n");
  482. return status;
  483. }
  484. while (words) {
  485. if (words > FW_MAX_READ_BUFFER_SIZE / 2)
  486. words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
  487. else
  488. words_to_read = words;
  489. buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
  490. buffer.hdr.req.buf_lenh = 0;
  491. buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
  492. buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
  493. /* convert offset from words to bytes */
  494. buffer.address = cpu_to_be32((offset + current_word) * 2);
  495. buffer.length = cpu_to_be16(words_to_read * 2);
  496. buffer.pad2 = 0;
  497. buffer.pad3 = 0;
  498. status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
  499. sizeof(buffer),
  500. IXGBE_HI_COMMAND_TIMEOUT,
  501. false);
  502. if (status) {
  503. hw_dbg(hw, "Host interface command failed\n");
  504. goto out;
  505. }
  506. for (i = 0; i < words_to_read; i++) {
  507. u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
  508. 2 * i;
  509. u32 value = IXGBE_READ_REG(hw, reg);
  510. data[current_word] = (u16)(value & 0xffff);
  511. current_word++;
  512. i++;
  513. if (i < words_to_read) {
  514. value >>= 16;
  515. data[current_word] = (u16)(value & 0xffff);
  516. current_word++;
  517. }
  518. }
  519. words -= words_to_read;
  520. }
  521. out:
  522. hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
  523. return status;
  524. }
  525. /** ixgbe_checksum_ptr_x550 - Checksum one pointer region
  526. * @hw: pointer to hardware structure
  527. * @ptr: pointer offset in eeprom
  528. * @size: size of section pointed by ptr, if 0 first word will be used as size
  529. * @csum: address of checksum to update
  530. *
  531. * Returns error status for any failure
  532. **/
  533. static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
  534. u16 size, u16 *csum, u16 *buffer,
  535. u32 buffer_size)
  536. {
  537. u16 buf[256];
  538. s32 status;
  539. u16 length, bufsz, i, start;
  540. u16 *local_buffer;
  541. bufsz = sizeof(buf) / sizeof(buf[0]);
  542. /* Read a chunk at the pointer location */
  543. if (!buffer) {
  544. status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
  545. if (status) {
  546. hw_dbg(hw, "Failed to read EEPROM image\n");
  547. return status;
  548. }
  549. local_buffer = buf;
  550. } else {
  551. if (buffer_size < ptr)
  552. return IXGBE_ERR_PARAM;
  553. local_buffer = &buffer[ptr];
  554. }
  555. if (size) {
  556. start = 0;
  557. length = size;
  558. } else {
  559. start = 1;
  560. length = local_buffer[0];
  561. /* Skip pointer section if length is invalid. */
  562. if (length == 0xFFFF || length == 0 ||
  563. (ptr + length) >= hw->eeprom.word_size)
  564. return 0;
  565. }
  566. if (buffer && ((u32)start + (u32)length > buffer_size))
  567. return IXGBE_ERR_PARAM;
  568. for (i = start; length; i++, length--) {
  569. if (i == bufsz && !buffer) {
  570. ptr += bufsz;
  571. i = 0;
  572. if (length < bufsz)
  573. bufsz = length;
  574. /* Read a chunk at the pointer location */
  575. status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
  576. bufsz, buf);
  577. if (status) {
  578. hw_dbg(hw, "Failed to read EEPROM image\n");
  579. return status;
  580. }
  581. }
  582. *csum += local_buffer[i];
  583. }
  584. return 0;
  585. }
  586. /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum
  587. * @hw: pointer to hardware structure
  588. * @buffer: pointer to buffer containing calculated checksum
  589. * @buffer_size: size of buffer
  590. *
  591. * Returns a negative error code on error, or the 16-bit checksum
  592. **/
  593. static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer,
  594. u32 buffer_size)
  595. {
  596. u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
  597. u16 *local_buffer;
  598. s32 status;
  599. u16 checksum = 0;
  600. u16 pointer, i, size;
  601. hw->eeprom.ops.init_params(hw);
  602. if (!buffer) {
  603. /* Read pointer area */
  604. status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
  605. IXGBE_EEPROM_LAST_WORD + 1,
  606. eeprom_ptrs);
  607. if (status) {
  608. hw_dbg(hw, "Failed to read EEPROM image\n");
  609. return status;
  610. }
  611. local_buffer = eeprom_ptrs;
  612. } else {
  613. if (buffer_size < IXGBE_EEPROM_LAST_WORD)
  614. return IXGBE_ERR_PARAM;
  615. local_buffer = buffer;
  616. }
  617. /* For X550 hardware include 0x0-0x41 in the checksum, skip the
  618. * checksum word itself
  619. */
  620. for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
  621. if (i != IXGBE_EEPROM_CHECKSUM)
  622. checksum += local_buffer[i];
  623. /* Include all data from pointers 0x3, 0x6-0xE. This excludes the
  624. * FW, PHY module, and PCIe Expansion/Option ROM pointers.
  625. */
  626. for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
  627. if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
  628. continue;
  629. pointer = local_buffer[i];
  630. /* Skip pointer section if the pointer is invalid. */
  631. if (pointer == 0xFFFF || pointer == 0 ||
  632. pointer >= hw->eeprom.word_size)
  633. continue;
  634. switch (i) {
  635. case IXGBE_PCIE_GENERAL_PTR:
  636. size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
  637. break;
  638. case IXGBE_PCIE_CONFIG0_PTR:
  639. case IXGBE_PCIE_CONFIG1_PTR:
  640. size = IXGBE_PCIE_CONFIG_SIZE;
  641. break;
  642. default:
  643. size = 0;
  644. break;
  645. }
  646. status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
  647. buffer, buffer_size);
  648. if (status)
  649. return status;
  650. }
  651. checksum = (u16)IXGBE_EEPROM_SUM - checksum;
  652. return (s32)checksum;
  653. }
  654. /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
  655. * @hw: pointer to hardware structure
  656. *
  657. * Returns a negative error code on error, or the 16-bit checksum
  658. **/
  659. static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
  660. {
  661. return ixgbe_calc_checksum_X550(hw, NULL, 0);
  662. }
  663. /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
  664. * @hw: pointer to hardware structure
  665. * @offset: offset of word in the EEPROM to read
  666. * @data: word read from the EEPROM
  667. *
  668. * Reads a 16 bit word from the EEPROM using the hostif.
  669. **/
  670. static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
  671. {
  672. s32 status = 0;
  673. if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
  674. status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
  675. hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
  676. } else {
  677. status = IXGBE_ERR_SWFW_SYNC;
  678. }
  679. return status;
  680. }
  681. /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
  682. * @hw: pointer to hardware structure
  683. * @checksum_val: calculated checksum
  684. *
  685. * Performs checksum calculation and validates the EEPROM checksum. If the
  686. * caller does not need checksum_val, the value can be NULL.
  687. **/
  688. static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,
  689. u16 *checksum_val)
  690. {
  691. s32 status;
  692. u16 checksum;
  693. u16 read_checksum = 0;
  694. /* Read the first word from the EEPROM. If this times out or fails, do
  695. * not continue or we could be in for a very long wait while every
  696. * EEPROM read fails
  697. */
  698. status = hw->eeprom.ops.read(hw, 0, &checksum);
  699. if (status) {
  700. hw_dbg(hw, "EEPROM read failed\n");
  701. return status;
  702. }
  703. status = hw->eeprom.ops.calc_checksum(hw);
  704. if (status < 0)
  705. return status;
  706. checksum = (u16)(status & 0xffff);
  707. status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
  708. &read_checksum);
  709. if (status)
  710. return status;
  711. /* Verify read checksum from EEPROM is the same as
  712. * calculated checksum
  713. */
  714. if (read_checksum != checksum) {
  715. status = IXGBE_ERR_EEPROM_CHECKSUM;
  716. hw_dbg(hw, "Invalid EEPROM checksum");
  717. }
  718. /* If the user cares, return the calculated checksum */
  719. if (checksum_val)
  720. *checksum_val = checksum;
  721. return status;
  722. }
  723. /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
  724. * @hw: pointer to hardware structure
  725. * @offset: offset of word in the EEPROM to write
  726. * @data: word write to the EEPROM
  727. *
  728. * Write a 16 bit word to the EEPROM using the hostif.
  729. **/
  730. static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
  731. u16 data)
  732. {
  733. s32 status;
  734. struct ixgbe_hic_write_shadow_ram buffer;
  735. buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
  736. buffer.hdr.req.buf_lenh = 0;
  737. buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
  738. buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
  739. /* one word */
  740. buffer.length = cpu_to_be16(sizeof(u16));
  741. buffer.data = data;
  742. buffer.address = cpu_to_be32(offset * 2);
  743. status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
  744. sizeof(buffer),
  745. IXGBE_HI_COMMAND_TIMEOUT, false);
  746. return status;
  747. }
  748. /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
  749. * @hw: pointer to hardware structure
  750. * @offset: offset of word in the EEPROM to write
  751. * @data: word write to the EEPROM
  752. *
  753. * Write a 16 bit word to the EEPROM using the hostif.
  754. **/
  755. static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data)
  756. {
  757. s32 status = 0;
  758. if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
  759. status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
  760. hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
  761. } else {
  762. hw_dbg(hw, "write ee hostif failed to get semaphore");
  763. status = IXGBE_ERR_SWFW_SYNC;
  764. }
  765. return status;
  766. }
  767. /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
  768. * @hw: pointer to hardware structure
  769. *
  770. * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
  771. **/
  772. static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
  773. {
  774. s32 status = 0;
  775. union ixgbe_hic_hdr2 buffer;
  776. buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
  777. buffer.req.buf_lenh = 0;
  778. buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
  779. buffer.req.checksum = FW_DEFAULT_CHECKSUM;
  780. status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
  781. sizeof(buffer),
  782. IXGBE_HI_COMMAND_TIMEOUT, false);
  783. return status;
  784. }
  785. /**
  786. * ixgbe_get_bus_info_X550em - Set PCI bus info
  787. * @hw: pointer to hardware structure
  788. *
  789. * Sets bus link width and speed to unknown because X550em is
  790. * not a PCI device.
  791. **/
  792. static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
  793. {
  794. hw->bus.type = ixgbe_bus_type_internal;
  795. hw->bus.width = ixgbe_bus_width_unknown;
  796. hw->bus.speed = ixgbe_bus_speed_unknown;
  797. hw->mac.ops.set_lan_id(hw);
  798. return 0;
  799. }
  800. /** ixgbe_disable_rx_x550 - Disable RX unit
  801. *
  802. * Enables the Rx DMA unit for x550
  803. **/
  804. static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
  805. {
  806. u32 rxctrl, pfdtxgswc;
  807. s32 status;
  808. struct ixgbe_hic_disable_rxen fw_cmd;
  809. rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
  810. if (rxctrl & IXGBE_RXCTRL_RXEN) {
  811. pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
  812. if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
  813. pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
  814. IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
  815. hw->mac.set_lben = true;
  816. } else {
  817. hw->mac.set_lben = false;
  818. }
  819. fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
  820. fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
  821. fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
  822. fw_cmd.port_number = (u8)hw->bus.lan_id;
  823. status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
  824. sizeof(struct ixgbe_hic_disable_rxen),
  825. IXGBE_HI_COMMAND_TIMEOUT, true);
  826. /* If we fail - disable RX using register write */
  827. if (status) {
  828. rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
  829. if (rxctrl & IXGBE_RXCTRL_RXEN) {
  830. rxctrl &= ~IXGBE_RXCTRL_RXEN;
  831. IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
  832. }
  833. }
  834. }
  835. }
  836. /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
  837. * @hw: pointer to hardware structure
  838. *
  839. * After writing EEPROM to shadow RAM using EEWR register, software calculates
  840. * checksum and updates the EEPROM and instructs the hardware to update
  841. * the flash.
  842. **/
  843. static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
  844. {
  845. s32 status;
  846. u16 checksum = 0;
  847. /* Read the first word from the EEPROM. If this times out or fails, do
  848. * not continue or we could be in for a very long wait while every
  849. * EEPROM read fails
  850. */
  851. status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
  852. if (status) {
  853. hw_dbg(hw, "EEPROM read failed\n");
  854. return status;
  855. }
  856. status = ixgbe_calc_eeprom_checksum_X550(hw);
  857. if (status < 0)
  858. return status;
  859. checksum = (u16)(status & 0xffff);
  860. status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
  861. checksum);
  862. if (status)
  863. return status;
  864. status = ixgbe_update_flash_X550(hw);
  865. return status;
  866. }
  867. /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
  868. * @hw: pointer to hardware structure
  869. * @offset: offset of word in the EEPROM to write
  870. * @words: number of words
  871. * @data: word(s) write to the EEPROM
  872. *
  873. *
  874. * Write a 16 bit word(s) to the EEPROM using the hostif.
  875. **/
  876. static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
  877. u16 offset, u16 words,
  878. u16 *data)
  879. {
  880. s32 status = 0;
  881. u32 i = 0;
  882. /* Take semaphore for the entire operation. */
  883. status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
  884. if (status) {
  885. hw_dbg(hw, "EEPROM write buffer - semaphore failed\n");
  886. return status;
  887. }
  888. for (i = 0; i < words; i++) {
  889. status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
  890. data[i]);
  891. if (status) {
  892. hw_dbg(hw, "Eeprom buffered write failed\n");
  893. break;
  894. }
  895. }
  896. hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
  897. return status;
  898. }
  899. /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the
  900. * IOSF device
  901. *
  902. * @hw: pointer to hardware structure
  903. * @reg_addr: 32 bit PHY register to write
  904. * @device_type: 3 bit device type
  905. * @data: Data to write to the register
  906. **/
  907. static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
  908. u32 device_type, u32 data)
  909. {
  910. u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
  911. u32 command, error;
  912. s32 ret;
  913. ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
  914. if (ret)
  915. return ret;
  916. ret = ixgbe_iosf_wait(hw, NULL);
  917. if (ret)
  918. goto out;
  919. command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
  920. (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
  921. /* Write IOSF control register */
  922. IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
  923. /* Write IOSF data register */
  924. IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
  925. ret = ixgbe_iosf_wait(hw, &command);
  926. if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
  927. error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
  928. IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
  929. hw_dbg(hw, "Failed to write, error %x\n", error);
  930. return IXGBE_ERR_PHY;
  931. }
  932. out:
  933. hw->mac.ops.release_swfw_sync(hw, gssr);
  934. return ret;
  935. }
  936. /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
  937. * @hw: pointer to hardware structure
  938. * @speed: the link speed to force
  939. *
  940. * Configures the integrated KR PHY to use iXFI mode. Used to connect an
  941. * internal and external PHY at a specific speed, without autonegotiation.
  942. **/
  943. static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
  944. {
  945. s32 status;
  946. u32 reg_val;
  947. /* Disable AN and force speed to 10G Serial. */
  948. status = ixgbe_read_iosf_sb_reg_x550(hw,
  949. IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
  950. IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
  951. if (status)
  952. return status;
  953. reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
  954. reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
  955. /* Select forced link speed for internal PHY. */
  956. switch (*speed) {
  957. case IXGBE_LINK_SPEED_10GB_FULL:
  958. reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
  959. break;
  960. case IXGBE_LINK_SPEED_1GB_FULL:
  961. reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
  962. break;
  963. default:
  964. /* Other link speeds are not supported by internal KR PHY. */
  965. return IXGBE_ERR_LINK_SETUP;
  966. }
  967. status = ixgbe_write_iosf_sb_reg_x550(hw,
  968. IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
  969. IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
  970. if (status)
  971. return status;
  972. /* Disable training protocol FSM. */
  973. status = ixgbe_read_iosf_sb_reg_x550(hw,
  974. IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
  975. IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
  976. if (status)
  977. return status;
  978. reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
  979. status = ixgbe_write_iosf_sb_reg_x550(hw,
  980. IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
  981. IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
  982. if (status)
  983. return status;
  984. /* Disable Flex from training TXFFE. */
  985. status = ixgbe_read_iosf_sb_reg_x550(hw,
  986. IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
  987. IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
  988. if (status)
  989. return status;
  990. reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
  991. reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
  992. reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
  993. status = ixgbe_write_iosf_sb_reg_x550(hw,
  994. IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
  995. IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
  996. if (status)
  997. return status;
  998. status = ixgbe_read_iosf_sb_reg_x550(hw,
  999. IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
  1000. IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
  1001. if (status)
  1002. return status;
  1003. reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
  1004. reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
  1005. reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
  1006. status = ixgbe_write_iosf_sb_reg_x550(hw,
  1007. IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
  1008. IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
  1009. if (status)
  1010. return status;
  1011. /* Enable override for coefficients. */
  1012. status = ixgbe_read_iosf_sb_reg_x550(hw,
  1013. IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
  1014. IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
  1015. if (status)
  1016. return status;
  1017. reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
  1018. reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
  1019. reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
  1020. reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
  1021. status = ixgbe_write_iosf_sb_reg_x550(hw,
  1022. IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
  1023. IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
  1024. if (status)
  1025. return status;
  1026. /* Toggle port SW reset by AN reset. */
  1027. status = ixgbe_read_iosf_sb_reg_x550(hw,
  1028. IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
  1029. IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
  1030. if (status)
  1031. return status;
  1032. reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
  1033. status = ixgbe_write_iosf_sb_reg_x550(hw,
  1034. IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
  1035. IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
  1036. return status;
  1037. }
  1038. /**
  1039. * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
  1040. * @hw: pointer to hardware structure
  1041. * @linear: true if SFP module is linear
  1042. */
  1043. static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
  1044. {
  1045. switch (hw->phy.sfp_type) {
  1046. case ixgbe_sfp_type_not_present:
  1047. return IXGBE_ERR_SFP_NOT_PRESENT;
  1048. case ixgbe_sfp_type_da_cu_core0:
  1049. case ixgbe_sfp_type_da_cu_core1:
  1050. *linear = true;
  1051. break;
  1052. case ixgbe_sfp_type_srlr_core0:
  1053. case ixgbe_sfp_type_srlr_core1:
  1054. case ixgbe_sfp_type_da_act_lmt_core0:
  1055. case ixgbe_sfp_type_da_act_lmt_core1:
  1056. case ixgbe_sfp_type_1g_sx_core0:
  1057. case ixgbe_sfp_type_1g_sx_core1:
  1058. case ixgbe_sfp_type_1g_lx_core0:
  1059. case ixgbe_sfp_type_1g_lx_core1:
  1060. *linear = false;
  1061. break;
  1062. case ixgbe_sfp_type_unknown:
  1063. case ixgbe_sfp_type_1g_cu_core0:
  1064. case ixgbe_sfp_type_1g_cu_core1:
  1065. default:
  1066. return IXGBE_ERR_SFP_NOT_SUPPORTED;
  1067. }
  1068. return 0;
  1069. }
  1070. /**
  1071. * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
  1072. * @hw: pointer to hardware structure
  1073. *
  1074. * Configures the extern PHY and the integrated KR PHY for SFP support.
  1075. */
  1076. static s32
  1077. ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
  1078. ixgbe_link_speed speed,
  1079. __always_unused bool autoneg_wait_to_complete)
  1080. {
  1081. s32 status;
  1082. u16 slice, value;
  1083. bool setup_linear = false;
  1084. /* Check if SFP module is supported and linear */
  1085. status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
  1086. /* If no SFP module present, then return success. Return success since
  1087. * there is no reason to configure CS4227 and SFP not present error is
  1088. * not accepted in the setup MAC link flow.
  1089. */
  1090. if (status == IXGBE_ERR_SFP_NOT_PRESENT)
  1091. return 0;
  1092. if (status)
  1093. return status;
  1094. /* Configure CS4227 LINE side to 10G SR. */
  1095. slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
  1096. value = IXGBE_CS4227_SPEED_10G;
  1097. status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227, slice,
  1098. value);
  1099. /* Configure CS4227 for HOST connection rate then type. */
  1100. slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
  1101. value = speed & IXGBE_LINK_SPEED_10GB_FULL ?
  1102. IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
  1103. status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227, slice,
  1104. value);
  1105. slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
  1106. if (setup_linear)
  1107. value = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
  1108. else
  1109. value = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
  1110. status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227, slice,
  1111. value);
  1112. /* If internal link mode is XFI, then setup XFI internal link. */
  1113. if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))
  1114. status = ixgbe_setup_ixfi_x550em(hw, &speed);
  1115. return status;
  1116. }
  1117. /**
  1118. * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
  1119. * @hw: pointer to hardware structure
  1120. * @speed: new link speed
  1121. * @autoneg_wait_to_complete: true when waiting for completion is needed
  1122. *
  1123. * Setup internal/external PHY link speed based on link speed, then set
  1124. * external PHY auto advertised link speed.
  1125. *
  1126. * Returns error status for any failure
  1127. **/
  1128. static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
  1129. ixgbe_link_speed speed,
  1130. bool autoneg_wait)
  1131. {
  1132. s32 status;
  1133. ixgbe_link_speed force_speed;
  1134. /* Setup internal/external PHY link speed to iXFI (10G), unless
  1135. * only 1G is auto advertised then setup KX link.
  1136. */
  1137. if (speed & IXGBE_LINK_SPEED_10GB_FULL)
  1138. force_speed = IXGBE_LINK_SPEED_10GB_FULL;
  1139. else
  1140. force_speed = IXGBE_LINK_SPEED_1GB_FULL;
  1141. /* If internal link mode is XFI, then setup XFI internal link. */
  1142. if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
  1143. status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
  1144. if (status)
  1145. return status;
  1146. }
  1147. return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
  1148. }
  1149. /** ixgbe_check_link_t_X550em - Determine link and speed status
  1150. * @hw: pointer to hardware structure
  1151. * @speed: pointer to link speed
  1152. * @link_up: true when link is up
  1153. * @link_up_wait_to_complete: bool used to wait for link up or not
  1154. *
  1155. * Check that both the MAC and X557 external PHY have link.
  1156. **/
  1157. static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw,
  1158. ixgbe_link_speed *speed,
  1159. bool *link_up,
  1160. bool link_up_wait_to_complete)
  1161. {
  1162. u32 status;
  1163. u16 autoneg_status;
  1164. if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
  1165. return IXGBE_ERR_CONFIG;
  1166. status = ixgbe_check_mac_link_generic(hw, speed, link_up,
  1167. link_up_wait_to_complete);
  1168. /* If check link fails or MAC link is not up, then return */
  1169. if (status || !(*link_up))
  1170. return status;
  1171. /* MAC link is up, so check external PHY link.
  1172. * Read this twice back to back to indicate current status.
  1173. */
  1174. status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
  1175. IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
  1176. &autoneg_status);
  1177. if (status)
  1178. return status;
  1179. /* If external PHY link is not up, then indicate link not up */
  1180. if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
  1181. *link_up = false;
  1182. return 0;
  1183. }
  1184. /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers
  1185. * @hw: pointer to hardware structure
  1186. **/
  1187. static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
  1188. {
  1189. struct ixgbe_mac_info *mac = &hw->mac;
  1190. switch (mac->ops.get_media_type(hw)) {
  1191. case ixgbe_media_type_fiber:
  1192. /* CS4227 does not support autoneg, so disable the laser control
  1193. * functions for SFP+ fiber
  1194. */
  1195. mac->ops.disable_tx_laser = NULL;
  1196. mac->ops.enable_tx_laser = NULL;
  1197. mac->ops.flap_tx_laser = NULL;
  1198. mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
  1199. mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
  1200. mac->ops.set_rate_select_speed =
  1201. ixgbe_set_soft_rate_select_speed;
  1202. break;
  1203. case ixgbe_media_type_copper:
  1204. mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
  1205. mac->ops.check_link = ixgbe_check_link_t_X550em;
  1206. break;
  1207. default:
  1208. break;
  1209. }
  1210. }
  1211. /** ixgbe_setup_sfp_modules_X550em - Setup SFP module
  1212. * @hw: pointer to hardware structure
  1213. */
  1214. static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
  1215. {
  1216. s32 status;
  1217. bool linear;
  1218. /* Check if SFP module is supported */
  1219. status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
  1220. if (status)
  1221. return status;
  1222. ixgbe_init_mac_link_ops_X550em(hw);
  1223. hw->phy.ops.reset = NULL;
  1224. return 0;
  1225. }
  1226. /** ixgbe_get_link_capabilities_x550em - Determines link capabilities
  1227. * @hw: pointer to hardware structure
  1228. * @speed: pointer to link speed
  1229. * @autoneg: true when autoneg or autotry is enabled
  1230. **/
  1231. static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
  1232. ixgbe_link_speed *speed,
  1233. bool *autoneg)
  1234. {
  1235. /* SFP */
  1236. if (hw->phy.media_type == ixgbe_media_type_fiber) {
  1237. /* CS4227 SFP must not enable auto-negotiation */
  1238. *autoneg = false;
  1239. if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
  1240. hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 ||
  1241. hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
  1242. hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
  1243. *speed = IXGBE_LINK_SPEED_1GB_FULL;
  1244. return 0;
  1245. }
  1246. /* Link capabilities are based on SFP */
  1247. if (hw->phy.multispeed_fiber)
  1248. *speed = IXGBE_LINK_SPEED_10GB_FULL |
  1249. IXGBE_LINK_SPEED_1GB_FULL;
  1250. else
  1251. *speed = IXGBE_LINK_SPEED_10GB_FULL;
  1252. } else {
  1253. *speed = IXGBE_LINK_SPEED_10GB_FULL |
  1254. IXGBE_LINK_SPEED_1GB_FULL;
  1255. *autoneg = true;
  1256. }
  1257. return 0;
  1258. }
  1259. /**
  1260. * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
  1261. * @hw: pointer to hardware structure
  1262. * @lsc: pointer to boolean flag which indicates whether external Base T
  1263. * PHY interrupt is lsc
  1264. *
  1265. * Determime if external Base T PHY interrupt cause is high temperature
  1266. * failure alarm or link status change.
  1267. *
  1268. * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
  1269. * failure alarm, else return PHY access status.
  1270. **/
  1271. static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
  1272. {
  1273. u32 status;
  1274. u16 reg;
  1275. *lsc = false;
  1276. /* Vendor alarm triggered */
  1277. status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
  1278. IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
  1279. &reg);
  1280. if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
  1281. return status;
  1282. /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
  1283. status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
  1284. IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
  1285. &reg);
  1286. if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
  1287. IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
  1288. return status;
  1289. /* High temperature failure alarm triggered */
  1290. status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
  1291. IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
  1292. &reg);
  1293. if (status)
  1294. return status;
  1295. /* If high temperature failure, then return over temp error and exit */
  1296. if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
  1297. /* power down the PHY in case the PHY FW didn't already */
  1298. ixgbe_set_copper_phy_power(hw, false);
  1299. return IXGBE_ERR_OVERTEMP;
  1300. }
  1301. /* Vendor alarm 2 triggered */
  1302. status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
  1303. IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
  1304. if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
  1305. return status;
  1306. /* link connect/disconnect event occurred */
  1307. status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
  1308. IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
  1309. if (status)
  1310. return status;
  1311. /* Indicate LSC */
  1312. if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
  1313. *lsc = true;
  1314. return 0;
  1315. }
  1316. /**
  1317. * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
  1318. * @hw: pointer to hardware structure
  1319. *
  1320. * Enable link status change and temperature failure alarm for the external
  1321. * Base T PHY
  1322. *
  1323. * Returns PHY access status
  1324. **/
  1325. static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
  1326. {
  1327. u32 status;
  1328. u16 reg;
  1329. bool lsc;
  1330. /* Clear interrupt flags */
  1331. status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
  1332. /* Enable link status change alarm */
  1333. status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
  1334. IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
  1335. if (status)
  1336. return status;
  1337. reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
  1338. status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
  1339. IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
  1340. if (status)
  1341. return status;
  1342. /* Enables high temperature failure alarm */
  1343. status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
  1344. IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
  1345. &reg);
  1346. if (status)
  1347. return status;
  1348. reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
  1349. status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
  1350. IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
  1351. reg);
  1352. if (status)
  1353. return status;
  1354. /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
  1355. status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
  1356. IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
  1357. &reg);
  1358. if (status)
  1359. return status;
  1360. reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
  1361. IXGBE_MDIO_GLOBAL_ALARM_1_INT);
  1362. status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
  1363. IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
  1364. reg);
  1365. if (status)
  1366. return status;
  1367. /* Enable chip-wide vendor alarm */
  1368. status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
  1369. IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
  1370. &reg);
  1371. if (status)
  1372. return status;
  1373. reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
  1374. status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
  1375. IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
  1376. reg);
  1377. return status;
  1378. }
  1379. /**
  1380. * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
  1381. * @hw: pointer to hardware structure
  1382. *
  1383. * Handle external Base T PHY interrupt. If high temperature
  1384. * failure alarm then return error, else if link status change
  1385. * then setup internal/external PHY link
  1386. *
  1387. * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
  1388. * failure alarm, else return PHY access status.
  1389. **/
  1390. static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
  1391. {
  1392. struct ixgbe_phy_info *phy = &hw->phy;
  1393. bool lsc;
  1394. u32 status;
  1395. status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
  1396. if (status)
  1397. return status;
  1398. if (lsc && phy->ops.setup_internal_link)
  1399. return phy->ops.setup_internal_link(hw);
  1400. return 0;
  1401. }
  1402. /**
  1403. * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
  1404. * @hw: pointer to hardware structure
  1405. * @speed: link speed
  1406. *
  1407. * Configures the integrated KR PHY.
  1408. **/
  1409. static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
  1410. ixgbe_link_speed speed)
  1411. {
  1412. s32 status;
  1413. u32 reg_val;
  1414. status = ixgbe_read_iosf_sb_reg_x550(hw,
  1415. IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
  1416. IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
  1417. if (status)
  1418. return status;
  1419. reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
  1420. reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
  1421. IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
  1422. /* Advertise 10G support. */
  1423. if (speed & IXGBE_LINK_SPEED_10GB_FULL)
  1424. reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
  1425. /* Advertise 1G support. */
  1426. if (speed & IXGBE_LINK_SPEED_1GB_FULL)
  1427. reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
  1428. /* Restart auto-negotiation. */
  1429. reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
  1430. status = ixgbe_write_iosf_sb_reg_x550(hw,
  1431. IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
  1432. IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
  1433. return status;
  1434. }
  1435. /** ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
  1436. * @hw: pointer to hardware structure
  1437. *
  1438. * Configures the integrated KX4 PHY.
  1439. **/
  1440. static s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
  1441. {
  1442. s32 status;
  1443. u32 reg_val;
  1444. status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
  1445. IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
  1446. hw->bus.lan_id, &reg_val);
  1447. if (status)
  1448. return status;
  1449. reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
  1450. IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
  1451. reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
  1452. /* Advertise 10G support. */
  1453. if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
  1454. reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
  1455. /* Advertise 1G support. */
  1456. if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
  1457. reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
  1458. /* Restart auto-negotiation. */
  1459. reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
  1460. status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
  1461. IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
  1462. hw->bus.lan_id, reg_val);
  1463. return status;
  1464. }
  1465. /** ixgbe_setup_kr_x550em - Configure the KR PHY.
  1466. * @hw: pointer to hardware structure
  1467. *
  1468. * Configures the integrated KR PHY.
  1469. **/
  1470. static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
  1471. {
  1472. return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
  1473. }
  1474. /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
  1475. * @hw: address of hardware structure
  1476. * @link_up: address of boolean to indicate link status
  1477. *
  1478. * Returns error code if unable to get link status.
  1479. **/
  1480. static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
  1481. {
  1482. u32 ret;
  1483. u16 autoneg_status;
  1484. *link_up = false;
  1485. /* read this twice back to back to indicate current status */
  1486. ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
  1487. IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
  1488. &autoneg_status);
  1489. if (ret)
  1490. return ret;
  1491. ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
  1492. IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
  1493. &autoneg_status);
  1494. if (ret)
  1495. return ret;
  1496. *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
  1497. return 0;
  1498. }
  1499. /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
  1500. * @hw: point to hardware structure
  1501. *
  1502. * Configures the link between the integrated KR PHY and the external X557 PHY
  1503. * The driver will call this function when it gets a link status change
  1504. * interrupt from the X557 PHY. This function configures the link speed
  1505. * between the PHYs to match the link speed of the BASE-T link.
  1506. *
  1507. * A return of a non-zero value indicates an error, and the base driver should
  1508. * not report link up.
  1509. **/
  1510. static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
  1511. {
  1512. ixgbe_link_speed force_speed;
  1513. bool link_up;
  1514. u32 status;
  1515. u16 speed;
  1516. if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
  1517. return IXGBE_ERR_CONFIG;
  1518. /* If link is not up, then there is no setup necessary so return */
  1519. status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
  1520. if (status)
  1521. return status;
  1522. if (!link_up)
  1523. return 0;
  1524. status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
  1525. IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
  1526. &speed);
  1527. if (status)
  1528. return status;
  1529. /* If link is not still up, then no setup is necessary so return */
  1530. status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
  1531. if (status)
  1532. return status;
  1533. if (!link_up)
  1534. return 0;
  1535. /* clear everything but the speed and duplex bits */
  1536. speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
  1537. switch (speed) {
  1538. case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
  1539. force_speed = IXGBE_LINK_SPEED_10GB_FULL;
  1540. break;
  1541. case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
  1542. force_speed = IXGBE_LINK_SPEED_1GB_FULL;
  1543. break;
  1544. default:
  1545. /* Internal PHY does not support anything else */
  1546. return IXGBE_ERR_INVALID_LINK_SETTINGS;
  1547. }
  1548. return ixgbe_setup_ixfi_x550em(hw, &force_speed);
  1549. }
  1550. /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
  1551. * @hw: pointer to hardware structure
  1552. **/
  1553. static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
  1554. {
  1555. s32 status;
  1556. status = ixgbe_reset_phy_generic(hw);
  1557. if (status)
  1558. return status;
  1559. /* Configure Link Status Alarm and Temperature Threshold interrupts */
  1560. return ixgbe_enable_lasi_ext_t_x550em(hw);
  1561. }
  1562. /** ixgbe_get_lcd_x550em - Determine lowest common denominator
  1563. * @hw: pointer to hardware structure
  1564. * @lcd_speed: pointer to lowest common link speed
  1565. *
  1566. * Determine lowest common link speed with link partner.
  1567. **/
  1568. static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw,
  1569. ixgbe_link_speed *lcd_speed)
  1570. {
  1571. u16 an_lp_status;
  1572. s32 status;
  1573. u16 word = hw->eeprom.ctrl_word_3;
  1574. *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
  1575. status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
  1576. IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
  1577. &an_lp_status);
  1578. if (status)
  1579. return status;
  1580. /* If link partner advertised 1G, return 1G */
  1581. if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
  1582. *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
  1583. return status;
  1584. }
  1585. /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
  1586. if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
  1587. (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
  1588. return status;
  1589. /* Link partner not capable of lower speeds, return 10G */
  1590. *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
  1591. return status;
  1592. }
  1593. /** ixgbe_enter_lplu_x550em - Transition to low power states
  1594. * @hw: pointer to hardware structure
  1595. *
  1596. * Configures Low Power Link Up on transition to low power states
  1597. * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting
  1598. * the X557 PHY immediately prior to entering LPLU.
  1599. **/
  1600. static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
  1601. {
  1602. u16 an_10g_cntl_reg, autoneg_reg, speed;
  1603. s32 status;
  1604. ixgbe_link_speed lcd_speed;
  1605. u32 save_autoneg;
  1606. bool link_up;
  1607. /* If blocked by MNG FW, then don't restart AN */
  1608. if (ixgbe_check_reset_blocked(hw))
  1609. return 0;
  1610. status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
  1611. if (status)
  1612. return status;
  1613. status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3,
  1614. &hw->eeprom.ctrl_word_3);
  1615. if (status)
  1616. return status;
  1617. /* If link is down, LPLU disabled in NVM, WoL disabled, or
  1618. * manageability disabled, then force link down by entering
  1619. * low power mode.
  1620. */
  1621. if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
  1622. !(hw->wol_enabled || ixgbe_mng_present(hw)))
  1623. return ixgbe_set_copper_phy_power(hw, false);
  1624. /* Determine LCD */
  1625. status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
  1626. if (status)
  1627. return status;
  1628. /* If no valid LCD link speed, then force link down and exit. */
  1629. if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
  1630. return ixgbe_set_copper_phy_power(hw, false);
  1631. status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
  1632. IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
  1633. &speed);
  1634. if (status)
  1635. return status;
  1636. /* If no link now, speed is invalid so take link down */
  1637. status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
  1638. if (status)
  1639. return ixgbe_set_copper_phy_power(hw, false);
  1640. /* clear everything but the speed bits */
  1641. speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
  1642. /* If current speed is already LCD, then exit. */
  1643. if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
  1644. (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
  1645. ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
  1646. (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
  1647. return status;
  1648. /* Clear AN completed indication */
  1649. status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
  1650. IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
  1651. &autoneg_reg);
  1652. if (status)
  1653. return status;
  1654. status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
  1655. IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
  1656. &an_10g_cntl_reg);
  1657. if (status)
  1658. return status;
  1659. status = hw->phy.ops.read_reg(hw,
  1660. IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
  1661. IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
  1662. &autoneg_reg);
  1663. if (status)
  1664. return status;
  1665. save_autoneg = hw->phy.autoneg_advertised;
  1666. /* Setup link at least common link speed */
  1667. status = hw->mac.ops.setup_link(hw, lcd_speed, false);
  1668. /* restore autoneg from before setting lplu speed */
  1669. hw->phy.autoneg_advertised = save_autoneg;
  1670. return status;
  1671. }
  1672. /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
  1673. * @hw: pointer to hardware structure
  1674. *
  1675. * Initialize any function pointers that were not able to be
  1676. * set during init_shared_code because the PHY/SFP type was
  1677. * not known. Perform the SFP init if necessary.
  1678. **/
  1679. static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
  1680. {
  1681. struct ixgbe_phy_info *phy = &hw->phy;
  1682. ixgbe_link_speed speed;
  1683. s32 ret_val;
  1684. hw->mac.ops.set_lan_id(hw);
  1685. if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
  1686. phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
  1687. ixgbe_setup_mux_ctl(hw);
  1688. /* Save NW management interface connected on board. This is used
  1689. * to determine internal PHY mode.
  1690. */
  1691. phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
  1692. /* If internal PHY mode is KR, then initialize KR link */
  1693. if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) {
  1694. speed = IXGBE_LINK_SPEED_10GB_FULL |
  1695. IXGBE_LINK_SPEED_1GB_FULL;
  1696. ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
  1697. }
  1698. }
  1699. /* Identify the PHY or SFP module */
  1700. ret_val = phy->ops.identify(hw);
  1701. /* Setup function pointers based on detected hardware */
  1702. ixgbe_init_mac_link_ops_X550em(hw);
  1703. if (phy->sfp_type != ixgbe_sfp_type_unknown)
  1704. phy->ops.reset = NULL;
  1705. /* Set functions pointers based on phy type */
  1706. switch (hw->phy.type) {
  1707. case ixgbe_phy_x550em_kx4:
  1708. phy->ops.setup_link = ixgbe_setup_kx4_x550em;
  1709. phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
  1710. phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
  1711. break;
  1712. case ixgbe_phy_x550em_kr:
  1713. phy->ops.setup_link = ixgbe_setup_kr_x550em;
  1714. phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
  1715. phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
  1716. break;
  1717. case ixgbe_phy_x550em_ext_t:
  1718. /* Save NW management interface connected on board. This is used
  1719. * to determine internal PHY mode
  1720. */
  1721. phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
  1722. /* If internal link mode is XFI, then setup iXFI internal link,
  1723. * else setup KR now.
  1724. */
  1725. if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
  1726. phy->ops.setup_internal_link =
  1727. ixgbe_setup_internal_phy_t_x550em;
  1728. } else {
  1729. speed = IXGBE_LINK_SPEED_10GB_FULL |
  1730. IXGBE_LINK_SPEED_1GB_FULL;
  1731. ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
  1732. }
  1733. /* setup SW LPLU only for first revision */
  1734. if (hw->mac.type == ixgbe_mac_X550EM_x &&
  1735. !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) &
  1736. IXGBE_FUSES0_REV_MASK))
  1737. phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
  1738. phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
  1739. phy->ops.reset = ixgbe_reset_phy_t_X550em;
  1740. break;
  1741. default:
  1742. break;
  1743. }
  1744. return ret_val;
  1745. }
  1746. /** ixgbe_get_media_type_X550em - Get media type
  1747. * @hw: pointer to hardware structure
  1748. *
  1749. * Returns the media type (fiber, copper, backplane)
  1750. *
  1751. */
  1752. static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
  1753. {
  1754. enum ixgbe_media_type media_type;
  1755. /* Detect if there is a copper PHY attached. */
  1756. switch (hw->device_id) {
  1757. case IXGBE_DEV_ID_X550EM_X_KR:
  1758. case IXGBE_DEV_ID_X550EM_X_KX4:
  1759. media_type = ixgbe_media_type_backplane;
  1760. break;
  1761. case IXGBE_DEV_ID_X550EM_X_SFP:
  1762. media_type = ixgbe_media_type_fiber;
  1763. break;
  1764. case IXGBE_DEV_ID_X550EM_X_1G_T:
  1765. case IXGBE_DEV_ID_X550EM_X_10G_T:
  1766. media_type = ixgbe_media_type_copper;
  1767. break;
  1768. default:
  1769. media_type = ixgbe_media_type_unknown;
  1770. break;
  1771. }
  1772. return media_type;
  1773. }
  1774. /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
  1775. ** @hw: pointer to hardware structure
  1776. **/
  1777. static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
  1778. {
  1779. s32 status;
  1780. u16 reg;
  1781. status = hw->phy.ops.read_reg(hw,
  1782. IXGBE_MDIO_TX_VENDOR_ALARMS_3,
  1783. IXGBE_MDIO_PMA_PMD_DEV_TYPE,
  1784. &reg);
  1785. if (status)
  1786. return status;
  1787. /* If PHY FW reset completed bit is set then this is the first
  1788. * SW instance after a power on so the PHY FW must be un-stalled.
  1789. */
  1790. if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
  1791. status = hw->phy.ops.read_reg(hw,
  1792. IXGBE_MDIO_GLOBAL_RES_PR_10,
  1793. IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
  1794. &reg);
  1795. if (status)
  1796. return status;
  1797. reg &= ~IXGBE_MDIO_POWER_UP_STALL;
  1798. status = hw->phy.ops.write_reg(hw,
  1799. IXGBE_MDIO_GLOBAL_RES_PR_10,
  1800. IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
  1801. reg);
  1802. if (status)
  1803. return status;
  1804. }
  1805. return status;
  1806. }
  1807. /** ixgbe_reset_hw_X550em - Perform hardware reset
  1808. ** @hw: pointer to hardware structure
  1809. **
  1810. ** Resets the hardware by resetting the transmit and receive units, masks
  1811. ** and clears all interrupts, perform a PHY reset, and perform a link (MAC)
  1812. ** reset.
  1813. **/
  1814. static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
  1815. {
  1816. ixgbe_link_speed link_speed;
  1817. s32 status;
  1818. u32 ctrl = 0;
  1819. u32 i;
  1820. u32 hlreg0;
  1821. bool link_up = false;
  1822. /* Call adapter stop to disable Tx/Rx and clear interrupts */
  1823. status = hw->mac.ops.stop_adapter(hw);
  1824. if (status)
  1825. return status;
  1826. /* flush pending Tx transactions */
  1827. ixgbe_clear_tx_pending(hw);
  1828. /* PHY ops must be identified and initialized prior to reset */
  1829. /* Identify PHY and related function pointers */
  1830. status = hw->phy.ops.init(hw);
  1831. /* start the external PHY */
  1832. if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
  1833. status = ixgbe_init_ext_t_x550em(hw);
  1834. if (status)
  1835. return status;
  1836. }
  1837. /* Setup SFP module if there is one present. */
  1838. if (hw->phy.sfp_setup_needed) {
  1839. status = hw->mac.ops.setup_sfp(hw);
  1840. hw->phy.sfp_setup_needed = false;
  1841. }
  1842. /* Reset PHY */
  1843. if (!hw->phy.reset_disable && hw->phy.ops.reset)
  1844. hw->phy.ops.reset(hw);
  1845. mac_reset_top:
  1846. /* Issue global reset to the MAC. Needs to be SW reset if link is up.
  1847. * If link reset is used when link is up, it might reset the PHY when
  1848. * mng is using it. If link is down or the flag to force full link
  1849. * reset is set, then perform link reset.
  1850. */
  1851. ctrl = IXGBE_CTRL_LNK_RST;
  1852. if (!hw->force_full_reset) {
  1853. hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
  1854. if (link_up)
  1855. ctrl = IXGBE_CTRL_RST;
  1856. }
  1857. ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
  1858. IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
  1859. IXGBE_WRITE_FLUSH(hw);
  1860. /* Poll for reset bit to self-clear meaning reset is complete */
  1861. for (i = 0; i < 10; i++) {
  1862. udelay(1);
  1863. ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
  1864. if (!(ctrl & IXGBE_CTRL_RST_MASK))
  1865. break;
  1866. }
  1867. if (ctrl & IXGBE_CTRL_RST_MASK) {
  1868. status = IXGBE_ERR_RESET_FAILED;
  1869. hw_dbg(hw, "Reset polling failed to complete.\n");
  1870. }
  1871. msleep(50);
  1872. /* Double resets are required for recovery from certain error
  1873. * clear the multicast table. Also reset num_rar_entries to 128,
  1874. * since we modify this value when programming the SAN MAC address.
  1875. */
  1876. if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
  1877. hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
  1878. goto mac_reset_top;
  1879. }
  1880. /* Store the permanent mac address */
  1881. hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
  1882. /* Store MAC address from RAR0, clear receive address registers, and
  1883. * clear the multicast table. Also reset num_rar_entries to 128,
  1884. * since we modify this value when programming the SAN MAC address.
  1885. */
  1886. hw->mac.num_rar_entries = 128;
  1887. hw->mac.ops.init_rx_addrs(hw);
  1888. if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
  1889. hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
  1890. hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
  1891. IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
  1892. }
  1893. if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
  1894. ixgbe_setup_mux_ctl(hw);
  1895. return status;
  1896. }
  1897. /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype
  1898. * anti-spoofing
  1899. * @hw: pointer to hardware structure
  1900. * @enable: enable or disable switch for Ethertype anti-spoofing
  1901. * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
  1902. **/
  1903. static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
  1904. bool enable, int vf)
  1905. {
  1906. int vf_target_reg = vf >> 3;
  1907. int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
  1908. u32 pfvfspoof;
  1909. pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
  1910. if (enable)
  1911. pfvfspoof |= (1 << vf_target_shift);
  1912. else
  1913. pfvfspoof &= ~(1 << vf_target_shift);
  1914. IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
  1915. }
  1916. /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning
  1917. * @hw: pointer to hardware structure
  1918. * @enable: enable or disable source address pruning
  1919. * @pool: Rx pool to set source address pruning for
  1920. **/
  1921. static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw,
  1922. bool enable,
  1923. unsigned int pool)
  1924. {
  1925. u64 pfflp;
  1926. /* max rx pool is 63 */
  1927. if (pool > 63)
  1928. return;
  1929. pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
  1930. pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
  1931. if (enable)
  1932. pfflp |= (1ULL << pool);
  1933. else
  1934. pfflp &= ~(1ULL << pool);
  1935. IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
  1936. IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
  1937. }
  1938. /**
  1939. * ixgbe_set_mux - Set mux for port 1 access with CS4227
  1940. * @hw: pointer to hardware structure
  1941. * @state: set mux if 1, clear if 0
  1942. */
  1943. static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
  1944. {
  1945. u32 esdp;
  1946. if (!hw->bus.lan_id)
  1947. return;
  1948. esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
  1949. if (state)
  1950. esdp |= IXGBE_ESDP_SDP1;
  1951. else
  1952. esdp &= ~IXGBE_ESDP_SDP1;
  1953. IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
  1954. IXGBE_WRITE_FLUSH(hw);
  1955. }
  1956. /**
  1957. * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
  1958. * @hw: pointer to hardware structure
  1959. * @mask: Mask to specify which semaphore to acquire
  1960. *
  1961. * Acquires the SWFW semaphore and sets the I2C MUX
  1962. */
  1963. static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
  1964. {
  1965. s32 status;
  1966. status = ixgbe_acquire_swfw_sync_X540(hw, mask);
  1967. if (status)
  1968. return status;
  1969. if (mask & IXGBE_GSSR_I2C_MASK)
  1970. ixgbe_set_mux(hw, 1);
  1971. return 0;
  1972. }
  1973. /**
  1974. * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
  1975. * @hw: pointer to hardware structure
  1976. * @mask: Mask to specify which semaphore to release
  1977. *
  1978. * Releases the SWFW semaphore and sets the I2C MUX
  1979. */
  1980. static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
  1981. {
  1982. if (mask & IXGBE_GSSR_I2C_MASK)
  1983. ixgbe_set_mux(hw, 0);
  1984. ixgbe_release_swfw_sync_X540(hw, mask);
  1985. }
  1986. #define X550_COMMON_MAC \
  1987. .init_hw = &ixgbe_init_hw_generic, \
  1988. .start_hw = &ixgbe_start_hw_X540, \
  1989. .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, \
  1990. .enable_rx_dma = &ixgbe_enable_rx_dma_generic, \
  1991. .get_mac_addr = &ixgbe_get_mac_addr_generic, \
  1992. .get_device_caps = &ixgbe_get_device_caps_generic, \
  1993. .stop_adapter = &ixgbe_stop_adapter_generic, \
  1994. .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, \
  1995. .read_analog_reg8 = NULL, \
  1996. .write_analog_reg8 = NULL, \
  1997. .set_rxpba = &ixgbe_set_rxpba_generic, \
  1998. .check_link = &ixgbe_check_mac_link_generic, \
  1999. .led_on = &ixgbe_led_on_generic, \
  2000. .led_off = &ixgbe_led_off_generic, \
  2001. .blink_led_start = &ixgbe_blink_led_start_X540, \
  2002. .blink_led_stop = &ixgbe_blink_led_stop_X540, \
  2003. .set_rar = &ixgbe_set_rar_generic, \
  2004. .clear_rar = &ixgbe_clear_rar_generic, \
  2005. .set_vmdq = &ixgbe_set_vmdq_generic, \
  2006. .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, \
  2007. .clear_vmdq = &ixgbe_clear_vmdq_generic, \
  2008. .init_rx_addrs = &ixgbe_init_rx_addrs_generic, \
  2009. .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, \
  2010. .enable_mc = &ixgbe_enable_mc_generic, \
  2011. .disable_mc = &ixgbe_disable_mc_generic, \
  2012. .clear_vfta = &ixgbe_clear_vfta_generic, \
  2013. .set_vfta = &ixgbe_set_vfta_generic, \
  2014. .fc_enable = &ixgbe_fc_enable_generic, \
  2015. .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic, \
  2016. .init_uta_tables = &ixgbe_init_uta_tables_generic, \
  2017. .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, \
  2018. .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, \
  2019. .set_source_address_pruning = \
  2020. &ixgbe_set_source_address_pruning_X550, \
  2021. .set_ethertype_anti_spoofing = \
  2022. &ixgbe_set_ethertype_anti_spoofing_X550, \
  2023. .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \
  2024. .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \
  2025. .get_thermal_sensor_data = NULL, \
  2026. .init_thermal_sensor_thresh = NULL, \
  2027. .prot_autoc_read = &prot_autoc_read_generic, \
  2028. .prot_autoc_write = &prot_autoc_write_generic, \
  2029. .enable_rx = &ixgbe_enable_rx_generic, \
  2030. .disable_rx = &ixgbe_disable_rx_x550, \
  2031. static struct ixgbe_mac_operations mac_ops_X550 = {
  2032. X550_COMMON_MAC
  2033. .reset_hw = &ixgbe_reset_hw_X540,
  2034. .get_media_type = &ixgbe_get_media_type_X540,
  2035. .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
  2036. .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
  2037. .setup_link = &ixgbe_setup_mac_link_X540,
  2038. .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic,
  2039. .get_bus_info = &ixgbe_get_bus_info_generic,
  2040. .setup_sfp = NULL,
  2041. .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540,
  2042. .release_swfw_sync = &ixgbe_release_swfw_sync_X540,
  2043. };
  2044. static struct ixgbe_mac_operations mac_ops_X550EM_x = {
  2045. X550_COMMON_MAC
  2046. .reset_hw = &ixgbe_reset_hw_X550em,
  2047. .get_media_type = &ixgbe_get_media_type_X550em,
  2048. .get_san_mac_addr = NULL,
  2049. .get_wwn_prefix = NULL,
  2050. .setup_link = NULL, /* defined later */
  2051. .get_link_capabilities = &ixgbe_get_link_capabilities_X550em,
  2052. .get_bus_info = &ixgbe_get_bus_info_X550em,
  2053. .setup_sfp = ixgbe_setup_sfp_modules_X550em,
  2054. .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em,
  2055. .release_swfw_sync = &ixgbe_release_swfw_sync_X550em,
  2056. };
  2057. #define X550_COMMON_EEP \
  2058. .read = &ixgbe_read_ee_hostif_X550, \
  2059. .read_buffer = &ixgbe_read_ee_hostif_buffer_X550, \
  2060. .write = &ixgbe_write_ee_hostif_X550, \
  2061. .write_buffer = &ixgbe_write_ee_hostif_buffer_X550, \
  2062. .validate_checksum = &ixgbe_validate_eeprom_checksum_X550, \
  2063. .update_checksum = &ixgbe_update_eeprom_checksum_X550, \
  2064. .calc_checksum = &ixgbe_calc_eeprom_checksum_X550, \
  2065. static struct ixgbe_eeprom_operations eeprom_ops_X550 = {
  2066. X550_COMMON_EEP
  2067. .init_params = &ixgbe_init_eeprom_params_X550,
  2068. };
  2069. static struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = {
  2070. X550_COMMON_EEP
  2071. .init_params = &ixgbe_init_eeprom_params_X540,
  2072. };
  2073. #define X550_COMMON_PHY \
  2074. .identify_sfp = &ixgbe_identify_module_generic, \
  2075. .reset = NULL, \
  2076. .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, \
  2077. .read_i2c_byte = &ixgbe_read_i2c_byte_generic, \
  2078. .write_i2c_byte = &ixgbe_write_i2c_byte_generic, \
  2079. .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \
  2080. .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \
  2081. .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \
  2082. .read_reg = &ixgbe_read_phy_reg_generic, \
  2083. .write_reg = &ixgbe_write_phy_reg_generic, \
  2084. .setup_link = &ixgbe_setup_phy_link_generic, \
  2085. .set_phy_power = NULL, \
  2086. .check_overtemp = &ixgbe_tn_check_overtemp, \
  2087. .get_firmware_version = &ixgbe_get_phy_firmware_version_generic,
  2088. static struct ixgbe_phy_operations phy_ops_X550 = {
  2089. X550_COMMON_PHY
  2090. .init = NULL,
  2091. .identify = &ixgbe_identify_phy_generic,
  2092. };
  2093. static struct ixgbe_phy_operations phy_ops_X550EM_x = {
  2094. X550_COMMON_PHY
  2095. .init = &ixgbe_init_phy_ops_X550em,
  2096. .identify = &ixgbe_identify_phy_x550em,
  2097. .read_i2c_combined = &ixgbe_read_i2c_combined_generic,
  2098. .write_i2c_combined = &ixgbe_write_i2c_combined_generic,
  2099. .read_i2c_combined_unlocked = &ixgbe_read_i2c_combined_generic_unlocked,
  2100. .write_i2c_combined_unlocked =
  2101. &ixgbe_write_i2c_combined_generic_unlocked,
  2102. };
  2103. static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
  2104. IXGBE_MVALS_INIT(X550)
  2105. };
  2106. static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
  2107. IXGBE_MVALS_INIT(X550EM_x)
  2108. };
  2109. struct ixgbe_info ixgbe_X550_info = {
  2110. .mac = ixgbe_mac_X550,
  2111. .get_invariants = &ixgbe_get_invariants_X540,
  2112. .mac_ops = &mac_ops_X550,
  2113. .eeprom_ops = &eeprom_ops_X550,
  2114. .phy_ops = &phy_ops_X550,
  2115. .mbx_ops = &mbx_ops_generic,
  2116. .mvals = ixgbe_mvals_X550,
  2117. };
  2118. struct ixgbe_info ixgbe_X550EM_x_info = {
  2119. .mac = ixgbe_mac_X550EM_x,
  2120. .get_invariants = &ixgbe_get_invariants_X550_x,
  2121. .mac_ops = &mac_ops_X550EM_x,
  2122. .eeprom_ops = &eeprom_ops_X550EM_x,
  2123. .phy_ops = &phy_ops_X550EM_x,
  2124. .mbx_ops = &mbx_ops_generic,
  2125. .mvals = ixgbe_mvals_X550EM_x,
  2126. };