catas.c 8.7 KB

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  1. /*
  2. * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
  3. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/workqueue.h>
  34. #include <linux/module.h>
  35. #include "mlx4.h"
  36. enum {
  37. MLX4_CATAS_POLL_INTERVAL = 5 * HZ,
  38. };
  39. int mlx4_internal_err_reset = 1;
  40. module_param_named(internal_err_reset, mlx4_internal_err_reset, int, 0644);
  41. MODULE_PARM_DESC(internal_err_reset,
  42. "Reset device on internal errors if non-zero (default 1)");
  43. static int read_vendor_id(struct mlx4_dev *dev)
  44. {
  45. u16 vendor_id = 0;
  46. int ret;
  47. ret = pci_read_config_word(dev->persist->pdev, 0, &vendor_id);
  48. if (ret) {
  49. mlx4_err(dev, "Failed to read vendor ID, ret=%d\n", ret);
  50. return ret;
  51. }
  52. if (vendor_id == 0xffff) {
  53. mlx4_err(dev, "PCI can't be accessed to read vendor id\n");
  54. return -EINVAL;
  55. }
  56. return 0;
  57. }
  58. static int mlx4_reset_master(struct mlx4_dev *dev)
  59. {
  60. int err = 0;
  61. if (mlx4_is_master(dev))
  62. mlx4_report_internal_err_comm_event(dev);
  63. if (!pci_channel_offline(dev->persist->pdev)) {
  64. err = read_vendor_id(dev);
  65. /* If PCI can't be accessed to read vendor ID we assume that its
  66. * link was disabled and chip was already reset.
  67. */
  68. if (err)
  69. return 0;
  70. err = mlx4_reset(dev);
  71. if (err)
  72. mlx4_err(dev, "Fail to reset HCA\n");
  73. }
  74. return err;
  75. }
  76. static int mlx4_reset_slave(struct mlx4_dev *dev)
  77. {
  78. #define COM_CHAN_RST_REQ_OFFSET 0x10
  79. #define COM_CHAN_RST_ACK_OFFSET 0x08
  80. u32 comm_flags;
  81. u32 rst_req;
  82. u32 rst_ack;
  83. unsigned long end;
  84. struct mlx4_priv *priv = mlx4_priv(dev);
  85. if (pci_channel_offline(dev->persist->pdev))
  86. return 0;
  87. comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm +
  88. MLX4_COMM_CHAN_FLAGS));
  89. if (comm_flags == 0xffffffff) {
  90. mlx4_err(dev, "VF reset is not needed\n");
  91. return 0;
  92. }
  93. if (!(dev->caps.vf_caps & MLX4_VF_CAP_FLAG_RESET)) {
  94. mlx4_err(dev, "VF reset is not supported\n");
  95. return -EOPNOTSUPP;
  96. }
  97. rst_req = (comm_flags & (u32)(1 << COM_CHAN_RST_REQ_OFFSET)) >>
  98. COM_CHAN_RST_REQ_OFFSET;
  99. rst_ack = (comm_flags & (u32)(1 << COM_CHAN_RST_ACK_OFFSET)) >>
  100. COM_CHAN_RST_ACK_OFFSET;
  101. if (rst_req != rst_ack) {
  102. mlx4_err(dev, "Communication channel isn't sync, fail to send reset\n");
  103. return -EIO;
  104. }
  105. rst_req ^= 1;
  106. mlx4_warn(dev, "VF is sending reset request to Firmware\n");
  107. comm_flags = rst_req << COM_CHAN_RST_REQ_OFFSET;
  108. __raw_writel((__force u32)cpu_to_be32(comm_flags),
  109. (__iomem char *)priv->mfunc.comm + MLX4_COMM_CHAN_FLAGS);
  110. /* Make sure that our comm channel write doesn't
  111. * get mixed in with writes from another CPU.
  112. */
  113. mmiowb();
  114. end = msecs_to_jiffies(MLX4_COMM_TIME) + jiffies;
  115. while (time_before(jiffies, end)) {
  116. comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm +
  117. MLX4_COMM_CHAN_FLAGS));
  118. rst_ack = (comm_flags & (u32)(1 << COM_CHAN_RST_ACK_OFFSET)) >>
  119. COM_CHAN_RST_ACK_OFFSET;
  120. /* Reading rst_req again since the communication channel can
  121. * be reset at any time by the PF and all its bits will be
  122. * set to zero.
  123. */
  124. rst_req = (comm_flags & (u32)(1 << COM_CHAN_RST_REQ_OFFSET)) >>
  125. COM_CHAN_RST_REQ_OFFSET;
  126. if (rst_ack == rst_req) {
  127. mlx4_warn(dev, "VF Reset succeed\n");
  128. return 0;
  129. }
  130. cond_resched();
  131. }
  132. mlx4_err(dev, "Fail to send reset over the communication channel\n");
  133. return -ETIMEDOUT;
  134. }
  135. int mlx4_comm_internal_err(u32 slave_read)
  136. {
  137. return (u32)COMM_CHAN_EVENT_INTERNAL_ERR ==
  138. (slave_read & (u32)COMM_CHAN_EVENT_INTERNAL_ERR) ? 1 : 0;
  139. }
  140. void mlx4_enter_error_state(struct mlx4_dev_persistent *persist)
  141. {
  142. int err;
  143. struct mlx4_dev *dev;
  144. if (!mlx4_internal_err_reset)
  145. return;
  146. mutex_lock(&persist->device_state_mutex);
  147. if (persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
  148. goto out;
  149. dev = persist->dev;
  150. mlx4_err(dev, "device is going to be reset\n");
  151. if (mlx4_is_slave(dev))
  152. err = mlx4_reset_slave(dev);
  153. else
  154. err = mlx4_reset_master(dev);
  155. BUG_ON(err != 0);
  156. dev->persist->state |= MLX4_DEVICE_STATE_INTERNAL_ERROR;
  157. mlx4_err(dev, "device was reset successfully\n");
  158. mutex_unlock(&persist->device_state_mutex);
  159. /* At that step HW was already reset, now notify clients */
  160. mlx4_dispatch_event(dev, MLX4_DEV_EVENT_CATASTROPHIC_ERROR, 0);
  161. mlx4_cmd_wake_completions(dev);
  162. return;
  163. out:
  164. mutex_unlock(&persist->device_state_mutex);
  165. }
  166. static void mlx4_handle_error_state(struct mlx4_dev_persistent *persist)
  167. {
  168. int err = 0;
  169. mlx4_enter_error_state(persist);
  170. mutex_lock(&persist->interface_state_mutex);
  171. if (persist->interface_state & MLX4_INTERFACE_STATE_UP &&
  172. !(persist->interface_state & MLX4_INTERFACE_STATE_DELETION)) {
  173. err = mlx4_restart_one(persist->pdev);
  174. mlx4_info(persist->dev, "mlx4_restart_one was ended, ret=%d\n",
  175. err);
  176. }
  177. mutex_unlock(&persist->interface_state_mutex);
  178. }
  179. static void dump_err_buf(struct mlx4_dev *dev)
  180. {
  181. struct mlx4_priv *priv = mlx4_priv(dev);
  182. int i;
  183. mlx4_err(dev, "Internal error detected:\n");
  184. for (i = 0; i < priv->fw.catas_size; ++i)
  185. mlx4_err(dev, " buf[%02x]: %08x\n",
  186. i, swab32(readl(priv->catas_err.map + i)));
  187. }
  188. static void poll_catas(unsigned long dev_ptr)
  189. {
  190. struct mlx4_dev *dev = (struct mlx4_dev *) dev_ptr;
  191. struct mlx4_priv *priv = mlx4_priv(dev);
  192. u32 slave_read;
  193. if (mlx4_is_slave(dev)) {
  194. slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
  195. if (mlx4_comm_internal_err(slave_read)) {
  196. mlx4_warn(dev, "Internal error detected on the communication channel\n");
  197. goto internal_err;
  198. }
  199. } else if (readl(priv->catas_err.map)) {
  200. dump_err_buf(dev);
  201. goto internal_err;
  202. }
  203. if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
  204. mlx4_warn(dev, "Internal error mark was detected on device\n");
  205. goto internal_err;
  206. }
  207. mod_timer(&priv->catas_err.timer,
  208. round_jiffies(jiffies + MLX4_CATAS_POLL_INTERVAL));
  209. return;
  210. internal_err:
  211. if (mlx4_internal_err_reset)
  212. queue_work(dev->persist->catas_wq, &dev->persist->catas_work);
  213. }
  214. static void catas_reset(struct work_struct *work)
  215. {
  216. struct mlx4_dev_persistent *persist =
  217. container_of(work, struct mlx4_dev_persistent,
  218. catas_work);
  219. mlx4_handle_error_state(persist);
  220. }
  221. void mlx4_start_catas_poll(struct mlx4_dev *dev)
  222. {
  223. struct mlx4_priv *priv = mlx4_priv(dev);
  224. phys_addr_t addr;
  225. INIT_LIST_HEAD(&priv->catas_err.list);
  226. init_timer(&priv->catas_err.timer);
  227. priv->catas_err.map = NULL;
  228. if (!mlx4_is_slave(dev)) {
  229. addr = pci_resource_start(dev->persist->pdev,
  230. priv->fw.catas_bar) +
  231. priv->fw.catas_offset;
  232. priv->catas_err.map = ioremap(addr, priv->fw.catas_size * 4);
  233. if (!priv->catas_err.map) {
  234. mlx4_warn(dev, "Failed to map internal error buffer at 0x%llx\n",
  235. (unsigned long long)addr);
  236. return;
  237. }
  238. }
  239. priv->catas_err.timer.data = (unsigned long) dev;
  240. priv->catas_err.timer.function = poll_catas;
  241. priv->catas_err.timer.expires =
  242. round_jiffies(jiffies + MLX4_CATAS_POLL_INTERVAL);
  243. add_timer(&priv->catas_err.timer);
  244. }
  245. void mlx4_stop_catas_poll(struct mlx4_dev *dev)
  246. {
  247. struct mlx4_priv *priv = mlx4_priv(dev);
  248. del_timer_sync(&priv->catas_err.timer);
  249. if (priv->catas_err.map) {
  250. iounmap(priv->catas_err.map);
  251. priv->catas_err.map = NULL;
  252. }
  253. if (dev->persist->interface_state & MLX4_INTERFACE_STATE_DELETION)
  254. flush_workqueue(dev->persist->catas_wq);
  255. }
  256. int mlx4_catas_init(struct mlx4_dev *dev)
  257. {
  258. INIT_WORK(&dev->persist->catas_work, catas_reset);
  259. dev->persist->catas_wq = create_singlethread_workqueue("mlx4_health");
  260. if (!dev->persist->catas_wq)
  261. return -ENOMEM;
  262. return 0;
  263. }
  264. void mlx4_catas_end(struct mlx4_dev *dev)
  265. {
  266. if (dev->persist->catas_wq) {
  267. destroy_workqueue(dev->persist->catas_wq);
  268. dev->persist->catas_wq = NULL;
  269. }
  270. }