srq.c 8.4 KB

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  1. /*
  2. * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
  3. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/mlx4/cmd.h>
  34. #include <linux/mlx4/srq.h>
  35. #include <linux/export.h>
  36. #include <linux/gfp.h>
  37. #include "mlx4.h"
  38. #include "icm.h"
  39. void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type)
  40. {
  41. struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
  42. struct mlx4_srq *srq;
  43. spin_lock(&srq_table->lock);
  44. srq = radix_tree_lookup(&srq_table->tree, srqn & (dev->caps.num_srqs - 1));
  45. if (srq)
  46. atomic_inc(&srq->refcount);
  47. spin_unlock(&srq_table->lock);
  48. if (!srq) {
  49. mlx4_warn(dev, "Async event for bogus SRQ %08x\n", srqn);
  50. return;
  51. }
  52. srq->event(srq, event_type);
  53. if (atomic_dec_and_test(&srq->refcount))
  54. complete(&srq->free);
  55. }
  56. static int mlx4_SW2HW_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
  57. int srq_num)
  58. {
  59. return mlx4_cmd(dev, mailbox->dma, srq_num, 0,
  60. MLX4_CMD_SW2HW_SRQ, MLX4_CMD_TIME_CLASS_A,
  61. MLX4_CMD_WRAPPED);
  62. }
  63. static int mlx4_HW2SW_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
  64. int srq_num)
  65. {
  66. return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, srq_num,
  67. mailbox ? 0 : 1, MLX4_CMD_HW2SW_SRQ,
  68. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
  69. }
  70. static int mlx4_ARM_SRQ(struct mlx4_dev *dev, int srq_num, int limit_watermark)
  71. {
  72. return mlx4_cmd(dev, limit_watermark, srq_num, 0, MLX4_CMD_ARM_SRQ,
  73. MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
  74. }
  75. static int mlx4_QUERY_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
  76. int srq_num)
  77. {
  78. return mlx4_cmd_box(dev, 0, mailbox->dma, srq_num, 0, MLX4_CMD_QUERY_SRQ,
  79. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
  80. }
  81. int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn)
  82. {
  83. struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
  84. int err;
  85. *srqn = mlx4_bitmap_alloc(&srq_table->bitmap);
  86. if (*srqn == -1)
  87. return -ENOMEM;
  88. err = mlx4_table_get(dev, &srq_table->table, *srqn, GFP_KERNEL);
  89. if (err)
  90. goto err_out;
  91. err = mlx4_table_get(dev, &srq_table->cmpt_table, *srqn, GFP_KERNEL);
  92. if (err)
  93. goto err_put;
  94. return 0;
  95. err_put:
  96. mlx4_table_put(dev, &srq_table->table, *srqn);
  97. err_out:
  98. mlx4_bitmap_free(&srq_table->bitmap, *srqn, MLX4_NO_RR);
  99. return err;
  100. }
  101. static int mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn)
  102. {
  103. u64 out_param;
  104. int err;
  105. if (mlx4_is_mfunc(dev)) {
  106. err = mlx4_cmd_imm(dev, 0, &out_param, RES_SRQ,
  107. RES_OP_RESERVE_AND_MAP,
  108. MLX4_CMD_ALLOC_RES,
  109. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
  110. if (!err)
  111. *srqn = get_param_l(&out_param);
  112. return err;
  113. }
  114. return __mlx4_srq_alloc_icm(dev, srqn);
  115. }
  116. void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn)
  117. {
  118. struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
  119. mlx4_table_put(dev, &srq_table->cmpt_table, srqn);
  120. mlx4_table_put(dev, &srq_table->table, srqn);
  121. mlx4_bitmap_free(&srq_table->bitmap, srqn, MLX4_NO_RR);
  122. }
  123. static void mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn)
  124. {
  125. u64 in_param = 0;
  126. if (mlx4_is_mfunc(dev)) {
  127. set_param_l(&in_param, srqn);
  128. if (mlx4_cmd(dev, in_param, RES_SRQ, RES_OP_RESERVE_AND_MAP,
  129. MLX4_CMD_FREE_RES,
  130. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED))
  131. mlx4_warn(dev, "Failed freeing cq:%d\n", srqn);
  132. return;
  133. }
  134. __mlx4_srq_free_icm(dev, srqn);
  135. }
  136. int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcd,
  137. struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq)
  138. {
  139. struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
  140. struct mlx4_cmd_mailbox *mailbox;
  141. struct mlx4_srq_context *srq_context;
  142. u64 mtt_addr;
  143. int err;
  144. err = mlx4_srq_alloc_icm(dev, &srq->srqn);
  145. if (err)
  146. return err;
  147. spin_lock_irq(&srq_table->lock);
  148. err = radix_tree_insert(&srq_table->tree, srq->srqn, srq);
  149. spin_unlock_irq(&srq_table->lock);
  150. if (err)
  151. goto err_icm;
  152. mailbox = mlx4_alloc_cmd_mailbox(dev);
  153. if (IS_ERR(mailbox)) {
  154. err = PTR_ERR(mailbox);
  155. goto err_radix;
  156. }
  157. srq_context = mailbox->buf;
  158. srq_context->state_logsize_srqn = cpu_to_be32((ilog2(srq->max) << 24) |
  159. srq->srqn);
  160. srq_context->logstride = srq->wqe_shift - 4;
  161. srq_context->xrcd = cpu_to_be16(xrcd);
  162. srq_context->pg_offset_cqn = cpu_to_be32(cqn & 0xffffff);
  163. srq_context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
  164. mtt_addr = mlx4_mtt_addr(dev, mtt);
  165. srq_context->mtt_base_addr_h = mtt_addr >> 32;
  166. srq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
  167. srq_context->pd = cpu_to_be32(pdn);
  168. srq_context->db_rec_addr = cpu_to_be64(db_rec);
  169. err = mlx4_SW2HW_SRQ(dev, mailbox, srq->srqn);
  170. mlx4_free_cmd_mailbox(dev, mailbox);
  171. if (err)
  172. goto err_radix;
  173. atomic_set(&srq->refcount, 1);
  174. init_completion(&srq->free);
  175. return 0;
  176. err_radix:
  177. spin_lock_irq(&srq_table->lock);
  178. radix_tree_delete(&srq_table->tree, srq->srqn);
  179. spin_unlock_irq(&srq_table->lock);
  180. err_icm:
  181. mlx4_srq_free_icm(dev, srq->srqn);
  182. return err;
  183. }
  184. EXPORT_SYMBOL_GPL(mlx4_srq_alloc);
  185. void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq)
  186. {
  187. struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
  188. int err;
  189. err = mlx4_HW2SW_SRQ(dev, NULL, srq->srqn);
  190. if (err)
  191. mlx4_warn(dev, "HW2SW_SRQ failed (%d) for SRQN %06x\n", err, srq->srqn);
  192. spin_lock_irq(&srq_table->lock);
  193. radix_tree_delete(&srq_table->tree, srq->srqn);
  194. spin_unlock_irq(&srq_table->lock);
  195. if (atomic_dec_and_test(&srq->refcount))
  196. complete(&srq->free);
  197. wait_for_completion(&srq->free);
  198. mlx4_srq_free_icm(dev, srq->srqn);
  199. }
  200. EXPORT_SYMBOL_GPL(mlx4_srq_free);
  201. int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark)
  202. {
  203. return mlx4_ARM_SRQ(dev, srq->srqn, limit_watermark);
  204. }
  205. EXPORT_SYMBOL_GPL(mlx4_srq_arm);
  206. int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark)
  207. {
  208. struct mlx4_cmd_mailbox *mailbox;
  209. struct mlx4_srq_context *srq_context;
  210. int err;
  211. mailbox = mlx4_alloc_cmd_mailbox(dev);
  212. if (IS_ERR(mailbox))
  213. return PTR_ERR(mailbox);
  214. srq_context = mailbox->buf;
  215. err = mlx4_QUERY_SRQ(dev, mailbox, srq->srqn);
  216. if (err)
  217. goto err_out;
  218. *limit_watermark = be16_to_cpu(srq_context->limit_watermark);
  219. err_out:
  220. mlx4_free_cmd_mailbox(dev, mailbox);
  221. return err;
  222. }
  223. EXPORT_SYMBOL_GPL(mlx4_srq_query);
  224. int mlx4_init_srq_table(struct mlx4_dev *dev)
  225. {
  226. struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
  227. int err;
  228. spin_lock_init(&srq_table->lock);
  229. INIT_RADIX_TREE(&srq_table->tree, GFP_ATOMIC);
  230. if (mlx4_is_slave(dev))
  231. return 0;
  232. err = mlx4_bitmap_init(&srq_table->bitmap, dev->caps.num_srqs,
  233. dev->caps.num_srqs - 1, dev->caps.reserved_srqs, 0);
  234. if (err)
  235. return err;
  236. return 0;
  237. }
  238. void mlx4_cleanup_srq_table(struct mlx4_dev *dev)
  239. {
  240. if (mlx4_is_slave(dev))
  241. return;
  242. mlx4_bitmap_cleanup(&mlx4_priv(dev)->srq_table.bitmap);
  243. }
  244. struct mlx4_srq *mlx4_srq_lookup(struct mlx4_dev *dev, u32 srqn)
  245. {
  246. struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
  247. struct mlx4_srq *srq;
  248. unsigned long flags;
  249. spin_lock_irqsave(&srq_table->lock, flags);
  250. srq = radix_tree_lookup(&srq_table->tree,
  251. srqn & (dev->caps.num_srqs - 1));
  252. spin_unlock_irqrestore(&srq_table->lock, flags);
  253. return srq;
  254. }
  255. EXPORT_SYMBOL_GPL(mlx4_srq_lookup);