core.c 36 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299
  1. /*
  2. * drivers/net/ethernet/mellanox/mlxsw/core.c
  3. * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
  4. * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
  5. * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
  6. * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
  7. *
  8. * Redistribution and use in source and binary forms, with or without
  9. * modification, are permitted provided that the following conditions are met:
  10. *
  11. * 1. Redistributions of source code must retain the above copyright
  12. * notice, this list of conditions and the following disclaimer.
  13. * 2. Redistributions in binary form must reproduce the above copyright
  14. * notice, this list of conditions and the following disclaimer in the
  15. * documentation and/or other materials provided with the distribution.
  16. * 3. Neither the names of the copyright holders nor the names of its
  17. * contributors may be used to endorse or promote products derived from
  18. * this software without specific prior written permission.
  19. *
  20. * Alternatively, this software may be distributed under the terms of the
  21. * GNU General Public License ("GPL") version 2 as published by the Free
  22. * Software Foundation.
  23. *
  24. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  27. * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  28. * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  31. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  32. * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  33. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  34. * POSSIBILITY OF SUCH DAMAGE.
  35. */
  36. #include <linux/kernel.h>
  37. #include <linux/module.h>
  38. #include <linux/device.h>
  39. #include <linux/export.h>
  40. #include <linux/err.h>
  41. #include <linux/if_link.h>
  42. #include <linux/debugfs.h>
  43. #include <linux/seq_file.h>
  44. #include <linux/u64_stats_sync.h>
  45. #include <linux/netdevice.h>
  46. #include <linux/wait.h>
  47. #include <linux/skbuff.h>
  48. #include <linux/etherdevice.h>
  49. #include <linux/types.h>
  50. #include <linux/string.h>
  51. #include <linux/gfp.h>
  52. #include <linux/random.h>
  53. #include <linux/jiffies.h>
  54. #include <linux/mutex.h>
  55. #include <linux/rcupdate.h>
  56. #include <linux/slab.h>
  57. #include <asm/byteorder.h>
  58. #include "core.h"
  59. #include "item.h"
  60. #include "cmd.h"
  61. #include "port.h"
  62. #include "trap.h"
  63. #include "emad.h"
  64. #include "reg.h"
  65. static LIST_HEAD(mlxsw_core_driver_list);
  66. static DEFINE_SPINLOCK(mlxsw_core_driver_list_lock);
  67. static const char mlxsw_core_driver_name[] = "mlxsw_core";
  68. static struct dentry *mlxsw_core_dbg_root;
  69. struct mlxsw_core_pcpu_stats {
  70. u64 trap_rx_packets[MLXSW_TRAP_ID_MAX];
  71. u64 trap_rx_bytes[MLXSW_TRAP_ID_MAX];
  72. u64 port_rx_packets[MLXSW_PORT_MAX_PORTS];
  73. u64 port_rx_bytes[MLXSW_PORT_MAX_PORTS];
  74. struct u64_stats_sync syncp;
  75. u32 trap_rx_dropped[MLXSW_TRAP_ID_MAX];
  76. u32 port_rx_dropped[MLXSW_PORT_MAX_PORTS];
  77. u32 trap_rx_invalid;
  78. u32 port_rx_invalid;
  79. };
  80. struct mlxsw_core {
  81. struct mlxsw_driver *driver;
  82. const struct mlxsw_bus *bus;
  83. void *bus_priv;
  84. const struct mlxsw_bus_info *bus_info;
  85. struct list_head rx_listener_list;
  86. struct list_head event_listener_list;
  87. struct {
  88. struct sk_buff *resp_skb;
  89. u64 tid;
  90. wait_queue_head_t wait;
  91. bool trans_active;
  92. struct mutex lock; /* One EMAD transaction at a time. */
  93. bool use_emad;
  94. } emad;
  95. struct mlxsw_core_pcpu_stats __percpu *pcpu_stats;
  96. struct dentry *dbg_dir;
  97. struct {
  98. struct debugfs_blob_wrapper vsd_blob;
  99. struct debugfs_blob_wrapper psid_blob;
  100. } dbg;
  101. unsigned long driver_priv[0];
  102. /* driver_priv has to be always the last item */
  103. };
  104. struct mlxsw_rx_listener_item {
  105. struct list_head list;
  106. struct mlxsw_rx_listener rxl;
  107. void *priv;
  108. };
  109. struct mlxsw_event_listener_item {
  110. struct list_head list;
  111. struct mlxsw_event_listener el;
  112. void *priv;
  113. };
  114. /******************
  115. * EMAD processing
  116. ******************/
  117. /* emad_eth_hdr_dmac
  118. * Destination MAC in EMAD's Ethernet header.
  119. * Must be set to 01:02:c9:00:00:01
  120. */
  121. MLXSW_ITEM_BUF(emad, eth_hdr, dmac, 0x00, 6);
  122. /* emad_eth_hdr_smac
  123. * Source MAC in EMAD's Ethernet header.
  124. * Must be set to 00:02:c9:01:02:03
  125. */
  126. MLXSW_ITEM_BUF(emad, eth_hdr, smac, 0x06, 6);
  127. /* emad_eth_hdr_ethertype
  128. * Ethertype in EMAD's Ethernet header.
  129. * Must be set to 0x8932
  130. */
  131. MLXSW_ITEM32(emad, eth_hdr, ethertype, 0x0C, 16, 16);
  132. /* emad_eth_hdr_mlx_proto
  133. * Mellanox protocol.
  134. * Must be set to 0x0.
  135. */
  136. MLXSW_ITEM32(emad, eth_hdr, mlx_proto, 0x0C, 8, 8);
  137. /* emad_eth_hdr_ver
  138. * Mellanox protocol version.
  139. * Must be set to 0x0.
  140. */
  141. MLXSW_ITEM32(emad, eth_hdr, ver, 0x0C, 4, 4);
  142. /* emad_op_tlv_type
  143. * Type of the TLV.
  144. * Must be set to 0x1 (operation TLV).
  145. */
  146. MLXSW_ITEM32(emad, op_tlv, type, 0x00, 27, 5);
  147. /* emad_op_tlv_len
  148. * Length of the operation TLV in u32.
  149. * Must be set to 0x4.
  150. */
  151. MLXSW_ITEM32(emad, op_tlv, len, 0x00, 16, 11);
  152. /* emad_op_tlv_dr
  153. * Direct route bit. Setting to 1 indicates the EMAD is a direct route
  154. * EMAD. DR TLV must follow.
  155. *
  156. * Note: Currently not supported and must not be set.
  157. */
  158. MLXSW_ITEM32(emad, op_tlv, dr, 0x00, 15, 1);
  159. /* emad_op_tlv_status
  160. * Returned status in case of EMAD response. Must be set to 0 in case
  161. * of EMAD request.
  162. * 0x0 - success
  163. * 0x1 - device is busy. Requester should retry
  164. * 0x2 - Mellanox protocol version not supported
  165. * 0x3 - unknown TLV
  166. * 0x4 - register not supported
  167. * 0x5 - operation class not supported
  168. * 0x6 - EMAD method not supported
  169. * 0x7 - bad parameter (e.g. port out of range)
  170. * 0x8 - resource not available
  171. * 0x9 - message receipt acknowledgment. Requester should retry
  172. * 0x70 - internal error
  173. */
  174. MLXSW_ITEM32(emad, op_tlv, status, 0x00, 8, 7);
  175. /* emad_op_tlv_register_id
  176. * Register ID of register within register TLV.
  177. */
  178. MLXSW_ITEM32(emad, op_tlv, register_id, 0x04, 16, 16);
  179. /* emad_op_tlv_r
  180. * Response bit. Setting to 1 indicates Response, otherwise request.
  181. */
  182. MLXSW_ITEM32(emad, op_tlv, r, 0x04, 15, 1);
  183. /* emad_op_tlv_method
  184. * EMAD method type.
  185. * 0x1 - query
  186. * 0x2 - write
  187. * 0x3 - send (currently not supported)
  188. * 0x4 - event
  189. */
  190. MLXSW_ITEM32(emad, op_tlv, method, 0x04, 8, 7);
  191. /* emad_op_tlv_class
  192. * EMAD operation class. Must be set to 0x1 (REG_ACCESS).
  193. */
  194. MLXSW_ITEM32(emad, op_tlv, class, 0x04, 0, 8);
  195. /* emad_op_tlv_tid
  196. * EMAD transaction ID. Used for pairing request and response EMADs.
  197. */
  198. MLXSW_ITEM64(emad, op_tlv, tid, 0x08, 0, 64);
  199. /* emad_reg_tlv_type
  200. * Type of the TLV.
  201. * Must be set to 0x3 (register TLV).
  202. */
  203. MLXSW_ITEM32(emad, reg_tlv, type, 0x00, 27, 5);
  204. /* emad_reg_tlv_len
  205. * Length of the operation TLV in u32.
  206. */
  207. MLXSW_ITEM32(emad, reg_tlv, len, 0x00, 16, 11);
  208. /* emad_end_tlv_type
  209. * Type of the TLV.
  210. * Must be set to 0x0 (end TLV).
  211. */
  212. MLXSW_ITEM32(emad, end_tlv, type, 0x00, 27, 5);
  213. /* emad_end_tlv_len
  214. * Length of the end TLV in u32.
  215. * Must be set to 1.
  216. */
  217. MLXSW_ITEM32(emad, end_tlv, len, 0x00, 16, 11);
  218. enum mlxsw_core_reg_access_type {
  219. MLXSW_CORE_REG_ACCESS_TYPE_QUERY,
  220. MLXSW_CORE_REG_ACCESS_TYPE_WRITE,
  221. };
  222. static inline const char *
  223. mlxsw_core_reg_access_type_str(enum mlxsw_core_reg_access_type type)
  224. {
  225. switch (type) {
  226. case MLXSW_CORE_REG_ACCESS_TYPE_QUERY:
  227. return "query";
  228. case MLXSW_CORE_REG_ACCESS_TYPE_WRITE:
  229. return "write";
  230. }
  231. BUG();
  232. }
  233. static void mlxsw_emad_pack_end_tlv(char *end_tlv)
  234. {
  235. mlxsw_emad_end_tlv_type_set(end_tlv, MLXSW_EMAD_TLV_TYPE_END);
  236. mlxsw_emad_end_tlv_len_set(end_tlv, MLXSW_EMAD_END_TLV_LEN);
  237. }
  238. static void mlxsw_emad_pack_reg_tlv(char *reg_tlv,
  239. const struct mlxsw_reg_info *reg,
  240. char *payload)
  241. {
  242. mlxsw_emad_reg_tlv_type_set(reg_tlv, MLXSW_EMAD_TLV_TYPE_REG);
  243. mlxsw_emad_reg_tlv_len_set(reg_tlv, reg->len / sizeof(u32) + 1);
  244. memcpy(reg_tlv + sizeof(u32), payload, reg->len);
  245. }
  246. static void mlxsw_emad_pack_op_tlv(char *op_tlv,
  247. const struct mlxsw_reg_info *reg,
  248. enum mlxsw_core_reg_access_type type,
  249. struct mlxsw_core *mlxsw_core)
  250. {
  251. mlxsw_emad_op_tlv_type_set(op_tlv, MLXSW_EMAD_TLV_TYPE_OP);
  252. mlxsw_emad_op_tlv_len_set(op_tlv, MLXSW_EMAD_OP_TLV_LEN);
  253. mlxsw_emad_op_tlv_dr_set(op_tlv, 0);
  254. mlxsw_emad_op_tlv_status_set(op_tlv, 0);
  255. mlxsw_emad_op_tlv_register_id_set(op_tlv, reg->id);
  256. mlxsw_emad_op_tlv_r_set(op_tlv, MLXSW_EMAD_OP_TLV_REQUEST);
  257. if (type == MLXSW_CORE_REG_ACCESS_TYPE_QUERY)
  258. mlxsw_emad_op_tlv_method_set(op_tlv,
  259. MLXSW_EMAD_OP_TLV_METHOD_QUERY);
  260. else
  261. mlxsw_emad_op_tlv_method_set(op_tlv,
  262. MLXSW_EMAD_OP_TLV_METHOD_WRITE);
  263. mlxsw_emad_op_tlv_class_set(op_tlv,
  264. MLXSW_EMAD_OP_TLV_CLASS_REG_ACCESS);
  265. mlxsw_emad_op_tlv_tid_set(op_tlv, mlxsw_core->emad.tid);
  266. }
  267. static int mlxsw_emad_construct_eth_hdr(struct sk_buff *skb)
  268. {
  269. char *eth_hdr = skb_push(skb, MLXSW_EMAD_ETH_HDR_LEN);
  270. mlxsw_emad_eth_hdr_dmac_memcpy_to(eth_hdr, MLXSW_EMAD_EH_DMAC);
  271. mlxsw_emad_eth_hdr_smac_memcpy_to(eth_hdr, MLXSW_EMAD_EH_SMAC);
  272. mlxsw_emad_eth_hdr_ethertype_set(eth_hdr, MLXSW_EMAD_EH_ETHERTYPE);
  273. mlxsw_emad_eth_hdr_mlx_proto_set(eth_hdr, MLXSW_EMAD_EH_MLX_PROTO);
  274. mlxsw_emad_eth_hdr_ver_set(eth_hdr, MLXSW_EMAD_EH_PROTO_VERSION);
  275. skb_reset_mac_header(skb);
  276. return 0;
  277. }
  278. static void mlxsw_emad_construct(struct sk_buff *skb,
  279. const struct mlxsw_reg_info *reg,
  280. char *payload,
  281. enum mlxsw_core_reg_access_type type,
  282. struct mlxsw_core *mlxsw_core)
  283. {
  284. char *buf;
  285. buf = skb_push(skb, MLXSW_EMAD_END_TLV_LEN * sizeof(u32));
  286. mlxsw_emad_pack_end_tlv(buf);
  287. buf = skb_push(skb, reg->len + sizeof(u32));
  288. mlxsw_emad_pack_reg_tlv(buf, reg, payload);
  289. buf = skb_push(skb, MLXSW_EMAD_OP_TLV_LEN * sizeof(u32));
  290. mlxsw_emad_pack_op_tlv(buf, reg, type, mlxsw_core);
  291. mlxsw_emad_construct_eth_hdr(skb);
  292. }
  293. static char *mlxsw_emad_op_tlv(const struct sk_buff *skb)
  294. {
  295. return ((char *) (skb->data + MLXSW_EMAD_ETH_HDR_LEN));
  296. }
  297. static char *mlxsw_emad_reg_tlv(const struct sk_buff *skb)
  298. {
  299. return ((char *) (skb->data + MLXSW_EMAD_ETH_HDR_LEN +
  300. MLXSW_EMAD_OP_TLV_LEN * sizeof(u32)));
  301. }
  302. static char *mlxsw_emad_reg_payload(const char *op_tlv)
  303. {
  304. return ((char *) (op_tlv + (MLXSW_EMAD_OP_TLV_LEN + 1) * sizeof(u32)));
  305. }
  306. static u64 mlxsw_emad_get_tid(const struct sk_buff *skb)
  307. {
  308. char *op_tlv;
  309. op_tlv = mlxsw_emad_op_tlv(skb);
  310. return mlxsw_emad_op_tlv_tid_get(op_tlv);
  311. }
  312. static bool mlxsw_emad_is_resp(const struct sk_buff *skb)
  313. {
  314. char *op_tlv;
  315. op_tlv = mlxsw_emad_op_tlv(skb);
  316. return (mlxsw_emad_op_tlv_r_get(op_tlv) == MLXSW_EMAD_OP_TLV_RESPONSE);
  317. }
  318. #define MLXSW_EMAD_TIMEOUT_MS 200
  319. static int __mlxsw_emad_transmit(struct mlxsw_core *mlxsw_core,
  320. struct sk_buff *skb,
  321. const struct mlxsw_tx_info *tx_info)
  322. {
  323. int err;
  324. int ret;
  325. mlxsw_core->emad.trans_active = true;
  326. err = mlxsw_core_skb_transmit(mlxsw_core->driver_priv, skb, tx_info);
  327. if (err) {
  328. dev_err(mlxsw_core->bus_info->dev, "Failed to transmit EMAD (tid=%llx)\n",
  329. mlxsw_core->emad.tid);
  330. dev_kfree_skb(skb);
  331. goto trans_inactive_out;
  332. }
  333. ret = wait_event_timeout(mlxsw_core->emad.wait,
  334. !(mlxsw_core->emad.trans_active),
  335. msecs_to_jiffies(MLXSW_EMAD_TIMEOUT_MS));
  336. if (!ret) {
  337. dev_warn(mlxsw_core->bus_info->dev, "EMAD timed-out (tid=%llx)\n",
  338. mlxsw_core->emad.tid);
  339. err = -EIO;
  340. goto trans_inactive_out;
  341. }
  342. return 0;
  343. trans_inactive_out:
  344. mlxsw_core->emad.trans_active = false;
  345. return err;
  346. }
  347. static int mlxsw_emad_process_status(struct mlxsw_core *mlxsw_core,
  348. char *op_tlv)
  349. {
  350. enum mlxsw_emad_op_tlv_status status;
  351. u64 tid;
  352. status = mlxsw_emad_op_tlv_status_get(op_tlv);
  353. tid = mlxsw_emad_op_tlv_tid_get(op_tlv);
  354. switch (status) {
  355. case MLXSW_EMAD_OP_TLV_STATUS_SUCCESS:
  356. return 0;
  357. case MLXSW_EMAD_OP_TLV_STATUS_BUSY:
  358. case MLXSW_EMAD_OP_TLV_STATUS_MESSAGE_RECEIPT_ACK:
  359. dev_warn(mlxsw_core->bus_info->dev, "Reg access status again (tid=%llx,status=%x(%s))\n",
  360. tid, status, mlxsw_emad_op_tlv_status_str(status));
  361. return -EAGAIN;
  362. case MLXSW_EMAD_OP_TLV_STATUS_VERSION_NOT_SUPPORTED:
  363. case MLXSW_EMAD_OP_TLV_STATUS_UNKNOWN_TLV:
  364. case MLXSW_EMAD_OP_TLV_STATUS_REGISTER_NOT_SUPPORTED:
  365. case MLXSW_EMAD_OP_TLV_STATUS_CLASS_NOT_SUPPORTED:
  366. case MLXSW_EMAD_OP_TLV_STATUS_METHOD_NOT_SUPPORTED:
  367. case MLXSW_EMAD_OP_TLV_STATUS_BAD_PARAMETER:
  368. case MLXSW_EMAD_OP_TLV_STATUS_RESOURCE_NOT_AVAILABLE:
  369. case MLXSW_EMAD_OP_TLV_STATUS_INTERNAL_ERROR:
  370. default:
  371. dev_err(mlxsw_core->bus_info->dev, "Reg access status failed (tid=%llx,status=%x(%s))\n",
  372. tid, status, mlxsw_emad_op_tlv_status_str(status));
  373. return -EIO;
  374. }
  375. }
  376. static int mlxsw_emad_process_status_skb(struct mlxsw_core *mlxsw_core,
  377. struct sk_buff *skb)
  378. {
  379. return mlxsw_emad_process_status(mlxsw_core, mlxsw_emad_op_tlv(skb));
  380. }
  381. static int mlxsw_emad_transmit(struct mlxsw_core *mlxsw_core,
  382. struct sk_buff *skb,
  383. const struct mlxsw_tx_info *tx_info)
  384. {
  385. struct sk_buff *trans_skb;
  386. int n_retry;
  387. int err;
  388. n_retry = 0;
  389. retry:
  390. /* We copy the EMAD to a new skb, since we might need
  391. * to retransmit it in case of failure.
  392. */
  393. trans_skb = skb_copy(skb, GFP_KERNEL);
  394. if (!trans_skb) {
  395. err = -ENOMEM;
  396. goto out;
  397. }
  398. err = __mlxsw_emad_transmit(mlxsw_core, trans_skb, tx_info);
  399. if (!err) {
  400. struct sk_buff *resp_skb = mlxsw_core->emad.resp_skb;
  401. err = mlxsw_emad_process_status_skb(mlxsw_core, resp_skb);
  402. if (err)
  403. dev_kfree_skb(resp_skb);
  404. if (!err || err != -EAGAIN)
  405. goto out;
  406. }
  407. if (n_retry++ < MLXSW_EMAD_MAX_RETRY)
  408. goto retry;
  409. out:
  410. dev_kfree_skb(skb);
  411. mlxsw_core->emad.tid++;
  412. return err;
  413. }
  414. static void mlxsw_emad_rx_listener_func(struct sk_buff *skb, u8 local_port,
  415. void *priv)
  416. {
  417. struct mlxsw_core *mlxsw_core = priv;
  418. if (mlxsw_emad_is_resp(skb) &&
  419. mlxsw_core->emad.trans_active &&
  420. mlxsw_emad_get_tid(skb) == mlxsw_core->emad.tid) {
  421. mlxsw_core->emad.resp_skb = skb;
  422. mlxsw_core->emad.trans_active = false;
  423. wake_up(&mlxsw_core->emad.wait);
  424. } else {
  425. dev_kfree_skb(skb);
  426. }
  427. }
  428. static const struct mlxsw_rx_listener mlxsw_emad_rx_listener = {
  429. .func = mlxsw_emad_rx_listener_func,
  430. .local_port = MLXSW_PORT_DONT_CARE,
  431. .trap_id = MLXSW_TRAP_ID_ETHEMAD,
  432. };
  433. static int mlxsw_emad_traps_set(struct mlxsw_core *mlxsw_core)
  434. {
  435. char htgt_pl[MLXSW_REG_HTGT_LEN];
  436. char hpkt_pl[MLXSW_REG_HPKT_LEN];
  437. int err;
  438. mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD);
  439. err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
  440. if (err)
  441. return err;
  442. mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
  443. MLXSW_TRAP_ID_ETHEMAD);
  444. return mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl);
  445. }
  446. static int mlxsw_emad_init(struct mlxsw_core *mlxsw_core)
  447. {
  448. int err;
  449. /* Set the upper 32 bits of the transaction ID field to a random
  450. * number. This allows us to discard EMADs addressed to other
  451. * devices.
  452. */
  453. get_random_bytes(&mlxsw_core->emad.tid, 4);
  454. mlxsw_core->emad.tid = mlxsw_core->emad.tid << 32;
  455. init_waitqueue_head(&mlxsw_core->emad.wait);
  456. mlxsw_core->emad.trans_active = false;
  457. mutex_init(&mlxsw_core->emad.lock);
  458. err = mlxsw_core_rx_listener_register(mlxsw_core,
  459. &mlxsw_emad_rx_listener,
  460. mlxsw_core);
  461. if (err)
  462. return err;
  463. err = mlxsw_emad_traps_set(mlxsw_core);
  464. if (err)
  465. goto err_emad_trap_set;
  466. mlxsw_core->emad.use_emad = true;
  467. return 0;
  468. err_emad_trap_set:
  469. mlxsw_core_rx_listener_unregister(mlxsw_core,
  470. &mlxsw_emad_rx_listener,
  471. mlxsw_core);
  472. return err;
  473. }
  474. static void mlxsw_emad_fini(struct mlxsw_core *mlxsw_core)
  475. {
  476. char hpkt_pl[MLXSW_REG_HPKT_LEN];
  477. mlxsw_core->emad.use_emad = false;
  478. mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_DISCARD,
  479. MLXSW_TRAP_ID_ETHEMAD);
  480. mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl);
  481. mlxsw_core_rx_listener_unregister(mlxsw_core,
  482. &mlxsw_emad_rx_listener,
  483. mlxsw_core);
  484. }
  485. static struct sk_buff *mlxsw_emad_alloc(const struct mlxsw_core *mlxsw_core,
  486. u16 reg_len)
  487. {
  488. struct sk_buff *skb;
  489. u16 emad_len;
  490. emad_len = (reg_len + sizeof(u32) + MLXSW_EMAD_ETH_HDR_LEN +
  491. (MLXSW_EMAD_OP_TLV_LEN + MLXSW_EMAD_END_TLV_LEN) *
  492. sizeof(u32) + mlxsw_core->driver->txhdr_len);
  493. if (emad_len > MLXSW_EMAD_MAX_FRAME_LEN)
  494. return NULL;
  495. skb = netdev_alloc_skb(NULL, emad_len);
  496. if (!skb)
  497. return NULL;
  498. memset(skb->data, 0, emad_len);
  499. skb_reserve(skb, emad_len);
  500. return skb;
  501. }
  502. /*****************
  503. * Core functions
  504. *****************/
  505. static int mlxsw_core_rx_stats_dbg_read(struct seq_file *file, void *data)
  506. {
  507. struct mlxsw_core *mlxsw_core = file->private;
  508. struct mlxsw_core_pcpu_stats *p;
  509. u64 rx_packets, rx_bytes;
  510. u64 tmp_rx_packets, tmp_rx_bytes;
  511. u32 rx_dropped, rx_invalid;
  512. unsigned int start;
  513. int i;
  514. int j;
  515. static const char hdr[] =
  516. " NUM RX_PACKETS RX_BYTES RX_DROPPED\n";
  517. seq_printf(file, hdr);
  518. for (i = 0; i < MLXSW_TRAP_ID_MAX; i++) {
  519. rx_packets = 0;
  520. rx_bytes = 0;
  521. rx_dropped = 0;
  522. for_each_possible_cpu(j) {
  523. p = per_cpu_ptr(mlxsw_core->pcpu_stats, j);
  524. do {
  525. start = u64_stats_fetch_begin(&p->syncp);
  526. tmp_rx_packets = p->trap_rx_packets[i];
  527. tmp_rx_bytes = p->trap_rx_bytes[i];
  528. } while (u64_stats_fetch_retry(&p->syncp, start));
  529. rx_packets += tmp_rx_packets;
  530. rx_bytes += tmp_rx_bytes;
  531. rx_dropped += p->trap_rx_dropped[i];
  532. }
  533. seq_printf(file, "trap %3d %12llu %12llu %10u\n",
  534. i, rx_packets, rx_bytes, rx_dropped);
  535. }
  536. rx_invalid = 0;
  537. for_each_possible_cpu(j) {
  538. p = per_cpu_ptr(mlxsw_core->pcpu_stats, j);
  539. rx_invalid += p->trap_rx_invalid;
  540. }
  541. seq_printf(file, "trap INV %10u\n",
  542. rx_invalid);
  543. for (i = 0; i < MLXSW_PORT_MAX_PORTS; i++) {
  544. rx_packets = 0;
  545. rx_bytes = 0;
  546. rx_dropped = 0;
  547. for_each_possible_cpu(j) {
  548. p = per_cpu_ptr(mlxsw_core->pcpu_stats, j);
  549. do {
  550. start = u64_stats_fetch_begin(&p->syncp);
  551. tmp_rx_packets = p->port_rx_packets[i];
  552. tmp_rx_bytes = p->port_rx_bytes[i];
  553. } while (u64_stats_fetch_retry(&p->syncp, start));
  554. rx_packets += tmp_rx_packets;
  555. rx_bytes += tmp_rx_bytes;
  556. rx_dropped += p->port_rx_dropped[i];
  557. }
  558. seq_printf(file, "port %3d %12llu %12llu %10u\n",
  559. i, rx_packets, rx_bytes, rx_dropped);
  560. }
  561. rx_invalid = 0;
  562. for_each_possible_cpu(j) {
  563. p = per_cpu_ptr(mlxsw_core->pcpu_stats, j);
  564. rx_invalid += p->port_rx_invalid;
  565. }
  566. seq_printf(file, "port INV %10u\n",
  567. rx_invalid);
  568. return 0;
  569. }
  570. static int mlxsw_core_rx_stats_dbg_open(struct inode *inode, struct file *f)
  571. {
  572. struct mlxsw_core *mlxsw_core = inode->i_private;
  573. return single_open(f, mlxsw_core_rx_stats_dbg_read, mlxsw_core);
  574. }
  575. static const struct file_operations mlxsw_core_rx_stats_dbg_ops = {
  576. .owner = THIS_MODULE,
  577. .open = mlxsw_core_rx_stats_dbg_open,
  578. .release = single_release,
  579. .read = seq_read,
  580. .llseek = seq_lseek
  581. };
  582. static void mlxsw_core_buf_dump_dbg(struct mlxsw_core *mlxsw_core,
  583. const char *buf, size_t size)
  584. {
  585. __be32 *m = (__be32 *) buf;
  586. int i;
  587. int count = size / sizeof(__be32);
  588. for (i = count - 1; i >= 0; i--)
  589. if (m[i])
  590. break;
  591. i++;
  592. count = i ? i : 1;
  593. for (i = 0; i < count; i += 4)
  594. dev_dbg(mlxsw_core->bus_info->dev, "%04x - %08x %08x %08x %08x\n",
  595. i * 4, be32_to_cpu(m[i]), be32_to_cpu(m[i + 1]),
  596. be32_to_cpu(m[i + 2]), be32_to_cpu(m[i + 3]));
  597. }
  598. int mlxsw_core_driver_register(struct mlxsw_driver *mlxsw_driver)
  599. {
  600. spin_lock(&mlxsw_core_driver_list_lock);
  601. list_add_tail(&mlxsw_driver->list, &mlxsw_core_driver_list);
  602. spin_unlock(&mlxsw_core_driver_list_lock);
  603. return 0;
  604. }
  605. EXPORT_SYMBOL(mlxsw_core_driver_register);
  606. void mlxsw_core_driver_unregister(struct mlxsw_driver *mlxsw_driver)
  607. {
  608. spin_lock(&mlxsw_core_driver_list_lock);
  609. list_del(&mlxsw_driver->list);
  610. spin_unlock(&mlxsw_core_driver_list_lock);
  611. }
  612. EXPORT_SYMBOL(mlxsw_core_driver_unregister);
  613. static struct mlxsw_driver *__driver_find(const char *kind)
  614. {
  615. struct mlxsw_driver *mlxsw_driver;
  616. list_for_each_entry(mlxsw_driver, &mlxsw_core_driver_list, list) {
  617. if (strcmp(mlxsw_driver->kind, kind) == 0)
  618. return mlxsw_driver;
  619. }
  620. return NULL;
  621. }
  622. static struct mlxsw_driver *mlxsw_core_driver_get(const char *kind)
  623. {
  624. struct mlxsw_driver *mlxsw_driver;
  625. spin_lock(&mlxsw_core_driver_list_lock);
  626. mlxsw_driver = __driver_find(kind);
  627. if (!mlxsw_driver) {
  628. spin_unlock(&mlxsw_core_driver_list_lock);
  629. request_module(MLXSW_MODULE_ALIAS_PREFIX "%s", kind);
  630. spin_lock(&mlxsw_core_driver_list_lock);
  631. mlxsw_driver = __driver_find(kind);
  632. }
  633. if (mlxsw_driver) {
  634. if (!try_module_get(mlxsw_driver->owner))
  635. mlxsw_driver = NULL;
  636. }
  637. spin_unlock(&mlxsw_core_driver_list_lock);
  638. return mlxsw_driver;
  639. }
  640. static void mlxsw_core_driver_put(const char *kind)
  641. {
  642. struct mlxsw_driver *mlxsw_driver;
  643. spin_lock(&mlxsw_core_driver_list_lock);
  644. mlxsw_driver = __driver_find(kind);
  645. spin_unlock(&mlxsw_core_driver_list_lock);
  646. if (!mlxsw_driver)
  647. return;
  648. module_put(mlxsw_driver->owner);
  649. }
  650. static int mlxsw_core_debugfs_init(struct mlxsw_core *mlxsw_core)
  651. {
  652. const struct mlxsw_bus_info *bus_info = mlxsw_core->bus_info;
  653. mlxsw_core->dbg_dir = debugfs_create_dir(bus_info->device_name,
  654. mlxsw_core_dbg_root);
  655. if (!mlxsw_core->dbg_dir)
  656. return -ENOMEM;
  657. debugfs_create_file("rx_stats", S_IRUGO, mlxsw_core->dbg_dir,
  658. mlxsw_core, &mlxsw_core_rx_stats_dbg_ops);
  659. mlxsw_core->dbg.vsd_blob.data = (void *) &bus_info->vsd;
  660. mlxsw_core->dbg.vsd_blob.size = sizeof(bus_info->vsd);
  661. debugfs_create_blob("vsd", S_IRUGO, mlxsw_core->dbg_dir,
  662. &mlxsw_core->dbg.vsd_blob);
  663. mlxsw_core->dbg.psid_blob.data = (void *) &bus_info->psid;
  664. mlxsw_core->dbg.psid_blob.size = sizeof(bus_info->psid);
  665. debugfs_create_blob("psid", S_IRUGO, mlxsw_core->dbg_dir,
  666. &mlxsw_core->dbg.psid_blob);
  667. return 0;
  668. }
  669. static void mlxsw_core_debugfs_fini(struct mlxsw_core *mlxsw_core)
  670. {
  671. debugfs_remove_recursive(mlxsw_core->dbg_dir);
  672. }
  673. int mlxsw_core_bus_device_register(const struct mlxsw_bus_info *mlxsw_bus_info,
  674. const struct mlxsw_bus *mlxsw_bus,
  675. void *bus_priv)
  676. {
  677. const char *device_kind = mlxsw_bus_info->device_kind;
  678. struct mlxsw_core *mlxsw_core;
  679. struct mlxsw_driver *mlxsw_driver;
  680. size_t alloc_size;
  681. int err;
  682. mlxsw_driver = mlxsw_core_driver_get(device_kind);
  683. if (!mlxsw_driver)
  684. return -EINVAL;
  685. alloc_size = sizeof(*mlxsw_core) + mlxsw_driver->priv_size;
  686. mlxsw_core = kzalloc(alloc_size, GFP_KERNEL);
  687. if (!mlxsw_core) {
  688. err = -ENOMEM;
  689. goto err_core_alloc;
  690. }
  691. INIT_LIST_HEAD(&mlxsw_core->rx_listener_list);
  692. INIT_LIST_HEAD(&mlxsw_core->event_listener_list);
  693. mlxsw_core->driver = mlxsw_driver;
  694. mlxsw_core->bus = mlxsw_bus;
  695. mlxsw_core->bus_priv = bus_priv;
  696. mlxsw_core->bus_info = mlxsw_bus_info;
  697. mlxsw_core->pcpu_stats =
  698. netdev_alloc_pcpu_stats(struct mlxsw_core_pcpu_stats);
  699. if (!mlxsw_core->pcpu_stats) {
  700. err = -ENOMEM;
  701. goto err_alloc_stats;
  702. }
  703. err = mlxsw_bus->init(bus_priv, mlxsw_core, mlxsw_driver->profile);
  704. if (err)
  705. goto err_bus_init;
  706. err = mlxsw_emad_init(mlxsw_core);
  707. if (err)
  708. goto err_emad_init;
  709. err = mlxsw_driver->init(mlxsw_core->driver_priv, mlxsw_core,
  710. mlxsw_bus_info);
  711. if (err)
  712. goto err_driver_init;
  713. err = mlxsw_core_debugfs_init(mlxsw_core);
  714. if (err)
  715. goto err_debugfs_init;
  716. return 0;
  717. err_debugfs_init:
  718. mlxsw_core->driver->fini(mlxsw_core->driver_priv);
  719. err_driver_init:
  720. mlxsw_emad_fini(mlxsw_core);
  721. err_emad_init:
  722. mlxsw_bus->fini(bus_priv);
  723. err_bus_init:
  724. free_percpu(mlxsw_core->pcpu_stats);
  725. err_alloc_stats:
  726. kfree(mlxsw_core);
  727. err_core_alloc:
  728. mlxsw_core_driver_put(device_kind);
  729. return err;
  730. }
  731. EXPORT_SYMBOL(mlxsw_core_bus_device_register);
  732. void mlxsw_core_bus_device_unregister(struct mlxsw_core *mlxsw_core)
  733. {
  734. const char *device_kind = mlxsw_core->bus_info->device_kind;
  735. mlxsw_core_debugfs_fini(mlxsw_core);
  736. mlxsw_core->driver->fini(mlxsw_core->driver_priv);
  737. mlxsw_emad_fini(mlxsw_core);
  738. mlxsw_core->bus->fini(mlxsw_core->bus_priv);
  739. free_percpu(mlxsw_core->pcpu_stats);
  740. kfree(mlxsw_core);
  741. mlxsw_core_driver_put(device_kind);
  742. }
  743. EXPORT_SYMBOL(mlxsw_core_bus_device_unregister);
  744. static struct mlxsw_core *__mlxsw_core_get(void *driver_priv)
  745. {
  746. return container_of(driver_priv, struct mlxsw_core, driver_priv);
  747. }
  748. bool mlxsw_core_skb_transmit_busy(void *driver_priv,
  749. const struct mlxsw_tx_info *tx_info)
  750. {
  751. struct mlxsw_core *mlxsw_core = __mlxsw_core_get(driver_priv);
  752. return mlxsw_core->bus->skb_transmit_busy(mlxsw_core->bus_priv,
  753. tx_info);
  754. }
  755. EXPORT_SYMBOL(mlxsw_core_skb_transmit_busy);
  756. int mlxsw_core_skb_transmit(void *driver_priv, struct sk_buff *skb,
  757. const struct mlxsw_tx_info *tx_info)
  758. {
  759. struct mlxsw_core *mlxsw_core = __mlxsw_core_get(driver_priv);
  760. return mlxsw_core->bus->skb_transmit(mlxsw_core->bus_priv, skb,
  761. tx_info);
  762. }
  763. EXPORT_SYMBOL(mlxsw_core_skb_transmit);
  764. static bool __is_rx_listener_equal(const struct mlxsw_rx_listener *rxl_a,
  765. const struct mlxsw_rx_listener *rxl_b)
  766. {
  767. return (rxl_a->func == rxl_b->func &&
  768. rxl_a->local_port == rxl_b->local_port &&
  769. rxl_a->trap_id == rxl_b->trap_id);
  770. }
  771. static struct mlxsw_rx_listener_item *
  772. __find_rx_listener_item(struct mlxsw_core *mlxsw_core,
  773. const struct mlxsw_rx_listener *rxl,
  774. void *priv)
  775. {
  776. struct mlxsw_rx_listener_item *rxl_item;
  777. list_for_each_entry(rxl_item, &mlxsw_core->rx_listener_list, list) {
  778. if (__is_rx_listener_equal(&rxl_item->rxl, rxl) &&
  779. rxl_item->priv == priv)
  780. return rxl_item;
  781. }
  782. return NULL;
  783. }
  784. int mlxsw_core_rx_listener_register(struct mlxsw_core *mlxsw_core,
  785. const struct mlxsw_rx_listener *rxl,
  786. void *priv)
  787. {
  788. struct mlxsw_rx_listener_item *rxl_item;
  789. rxl_item = __find_rx_listener_item(mlxsw_core, rxl, priv);
  790. if (rxl_item)
  791. return -EEXIST;
  792. rxl_item = kmalloc(sizeof(*rxl_item), GFP_KERNEL);
  793. if (!rxl_item)
  794. return -ENOMEM;
  795. rxl_item->rxl = *rxl;
  796. rxl_item->priv = priv;
  797. list_add_rcu(&rxl_item->list, &mlxsw_core->rx_listener_list);
  798. return 0;
  799. }
  800. EXPORT_SYMBOL(mlxsw_core_rx_listener_register);
  801. void mlxsw_core_rx_listener_unregister(struct mlxsw_core *mlxsw_core,
  802. const struct mlxsw_rx_listener *rxl,
  803. void *priv)
  804. {
  805. struct mlxsw_rx_listener_item *rxl_item;
  806. rxl_item = __find_rx_listener_item(mlxsw_core, rxl, priv);
  807. if (!rxl_item)
  808. return;
  809. list_del_rcu(&rxl_item->list);
  810. synchronize_rcu();
  811. kfree(rxl_item);
  812. }
  813. EXPORT_SYMBOL(mlxsw_core_rx_listener_unregister);
  814. static void mlxsw_core_event_listener_func(struct sk_buff *skb, u8 local_port,
  815. void *priv)
  816. {
  817. struct mlxsw_event_listener_item *event_listener_item = priv;
  818. struct mlxsw_reg_info reg;
  819. char *payload;
  820. char *op_tlv = mlxsw_emad_op_tlv(skb);
  821. char *reg_tlv = mlxsw_emad_reg_tlv(skb);
  822. reg.id = mlxsw_emad_op_tlv_register_id_get(op_tlv);
  823. reg.len = (mlxsw_emad_reg_tlv_len_get(reg_tlv) - 1) * sizeof(u32);
  824. payload = mlxsw_emad_reg_payload(op_tlv);
  825. event_listener_item->el.func(&reg, payload, event_listener_item->priv);
  826. dev_kfree_skb(skb);
  827. }
  828. static bool __is_event_listener_equal(const struct mlxsw_event_listener *el_a,
  829. const struct mlxsw_event_listener *el_b)
  830. {
  831. return (el_a->func == el_b->func &&
  832. el_a->trap_id == el_b->trap_id);
  833. }
  834. static struct mlxsw_event_listener_item *
  835. __find_event_listener_item(struct mlxsw_core *mlxsw_core,
  836. const struct mlxsw_event_listener *el,
  837. void *priv)
  838. {
  839. struct mlxsw_event_listener_item *el_item;
  840. list_for_each_entry(el_item, &mlxsw_core->event_listener_list, list) {
  841. if (__is_event_listener_equal(&el_item->el, el) &&
  842. el_item->priv == priv)
  843. return el_item;
  844. }
  845. return NULL;
  846. }
  847. int mlxsw_core_event_listener_register(struct mlxsw_core *mlxsw_core,
  848. const struct mlxsw_event_listener *el,
  849. void *priv)
  850. {
  851. int err;
  852. struct mlxsw_event_listener_item *el_item;
  853. const struct mlxsw_rx_listener rxl = {
  854. .func = mlxsw_core_event_listener_func,
  855. .local_port = MLXSW_PORT_DONT_CARE,
  856. .trap_id = el->trap_id,
  857. };
  858. el_item = __find_event_listener_item(mlxsw_core, el, priv);
  859. if (el_item)
  860. return -EEXIST;
  861. el_item = kmalloc(sizeof(*el_item), GFP_KERNEL);
  862. if (!el_item)
  863. return -ENOMEM;
  864. el_item->el = *el;
  865. el_item->priv = priv;
  866. err = mlxsw_core_rx_listener_register(mlxsw_core, &rxl, el_item);
  867. if (err)
  868. goto err_rx_listener_register;
  869. /* No reason to save item if we did not manage to register an RX
  870. * listener for it.
  871. */
  872. list_add_rcu(&el_item->list, &mlxsw_core->event_listener_list);
  873. return 0;
  874. err_rx_listener_register:
  875. kfree(el_item);
  876. return err;
  877. }
  878. EXPORT_SYMBOL(mlxsw_core_event_listener_register);
  879. void mlxsw_core_event_listener_unregister(struct mlxsw_core *mlxsw_core,
  880. const struct mlxsw_event_listener *el,
  881. void *priv)
  882. {
  883. struct mlxsw_event_listener_item *el_item;
  884. const struct mlxsw_rx_listener rxl = {
  885. .func = mlxsw_core_event_listener_func,
  886. .local_port = MLXSW_PORT_DONT_CARE,
  887. .trap_id = el->trap_id,
  888. };
  889. el_item = __find_event_listener_item(mlxsw_core, el, priv);
  890. if (!el_item)
  891. return;
  892. mlxsw_core_rx_listener_unregister(mlxsw_core, &rxl, el_item);
  893. list_del(&el_item->list);
  894. kfree(el_item);
  895. }
  896. EXPORT_SYMBOL(mlxsw_core_event_listener_unregister);
  897. static int mlxsw_core_reg_access_emad(struct mlxsw_core *mlxsw_core,
  898. const struct mlxsw_reg_info *reg,
  899. char *payload,
  900. enum mlxsw_core_reg_access_type type)
  901. {
  902. int err;
  903. char *op_tlv;
  904. struct sk_buff *skb;
  905. struct mlxsw_tx_info tx_info = {
  906. .local_port = MLXSW_PORT_CPU_PORT,
  907. .is_emad = true,
  908. };
  909. skb = mlxsw_emad_alloc(mlxsw_core, reg->len);
  910. if (!skb)
  911. return -ENOMEM;
  912. mlxsw_emad_construct(skb, reg, payload, type, mlxsw_core);
  913. mlxsw_core->driver->txhdr_construct(skb, &tx_info);
  914. dev_dbg(mlxsw_core->bus_info->dev, "EMAD send (tid=%llx)\n",
  915. mlxsw_core->emad.tid);
  916. mlxsw_core_buf_dump_dbg(mlxsw_core, skb->data, skb->len);
  917. err = mlxsw_emad_transmit(mlxsw_core, skb, &tx_info);
  918. if (!err) {
  919. op_tlv = mlxsw_emad_op_tlv(mlxsw_core->emad.resp_skb);
  920. memcpy(payload, mlxsw_emad_reg_payload(op_tlv),
  921. reg->len);
  922. dev_dbg(mlxsw_core->bus_info->dev, "EMAD recv (tid=%llx)\n",
  923. mlxsw_core->emad.tid - 1);
  924. mlxsw_core_buf_dump_dbg(mlxsw_core,
  925. mlxsw_core->emad.resp_skb->data,
  926. mlxsw_core->emad.resp_skb->len);
  927. dev_kfree_skb(mlxsw_core->emad.resp_skb);
  928. }
  929. return err;
  930. }
  931. static int mlxsw_core_reg_access_cmd(struct mlxsw_core *mlxsw_core,
  932. const struct mlxsw_reg_info *reg,
  933. char *payload,
  934. enum mlxsw_core_reg_access_type type)
  935. {
  936. int err, n_retry;
  937. char *in_mbox, *out_mbox, *tmp;
  938. in_mbox = mlxsw_cmd_mbox_alloc();
  939. if (!in_mbox)
  940. return -ENOMEM;
  941. out_mbox = mlxsw_cmd_mbox_alloc();
  942. if (!out_mbox) {
  943. err = -ENOMEM;
  944. goto free_in_mbox;
  945. }
  946. mlxsw_emad_pack_op_tlv(in_mbox, reg, type, mlxsw_core);
  947. tmp = in_mbox + MLXSW_EMAD_OP_TLV_LEN * sizeof(u32);
  948. mlxsw_emad_pack_reg_tlv(tmp, reg, payload);
  949. n_retry = 0;
  950. retry:
  951. err = mlxsw_cmd_access_reg(mlxsw_core, in_mbox, out_mbox);
  952. if (!err) {
  953. err = mlxsw_emad_process_status(mlxsw_core, out_mbox);
  954. if (err == -EAGAIN && n_retry++ < MLXSW_EMAD_MAX_RETRY)
  955. goto retry;
  956. }
  957. if (!err)
  958. memcpy(payload, mlxsw_emad_reg_payload(out_mbox),
  959. reg->len);
  960. mlxsw_core->emad.tid++;
  961. mlxsw_cmd_mbox_free(out_mbox);
  962. free_in_mbox:
  963. mlxsw_cmd_mbox_free(in_mbox);
  964. return err;
  965. }
  966. static int mlxsw_core_reg_access(struct mlxsw_core *mlxsw_core,
  967. const struct mlxsw_reg_info *reg,
  968. char *payload,
  969. enum mlxsw_core_reg_access_type type)
  970. {
  971. u64 cur_tid;
  972. int err;
  973. if (mutex_lock_interruptible(&mlxsw_core->emad.lock)) {
  974. dev_err(mlxsw_core->bus_info->dev, "Reg access interrupted (reg_id=%x(%s),type=%s)\n",
  975. reg->id, mlxsw_reg_id_str(reg->id),
  976. mlxsw_core_reg_access_type_str(type));
  977. return -EINTR;
  978. }
  979. cur_tid = mlxsw_core->emad.tid;
  980. dev_dbg(mlxsw_core->bus_info->dev, "Reg access (tid=%llx,reg_id=%x(%s),type=%s)\n",
  981. cur_tid, reg->id, mlxsw_reg_id_str(reg->id),
  982. mlxsw_core_reg_access_type_str(type));
  983. /* During initialization EMAD interface is not available to us,
  984. * so we default to command interface. We switch to EMAD interface
  985. * after setting the appropriate traps.
  986. */
  987. if (!mlxsw_core->emad.use_emad)
  988. err = mlxsw_core_reg_access_cmd(mlxsw_core, reg,
  989. payload, type);
  990. else
  991. err = mlxsw_core_reg_access_emad(mlxsw_core, reg,
  992. payload, type);
  993. if (err)
  994. dev_err(mlxsw_core->bus_info->dev, "Reg access failed (tid=%llx,reg_id=%x(%s),type=%s)\n",
  995. cur_tid, reg->id, mlxsw_reg_id_str(reg->id),
  996. mlxsw_core_reg_access_type_str(type));
  997. mutex_unlock(&mlxsw_core->emad.lock);
  998. return err;
  999. }
  1000. int mlxsw_reg_query(struct mlxsw_core *mlxsw_core,
  1001. const struct mlxsw_reg_info *reg, char *payload)
  1002. {
  1003. return mlxsw_core_reg_access(mlxsw_core, reg, payload,
  1004. MLXSW_CORE_REG_ACCESS_TYPE_QUERY);
  1005. }
  1006. EXPORT_SYMBOL(mlxsw_reg_query);
  1007. int mlxsw_reg_write(struct mlxsw_core *mlxsw_core,
  1008. const struct mlxsw_reg_info *reg, char *payload)
  1009. {
  1010. return mlxsw_core_reg_access(mlxsw_core, reg, payload,
  1011. MLXSW_CORE_REG_ACCESS_TYPE_WRITE);
  1012. }
  1013. EXPORT_SYMBOL(mlxsw_reg_write);
  1014. void mlxsw_core_skb_receive(struct mlxsw_core *mlxsw_core, struct sk_buff *skb,
  1015. struct mlxsw_rx_info *rx_info)
  1016. {
  1017. struct mlxsw_rx_listener_item *rxl_item;
  1018. const struct mlxsw_rx_listener *rxl;
  1019. struct mlxsw_core_pcpu_stats *pcpu_stats;
  1020. u8 local_port = rx_info->sys_port;
  1021. bool found = false;
  1022. dev_dbg_ratelimited(mlxsw_core->bus_info->dev, "%s: sys_port = %d, trap_id = 0x%x\n",
  1023. __func__, rx_info->sys_port, rx_info->trap_id);
  1024. if ((rx_info->trap_id >= MLXSW_TRAP_ID_MAX) ||
  1025. (local_port >= MLXSW_PORT_MAX_PORTS))
  1026. goto drop;
  1027. rcu_read_lock();
  1028. list_for_each_entry_rcu(rxl_item, &mlxsw_core->rx_listener_list, list) {
  1029. rxl = &rxl_item->rxl;
  1030. if ((rxl->local_port == MLXSW_PORT_DONT_CARE ||
  1031. rxl->local_port == local_port) &&
  1032. rxl->trap_id == rx_info->trap_id) {
  1033. found = true;
  1034. break;
  1035. }
  1036. }
  1037. rcu_read_unlock();
  1038. if (!found)
  1039. goto drop;
  1040. pcpu_stats = this_cpu_ptr(mlxsw_core->pcpu_stats);
  1041. u64_stats_update_begin(&pcpu_stats->syncp);
  1042. pcpu_stats->port_rx_packets[local_port]++;
  1043. pcpu_stats->port_rx_bytes[local_port] += skb->len;
  1044. pcpu_stats->trap_rx_packets[rx_info->trap_id]++;
  1045. pcpu_stats->trap_rx_bytes[rx_info->trap_id] += skb->len;
  1046. u64_stats_update_end(&pcpu_stats->syncp);
  1047. rxl->func(skb, local_port, rxl_item->priv);
  1048. return;
  1049. drop:
  1050. if (rx_info->trap_id >= MLXSW_TRAP_ID_MAX)
  1051. this_cpu_inc(mlxsw_core->pcpu_stats->trap_rx_invalid);
  1052. else
  1053. this_cpu_inc(mlxsw_core->pcpu_stats->trap_rx_dropped[rx_info->trap_id]);
  1054. if (local_port >= MLXSW_PORT_MAX_PORTS)
  1055. this_cpu_inc(mlxsw_core->pcpu_stats->port_rx_invalid);
  1056. else
  1057. this_cpu_inc(mlxsw_core->pcpu_stats->port_rx_dropped[local_port]);
  1058. dev_kfree_skb(skb);
  1059. }
  1060. EXPORT_SYMBOL(mlxsw_core_skb_receive);
  1061. int mlxsw_cmd_exec(struct mlxsw_core *mlxsw_core, u16 opcode, u8 opcode_mod,
  1062. u32 in_mod, bool out_mbox_direct,
  1063. char *in_mbox, size_t in_mbox_size,
  1064. char *out_mbox, size_t out_mbox_size)
  1065. {
  1066. u8 status;
  1067. int err;
  1068. BUG_ON(in_mbox_size % sizeof(u32) || out_mbox_size % sizeof(u32));
  1069. if (!mlxsw_core->bus->cmd_exec)
  1070. return -EOPNOTSUPP;
  1071. dev_dbg(mlxsw_core->bus_info->dev, "Cmd exec (opcode=%x(%s),opcode_mod=%x,in_mod=%x)\n",
  1072. opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, in_mod);
  1073. if (in_mbox) {
  1074. dev_dbg(mlxsw_core->bus_info->dev, "Input mailbox:\n");
  1075. mlxsw_core_buf_dump_dbg(mlxsw_core, in_mbox, in_mbox_size);
  1076. }
  1077. err = mlxsw_core->bus->cmd_exec(mlxsw_core->bus_priv, opcode,
  1078. opcode_mod, in_mod, out_mbox_direct,
  1079. in_mbox, in_mbox_size,
  1080. out_mbox, out_mbox_size, &status);
  1081. if (err == -EIO && status != MLXSW_CMD_STATUS_OK) {
  1082. dev_err(mlxsw_core->bus_info->dev, "Cmd exec failed (opcode=%x(%s),opcode_mod=%x,in_mod=%x,status=%x(%s))\n",
  1083. opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod,
  1084. in_mod, status, mlxsw_cmd_status_str(status));
  1085. } else if (err == -ETIMEDOUT) {
  1086. dev_err(mlxsw_core->bus_info->dev, "Cmd exec timed-out (opcode=%x(%s),opcode_mod=%x,in_mod=%x)\n",
  1087. opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod,
  1088. in_mod);
  1089. }
  1090. if (!err && out_mbox) {
  1091. dev_dbg(mlxsw_core->bus_info->dev, "Output mailbox:\n");
  1092. mlxsw_core_buf_dump_dbg(mlxsw_core, out_mbox, out_mbox_size);
  1093. }
  1094. return err;
  1095. }
  1096. EXPORT_SYMBOL(mlxsw_cmd_exec);
  1097. static int __init mlxsw_core_module_init(void)
  1098. {
  1099. mlxsw_core_dbg_root = debugfs_create_dir(mlxsw_core_driver_name, NULL);
  1100. if (!mlxsw_core_dbg_root)
  1101. return -ENOMEM;
  1102. return 0;
  1103. }
  1104. static void __exit mlxsw_core_module_exit(void)
  1105. {
  1106. debugfs_remove_recursive(mlxsw_core_dbg_root);
  1107. }
  1108. module_init(mlxsw_core_module_init);
  1109. module_exit(mlxsw_core_module_exit);
  1110. MODULE_LICENSE("Dual BSD/GPL");
  1111. MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
  1112. MODULE_DESCRIPTION("Mellanox switch device core driver");