pch_gbe_api.c 6.7 KB

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  1. /*
  2. * Copyright (C) 1999 - 2010 Intel Corporation.
  3. * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
  4. *
  5. * This code was derived from the Intel e1000e Linux driver.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; version 2 of the License.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include "pch_gbe.h"
  20. #include "pch_gbe_phy.h"
  21. #include "pch_gbe_api.h"
  22. /* bus type values */
  23. #define pch_gbe_bus_type_unknown 0
  24. #define pch_gbe_bus_type_pci 1
  25. #define pch_gbe_bus_type_pcix 2
  26. #define pch_gbe_bus_type_pci_express 3
  27. #define pch_gbe_bus_type_reserved 4
  28. /* bus speed values */
  29. #define pch_gbe_bus_speed_unknown 0
  30. #define pch_gbe_bus_speed_33 1
  31. #define pch_gbe_bus_speed_66 2
  32. #define pch_gbe_bus_speed_100 3
  33. #define pch_gbe_bus_speed_120 4
  34. #define pch_gbe_bus_speed_133 5
  35. #define pch_gbe_bus_speed_2500 6
  36. #define pch_gbe_bus_speed_reserved 7
  37. /* bus width values */
  38. #define pch_gbe_bus_width_unknown 0
  39. #define pch_gbe_bus_width_pcie_x1 1
  40. #define pch_gbe_bus_width_pcie_x2 2
  41. #define pch_gbe_bus_width_pcie_x4 4
  42. #define pch_gbe_bus_width_32 5
  43. #define pch_gbe_bus_width_64 6
  44. #define pch_gbe_bus_width_reserved 7
  45. /**
  46. * pch_gbe_plat_get_bus_info - Obtain bus information for adapter
  47. * @hw: Pointer to the HW structure
  48. */
  49. static void pch_gbe_plat_get_bus_info(struct pch_gbe_hw *hw)
  50. {
  51. hw->bus.type = pch_gbe_bus_type_pci_express;
  52. hw->bus.speed = pch_gbe_bus_speed_2500;
  53. hw->bus.width = pch_gbe_bus_width_pcie_x1;
  54. }
  55. /**
  56. * pch_gbe_plat_init_hw - Initialize hardware
  57. * @hw: Pointer to the HW structure
  58. * Returns:
  59. * 0: Successfully
  60. * Negative value: Failed-EBUSY
  61. */
  62. static s32 pch_gbe_plat_init_hw(struct pch_gbe_hw *hw)
  63. {
  64. s32 ret_val;
  65. ret_val = pch_gbe_phy_get_id(hw);
  66. if (ret_val) {
  67. struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
  68. netdev_err(adapter->netdev, "pch_gbe_phy_get_id error\n");
  69. return ret_val;
  70. }
  71. pch_gbe_phy_init_setting(hw);
  72. /* Setup Mac interface option RGMII */
  73. #ifdef PCH_GBE_MAC_IFOP_RGMII
  74. pch_gbe_phy_set_rgmii(hw);
  75. #endif
  76. return ret_val;
  77. }
  78. static const struct pch_gbe_functions pch_gbe_ops = {
  79. .get_bus_info = pch_gbe_plat_get_bus_info,
  80. .init_hw = pch_gbe_plat_init_hw,
  81. .read_phy_reg = pch_gbe_phy_read_reg_miic,
  82. .write_phy_reg = pch_gbe_phy_write_reg_miic,
  83. .reset_phy = pch_gbe_phy_hw_reset,
  84. .sw_reset_phy = pch_gbe_phy_sw_reset,
  85. .power_up_phy = pch_gbe_phy_power_up,
  86. .power_down_phy = pch_gbe_phy_power_down,
  87. .read_mac_addr = pch_gbe_mac_read_mac_addr
  88. };
  89. /**
  90. * pch_gbe_plat_init_function_pointers - Init func ptrs
  91. * @hw: Pointer to the HW structure
  92. */
  93. static void pch_gbe_plat_init_function_pointers(struct pch_gbe_hw *hw)
  94. {
  95. /* Set PHY parameter */
  96. hw->phy.reset_delay_us = PCH_GBE_PHY_RESET_DELAY_US;
  97. /* Set function pointers */
  98. hw->func = &pch_gbe_ops;
  99. }
  100. /**
  101. * pch_gbe_hal_setup_init_funcs - Initializes function pointers
  102. * @hw: Pointer to the HW structure
  103. * Returns:
  104. * 0: Successfully
  105. * ENOSYS: Function is not registered
  106. */
  107. s32 pch_gbe_hal_setup_init_funcs(struct pch_gbe_hw *hw)
  108. {
  109. if (!hw->reg) {
  110. struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
  111. netdev_err(adapter->netdev, "ERROR: Registers not mapped\n");
  112. return -ENOSYS;
  113. }
  114. pch_gbe_plat_init_function_pointers(hw);
  115. return 0;
  116. }
  117. /**
  118. * pch_gbe_hal_get_bus_info - Obtain bus information for adapter
  119. * @hw: Pointer to the HW structure
  120. */
  121. void pch_gbe_hal_get_bus_info(struct pch_gbe_hw *hw)
  122. {
  123. if (!hw->func->get_bus_info) {
  124. struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
  125. netdev_err(adapter->netdev, "ERROR: configuration\n");
  126. return;
  127. }
  128. hw->func->get_bus_info(hw);
  129. }
  130. /**
  131. * pch_gbe_hal_init_hw - Initialize hardware
  132. * @hw: Pointer to the HW structure
  133. * Returns:
  134. * 0: Successfully
  135. * ENOSYS: Function is not registered
  136. */
  137. s32 pch_gbe_hal_init_hw(struct pch_gbe_hw *hw)
  138. {
  139. if (!hw->func->init_hw) {
  140. struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
  141. netdev_err(adapter->netdev, "ERROR: configuration\n");
  142. return -ENOSYS;
  143. }
  144. return hw->func->init_hw(hw);
  145. }
  146. /**
  147. * pch_gbe_hal_read_phy_reg - Reads PHY register
  148. * @hw: Pointer to the HW structure
  149. * @offset: The register to read
  150. * @data: The buffer to store the 16-bit read.
  151. * Returns:
  152. * 0: Successfully
  153. * Negative value: Failed
  154. */
  155. s32 pch_gbe_hal_read_phy_reg(struct pch_gbe_hw *hw, u32 offset,
  156. u16 *data)
  157. {
  158. if (!hw->func->read_phy_reg)
  159. return 0;
  160. return hw->func->read_phy_reg(hw, offset, data);
  161. }
  162. /**
  163. * pch_gbe_hal_write_phy_reg - Writes PHY register
  164. * @hw: Pointer to the HW structure
  165. * @offset: The register to read
  166. * @data: The value to write.
  167. * Returns:
  168. * 0: Successfully
  169. * Negative value: Failed
  170. */
  171. s32 pch_gbe_hal_write_phy_reg(struct pch_gbe_hw *hw, u32 offset,
  172. u16 data)
  173. {
  174. if (!hw->func->write_phy_reg)
  175. return 0;
  176. return hw->func->write_phy_reg(hw, offset, data);
  177. }
  178. /**
  179. * pch_gbe_hal_phy_hw_reset - Hard PHY reset
  180. * @hw: Pointer to the HW structure
  181. */
  182. void pch_gbe_hal_phy_hw_reset(struct pch_gbe_hw *hw)
  183. {
  184. if (!hw->func->reset_phy) {
  185. struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
  186. netdev_err(adapter->netdev, "ERROR: configuration\n");
  187. return;
  188. }
  189. hw->func->reset_phy(hw);
  190. }
  191. /**
  192. * pch_gbe_hal_phy_sw_reset - Soft PHY reset
  193. * @hw: Pointer to the HW structure
  194. */
  195. void pch_gbe_hal_phy_sw_reset(struct pch_gbe_hw *hw)
  196. {
  197. if (!hw->func->sw_reset_phy) {
  198. struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
  199. netdev_err(adapter->netdev, "ERROR: configuration\n");
  200. return;
  201. }
  202. hw->func->sw_reset_phy(hw);
  203. }
  204. /**
  205. * pch_gbe_hal_read_mac_addr - Reads MAC address
  206. * @hw: Pointer to the HW structure
  207. * Returns:
  208. * 0: Successfully
  209. * ENOSYS: Function is not registered
  210. */
  211. s32 pch_gbe_hal_read_mac_addr(struct pch_gbe_hw *hw)
  212. {
  213. if (!hw->func->read_mac_addr) {
  214. struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
  215. netdev_err(adapter->netdev, "ERROR: configuration\n");
  216. return -ENOSYS;
  217. }
  218. return hw->func->read_mac_addr(hw);
  219. }
  220. /**
  221. * pch_gbe_hal_power_up_phy - Power up PHY
  222. * @hw: Pointer to the HW structure
  223. */
  224. void pch_gbe_hal_power_up_phy(struct pch_gbe_hw *hw)
  225. {
  226. if (hw->func->power_up_phy)
  227. hw->func->power_up_phy(hw);
  228. }
  229. /**
  230. * pch_gbe_hal_power_down_phy - Power down PHY
  231. * @hw: Pointer to the HW structure
  232. */
  233. void pch_gbe_hal_power_down_phy(struct pch_gbe_hw *hw)
  234. {
  235. if (hw->func->power_down_phy)
  236. hw->func->power_down_phy(hw);
  237. }