netxen_nic_init.c 46 KB

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  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * Copyright (C) 2009 - QLogic Corporation.
  4. * All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18. *
  19. * The full GNU General Public License is included in this distribution
  20. * in the file called "COPYING".
  21. *
  22. */
  23. #include <linux/netdevice.h>
  24. #include <linux/delay.h>
  25. #include <linux/slab.h>
  26. #include <linux/if_vlan.h>
  27. #include <net/checksum.h>
  28. #include "netxen_nic.h"
  29. #include "netxen_nic_hw.h"
  30. struct crb_addr_pair {
  31. u32 addr;
  32. u32 data;
  33. };
  34. #define NETXEN_MAX_CRB_XFORM 60
  35. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  36. #define NETXEN_ADDR_ERROR (0xffffffff)
  37. #define crb_addr_transform(name) \
  38. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  39. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  40. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  41. static void
  42. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  43. struct nx_host_rds_ring *rds_ring);
  44. static int netxen_p3_has_mn(struct netxen_adapter *adapter);
  45. static void crb_addr_transform_setup(void)
  46. {
  47. crb_addr_transform(XDMA);
  48. crb_addr_transform(TIMR);
  49. crb_addr_transform(SRE);
  50. crb_addr_transform(SQN3);
  51. crb_addr_transform(SQN2);
  52. crb_addr_transform(SQN1);
  53. crb_addr_transform(SQN0);
  54. crb_addr_transform(SQS3);
  55. crb_addr_transform(SQS2);
  56. crb_addr_transform(SQS1);
  57. crb_addr_transform(SQS0);
  58. crb_addr_transform(RPMX7);
  59. crb_addr_transform(RPMX6);
  60. crb_addr_transform(RPMX5);
  61. crb_addr_transform(RPMX4);
  62. crb_addr_transform(RPMX3);
  63. crb_addr_transform(RPMX2);
  64. crb_addr_transform(RPMX1);
  65. crb_addr_transform(RPMX0);
  66. crb_addr_transform(ROMUSB);
  67. crb_addr_transform(SN);
  68. crb_addr_transform(QMN);
  69. crb_addr_transform(QMS);
  70. crb_addr_transform(PGNI);
  71. crb_addr_transform(PGND);
  72. crb_addr_transform(PGN3);
  73. crb_addr_transform(PGN2);
  74. crb_addr_transform(PGN1);
  75. crb_addr_transform(PGN0);
  76. crb_addr_transform(PGSI);
  77. crb_addr_transform(PGSD);
  78. crb_addr_transform(PGS3);
  79. crb_addr_transform(PGS2);
  80. crb_addr_transform(PGS1);
  81. crb_addr_transform(PGS0);
  82. crb_addr_transform(PS);
  83. crb_addr_transform(PH);
  84. crb_addr_transform(NIU);
  85. crb_addr_transform(I2Q);
  86. crb_addr_transform(EG);
  87. crb_addr_transform(MN);
  88. crb_addr_transform(MS);
  89. crb_addr_transform(CAS2);
  90. crb_addr_transform(CAS1);
  91. crb_addr_transform(CAS0);
  92. crb_addr_transform(CAM);
  93. crb_addr_transform(C2C1);
  94. crb_addr_transform(C2C0);
  95. crb_addr_transform(SMB);
  96. crb_addr_transform(OCM0);
  97. crb_addr_transform(I2C0);
  98. }
  99. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  100. {
  101. struct netxen_recv_context *recv_ctx;
  102. struct nx_host_rds_ring *rds_ring;
  103. struct netxen_rx_buffer *rx_buf;
  104. int i, ring;
  105. recv_ctx = &adapter->recv_ctx;
  106. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  107. rds_ring = &recv_ctx->rds_rings[ring];
  108. for (i = 0; i < rds_ring->num_desc; ++i) {
  109. rx_buf = &(rds_ring->rx_buf_arr[i]);
  110. if (rx_buf->state == NETXEN_BUFFER_FREE)
  111. continue;
  112. pci_unmap_single(adapter->pdev,
  113. rx_buf->dma,
  114. rds_ring->dma_size,
  115. PCI_DMA_FROMDEVICE);
  116. if (rx_buf->skb != NULL)
  117. dev_kfree_skb_any(rx_buf->skb);
  118. }
  119. }
  120. }
  121. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  122. {
  123. struct netxen_cmd_buffer *cmd_buf;
  124. struct netxen_skb_frag *buffrag;
  125. int i, j;
  126. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  127. spin_lock_bh(&adapter->tx_clean_lock);
  128. cmd_buf = tx_ring->cmd_buf_arr;
  129. for (i = 0; i < tx_ring->num_desc; i++) {
  130. buffrag = cmd_buf->frag_array;
  131. if (buffrag->dma) {
  132. pci_unmap_single(adapter->pdev, buffrag->dma,
  133. buffrag->length, PCI_DMA_TODEVICE);
  134. buffrag->dma = 0ULL;
  135. }
  136. for (j = 1; j < cmd_buf->frag_count; j++) {
  137. buffrag++;
  138. if (buffrag->dma) {
  139. pci_unmap_page(adapter->pdev, buffrag->dma,
  140. buffrag->length,
  141. PCI_DMA_TODEVICE);
  142. buffrag->dma = 0ULL;
  143. }
  144. }
  145. if (cmd_buf->skb) {
  146. dev_kfree_skb_any(cmd_buf->skb);
  147. cmd_buf->skb = NULL;
  148. }
  149. cmd_buf++;
  150. }
  151. spin_unlock_bh(&adapter->tx_clean_lock);
  152. }
  153. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  154. {
  155. struct netxen_recv_context *recv_ctx;
  156. struct nx_host_rds_ring *rds_ring;
  157. struct nx_host_tx_ring *tx_ring;
  158. int ring;
  159. recv_ctx = &adapter->recv_ctx;
  160. if (recv_ctx->rds_rings == NULL)
  161. goto skip_rds;
  162. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  163. rds_ring = &recv_ctx->rds_rings[ring];
  164. vfree(rds_ring->rx_buf_arr);
  165. rds_ring->rx_buf_arr = NULL;
  166. }
  167. kfree(recv_ctx->rds_rings);
  168. skip_rds:
  169. if (adapter->tx_ring == NULL)
  170. return;
  171. tx_ring = adapter->tx_ring;
  172. vfree(tx_ring->cmd_buf_arr);
  173. kfree(tx_ring);
  174. adapter->tx_ring = NULL;
  175. }
  176. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  177. {
  178. struct netxen_recv_context *recv_ctx;
  179. struct nx_host_rds_ring *rds_ring;
  180. struct nx_host_sds_ring *sds_ring;
  181. struct nx_host_tx_ring *tx_ring;
  182. struct netxen_rx_buffer *rx_buf;
  183. int ring, i;
  184. struct netxen_cmd_buffer *cmd_buf_arr;
  185. struct net_device *netdev = adapter->netdev;
  186. tx_ring = kzalloc(sizeof(struct nx_host_tx_ring), GFP_KERNEL);
  187. if (tx_ring == NULL)
  188. return -ENOMEM;
  189. adapter->tx_ring = tx_ring;
  190. tx_ring->num_desc = adapter->num_txd;
  191. tx_ring->txq = netdev_get_tx_queue(netdev, 0);
  192. cmd_buf_arr = vzalloc(TX_BUFF_RINGSIZE(tx_ring));
  193. if (cmd_buf_arr == NULL)
  194. goto err_out;
  195. tx_ring->cmd_buf_arr = cmd_buf_arr;
  196. recv_ctx = &adapter->recv_ctx;
  197. rds_ring = kcalloc(adapter->max_rds_rings,
  198. sizeof(struct nx_host_rds_ring), GFP_KERNEL);
  199. if (rds_ring == NULL)
  200. goto err_out;
  201. recv_ctx->rds_rings = rds_ring;
  202. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  203. rds_ring = &recv_ctx->rds_rings[ring];
  204. switch (ring) {
  205. case RCV_RING_NORMAL:
  206. rds_ring->num_desc = adapter->num_rxd;
  207. if (adapter->ahw.cut_through) {
  208. rds_ring->dma_size =
  209. NX_CT_DEFAULT_RX_BUF_LEN;
  210. rds_ring->skb_size =
  211. NX_CT_DEFAULT_RX_BUF_LEN;
  212. } else {
  213. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  214. rds_ring->dma_size =
  215. NX_P3_RX_BUF_MAX_LEN;
  216. else
  217. rds_ring->dma_size =
  218. NX_P2_RX_BUF_MAX_LEN;
  219. rds_ring->skb_size =
  220. rds_ring->dma_size + NET_IP_ALIGN;
  221. }
  222. break;
  223. case RCV_RING_JUMBO:
  224. rds_ring->num_desc = adapter->num_jumbo_rxd;
  225. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  226. rds_ring->dma_size =
  227. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  228. else
  229. rds_ring->dma_size =
  230. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  231. if (adapter->capabilities & NX_CAP0_HW_LRO)
  232. rds_ring->dma_size += NX_LRO_BUFFER_EXTRA;
  233. rds_ring->skb_size =
  234. rds_ring->dma_size + NET_IP_ALIGN;
  235. break;
  236. case RCV_RING_LRO:
  237. rds_ring->num_desc = adapter->num_lro_rxd;
  238. rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
  239. rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
  240. break;
  241. }
  242. rds_ring->rx_buf_arr = vzalloc(RCV_BUFF_RINGSIZE(rds_ring));
  243. if (rds_ring->rx_buf_arr == NULL)
  244. /* free whatever was already allocated */
  245. goto err_out;
  246. INIT_LIST_HEAD(&rds_ring->free_list);
  247. /*
  248. * Now go through all of them, set reference handles
  249. * and put them in the queues.
  250. */
  251. rx_buf = rds_ring->rx_buf_arr;
  252. for (i = 0; i < rds_ring->num_desc; i++) {
  253. list_add_tail(&rx_buf->list,
  254. &rds_ring->free_list);
  255. rx_buf->ref_handle = i;
  256. rx_buf->state = NETXEN_BUFFER_FREE;
  257. rx_buf++;
  258. }
  259. spin_lock_init(&rds_ring->lock);
  260. }
  261. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  262. sds_ring = &recv_ctx->sds_rings[ring];
  263. sds_ring->irq = adapter->msix_entries[ring].vector;
  264. sds_ring->adapter = adapter;
  265. sds_ring->num_desc = adapter->num_rxd;
  266. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  267. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  268. }
  269. return 0;
  270. err_out:
  271. netxen_free_sw_resources(adapter);
  272. return -ENOMEM;
  273. }
  274. /*
  275. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  276. * address to external PCI CRB address.
  277. */
  278. static u32 netxen_decode_crb_addr(u32 addr)
  279. {
  280. int i;
  281. u32 base_addr, offset, pci_base;
  282. crb_addr_transform_setup();
  283. pci_base = NETXEN_ADDR_ERROR;
  284. base_addr = addr & 0xfff00000;
  285. offset = addr & 0x000fffff;
  286. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  287. if (crb_addr_xform[i] == base_addr) {
  288. pci_base = i << 20;
  289. break;
  290. }
  291. }
  292. if (pci_base == NETXEN_ADDR_ERROR)
  293. return pci_base;
  294. else
  295. return pci_base + offset;
  296. }
  297. #define NETXEN_MAX_ROM_WAIT_USEC 100
  298. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  299. {
  300. long timeout = 0;
  301. long done = 0;
  302. cond_resched();
  303. while (done == 0) {
  304. done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
  305. done &= 2;
  306. if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) {
  307. dev_err(&adapter->pdev->dev,
  308. "Timeout reached waiting for rom done");
  309. return -EIO;
  310. }
  311. udelay(1);
  312. }
  313. return 0;
  314. }
  315. static int do_rom_fast_read(struct netxen_adapter *adapter,
  316. int addr, int *valp)
  317. {
  318. NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  319. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  320. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  321. NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  322. if (netxen_wait_rom_done(adapter)) {
  323. printk("Error waiting for rom done\n");
  324. return -EIO;
  325. }
  326. /* reset abyte_cnt and dummy_byte_cnt */
  327. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  328. udelay(10);
  329. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  330. *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
  331. return 0;
  332. }
  333. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  334. u8 *bytes, size_t size)
  335. {
  336. int addridx;
  337. int ret = 0;
  338. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  339. int v;
  340. ret = do_rom_fast_read(adapter, addridx, &v);
  341. if (ret != 0)
  342. break;
  343. *(__le32 *)bytes = cpu_to_le32(v);
  344. bytes += 4;
  345. }
  346. return ret;
  347. }
  348. int
  349. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  350. u8 *bytes, size_t size)
  351. {
  352. int ret;
  353. ret = netxen_rom_lock(adapter);
  354. if (ret < 0)
  355. return ret;
  356. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  357. netxen_rom_unlock(adapter);
  358. return ret;
  359. }
  360. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  361. {
  362. int ret;
  363. if (netxen_rom_lock(adapter) != 0)
  364. return -EIO;
  365. ret = do_rom_fast_read(adapter, addr, valp);
  366. netxen_rom_unlock(adapter);
  367. return ret;
  368. }
  369. #define NETXEN_BOARDTYPE 0x4008
  370. #define NETXEN_BOARDNUM 0x400c
  371. #define NETXEN_CHIPNUM 0x4010
  372. int netxen_pinit_from_rom(struct netxen_adapter *adapter)
  373. {
  374. int addr, val;
  375. int i, n, init_delay = 0;
  376. struct crb_addr_pair *buf;
  377. unsigned offset;
  378. u32 off;
  379. /* resetall */
  380. netxen_rom_lock(adapter);
  381. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xfeffffff);
  382. netxen_rom_unlock(adapter);
  383. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  384. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  385. (n != 0xcafecafe) ||
  386. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  387. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  388. "n: %08x\n", netxen_nic_driver_name, n);
  389. return -EIO;
  390. }
  391. offset = n & 0xffffU;
  392. n = (n >> 16) & 0xffffU;
  393. } else {
  394. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  395. !(n & 0x80000000)) {
  396. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  397. "n: %08x\n", netxen_nic_driver_name, n);
  398. return -EIO;
  399. }
  400. offset = 1;
  401. n &= ~0x80000000;
  402. }
  403. if (n >= 1024) {
  404. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  405. " initialized.\n", __func__, n);
  406. return -EIO;
  407. }
  408. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  409. if (buf == NULL)
  410. return -ENOMEM;
  411. for (i = 0; i < n; i++) {
  412. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  413. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  414. kfree(buf);
  415. return -EIO;
  416. }
  417. buf[i].addr = addr;
  418. buf[i].data = val;
  419. }
  420. for (i = 0; i < n; i++) {
  421. off = netxen_decode_crb_addr(buf[i].addr);
  422. if (off == NETXEN_ADDR_ERROR) {
  423. printk(KERN_ERR"CRB init value out of range %x\n",
  424. buf[i].addr);
  425. continue;
  426. }
  427. off += NETXEN_PCI_CRBSPACE;
  428. if (off & 1)
  429. continue;
  430. /* skipping cold reboot MAGIC */
  431. if (off == NETXEN_CAM_RAM(0x1fc))
  432. continue;
  433. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  434. if (off == (NETXEN_CRB_I2C0 + 0x1c))
  435. continue;
  436. /* do not reset PCI */
  437. if (off == (ROMUSB_GLB + 0xbc))
  438. continue;
  439. if (off == (ROMUSB_GLB + 0xa8))
  440. continue;
  441. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  442. continue;
  443. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  444. continue;
  445. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  446. continue;
  447. if ((off & 0x0ff00000) == NETXEN_CRB_DDR_NET)
  448. continue;
  449. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18) &&
  450. !NX_IS_REVISION_P3P(adapter->ahw.revision_id))
  451. buf[i].data = 0x1020;
  452. /* skip the function enable register */
  453. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  454. continue;
  455. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  456. continue;
  457. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  458. continue;
  459. }
  460. init_delay = 1;
  461. /* After writing this register, HW needs time for CRB */
  462. /* to quiet down (else crb_window returns 0xffffffff) */
  463. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  464. init_delay = 1000;
  465. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  466. /* hold xdma in reset also */
  467. buf[i].data = NETXEN_NIC_XDMA_RESET;
  468. buf[i].data = 0x8000ff;
  469. }
  470. }
  471. NXWR32(adapter, off, buf[i].data);
  472. msleep(init_delay);
  473. }
  474. kfree(buf);
  475. /* disable_peg_cache_all */
  476. /* unreset_net_cache */
  477. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  478. val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
  479. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  480. }
  481. /* p2dn replyCount */
  482. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  483. /* disable_peg_cache 0 */
  484. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  485. /* disable_peg_cache 1 */
  486. NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  487. /* peg_clr_all */
  488. /* peg_clr 0 */
  489. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  490. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  491. /* peg_clr 1 */
  492. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  493. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  494. /* peg_clr 2 */
  495. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  496. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  497. /* peg_clr 3 */
  498. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  499. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  500. return 0;
  501. }
  502. static struct uni_table_desc *nx_get_table_desc(const u8 *unirom, int section)
  503. {
  504. uint32_t i;
  505. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  506. __le32 entries = cpu_to_le32(directory->num_entries);
  507. for (i = 0; i < entries; i++) {
  508. __le32 offs = cpu_to_le32(directory->findex) +
  509. (i * cpu_to_le32(directory->entry_size));
  510. __le32 tab_type = cpu_to_le32(*((u32 *)&unirom[offs] + 8));
  511. if (tab_type == section)
  512. return (struct uni_table_desc *) &unirom[offs];
  513. }
  514. return NULL;
  515. }
  516. #define QLCNIC_FILEHEADER_SIZE (14 * 4)
  517. static int
  518. netxen_nic_validate_header(struct netxen_adapter *adapter)
  519. {
  520. const u8 *unirom = adapter->fw->data;
  521. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  522. u32 fw_file_size = adapter->fw->size;
  523. u32 tab_size;
  524. __le32 entries;
  525. __le32 entry_size;
  526. if (fw_file_size < QLCNIC_FILEHEADER_SIZE)
  527. return -EINVAL;
  528. entries = cpu_to_le32(directory->num_entries);
  529. entry_size = cpu_to_le32(directory->entry_size);
  530. tab_size = cpu_to_le32(directory->findex) + (entries * entry_size);
  531. if (fw_file_size < tab_size)
  532. return -EINVAL;
  533. return 0;
  534. }
  535. static int
  536. netxen_nic_validate_bootld(struct netxen_adapter *adapter)
  537. {
  538. struct uni_table_desc *tab_desc;
  539. struct uni_data_desc *descr;
  540. const u8 *unirom = adapter->fw->data;
  541. __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  542. NX_UNI_BOOTLD_IDX_OFF));
  543. u32 offs;
  544. u32 tab_size;
  545. u32 data_size;
  546. tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_BOOTLD);
  547. if (!tab_desc)
  548. return -EINVAL;
  549. tab_size = cpu_to_le32(tab_desc->findex) +
  550. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  551. if (adapter->fw->size < tab_size)
  552. return -EINVAL;
  553. offs = cpu_to_le32(tab_desc->findex) +
  554. (cpu_to_le32(tab_desc->entry_size) * (idx));
  555. descr = (struct uni_data_desc *)&unirom[offs];
  556. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  557. if (adapter->fw->size < data_size)
  558. return -EINVAL;
  559. return 0;
  560. }
  561. static int
  562. netxen_nic_validate_fw(struct netxen_adapter *adapter)
  563. {
  564. struct uni_table_desc *tab_desc;
  565. struct uni_data_desc *descr;
  566. const u8 *unirom = adapter->fw->data;
  567. __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  568. NX_UNI_FIRMWARE_IDX_OFF));
  569. u32 offs;
  570. u32 tab_size;
  571. u32 data_size;
  572. tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_FW);
  573. if (!tab_desc)
  574. return -EINVAL;
  575. tab_size = cpu_to_le32(tab_desc->findex) +
  576. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  577. if (adapter->fw->size < tab_size)
  578. return -EINVAL;
  579. offs = cpu_to_le32(tab_desc->findex) +
  580. (cpu_to_le32(tab_desc->entry_size) * (idx));
  581. descr = (struct uni_data_desc *)&unirom[offs];
  582. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  583. if (adapter->fw->size < data_size)
  584. return -EINVAL;
  585. return 0;
  586. }
  587. static int
  588. netxen_nic_validate_product_offs(struct netxen_adapter *adapter)
  589. {
  590. struct uni_table_desc *ptab_descr;
  591. const u8 *unirom = adapter->fw->data;
  592. int mn_present = (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ?
  593. 1 : netxen_p3_has_mn(adapter);
  594. __le32 entries;
  595. __le32 entry_size;
  596. u32 tab_size;
  597. u32 i;
  598. ptab_descr = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_PRODUCT_TBL);
  599. if (ptab_descr == NULL)
  600. return -EINVAL;
  601. entries = cpu_to_le32(ptab_descr->num_entries);
  602. entry_size = cpu_to_le32(ptab_descr->entry_size);
  603. tab_size = cpu_to_le32(ptab_descr->findex) + (entries * entry_size);
  604. if (adapter->fw->size < tab_size)
  605. return -EINVAL;
  606. nomn:
  607. for (i = 0; i < entries; i++) {
  608. __le32 flags, file_chiprev, offs;
  609. u8 chiprev = adapter->ahw.revision_id;
  610. uint32_t flagbit;
  611. offs = cpu_to_le32(ptab_descr->findex) +
  612. (i * cpu_to_le32(ptab_descr->entry_size));
  613. flags = cpu_to_le32(*((int *)&unirom[offs] + NX_UNI_FLAGS_OFF));
  614. file_chiprev = cpu_to_le32(*((int *)&unirom[offs] +
  615. NX_UNI_CHIP_REV_OFF));
  616. flagbit = mn_present ? 1 : 2;
  617. if ((chiprev == file_chiprev) &&
  618. ((1ULL << flagbit) & flags)) {
  619. adapter->file_prd_off = offs;
  620. return 0;
  621. }
  622. }
  623. if (mn_present && NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  624. mn_present = 0;
  625. goto nomn;
  626. }
  627. return -EINVAL;
  628. }
  629. static int
  630. netxen_nic_validate_unified_romimage(struct netxen_adapter *adapter)
  631. {
  632. if (netxen_nic_validate_header(adapter)) {
  633. dev_err(&adapter->pdev->dev,
  634. "unified image: header validation failed\n");
  635. return -EINVAL;
  636. }
  637. if (netxen_nic_validate_product_offs(adapter)) {
  638. dev_err(&adapter->pdev->dev,
  639. "unified image: product validation failed\n");
  640. return -EINVAL;
  641. }
  642. if (netxen_nic_validate_bootld(adapter)) {
  643. dev_err(&adapter->pdev->dev,
  644. "unified image: bootld validation failed\n");
  645. return -EINVAL;
  646. }
  647. if (netxen_nic_validate_fw(adapter)) {
  648. dev_err(&adapter->pdev->dev,
  649. "unified image: firmware validation failed\n");
  650. return -EINVAL;
  651. }
  652. return 0;
  653. }
  654. static struct uni_data_desc *nx_get_data_desc(struct netxen_adapter *adapter,
  655. u32 section, u32 idx_offset)
  656. {
  657. const u8 *unirom = adapter->fw->data;
  658. int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  659. idx_offset));
  660. struct uni_table_desc *tab_desc;
  661. __le32 offs;
  662. tab_desc = nx_get_table_desc(unirom, section);
  663. if (tab_desc == NULL)
  664. return NULL;
  665. offs = cpu_to_le32(tab_desc->findex) +
  666. (cpu_to_le32(tab_desc->entry_size) * idx);
  667. return (struct uni_data_desc *)&unirom[offs];
  668. }
  669. static u8 *
  670. nx_get_bootld_offs(struct netxen_adapter *adapter)
  671. {
  672. u32 offs = NETXEN_BOOTLD_START;
  673. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  674. offs = cpu_to_le32((nx_get_data_desc(adapter,
  675. NX_UNI_DIR_SECT_BOOTLD,
  676. NX_UNI_BOOTLD_IDX_OFF))->findex);
  677. return (u8 *)&adapter->fw->data[offs];
  678. }
  679. static u8 *
  680. nx_get_fw_offs(struct netxen_adapter *adapter)
  681. {
  682. u32 offs = NETXEN_IMAGE_START;
  683. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  684. offs = cpu_to_le32((nx_get_data_desc(adapter,
  685. NX_UNI_DIR_SECT_FW,
  686. NX_UNI_FIRMWARE_IDX_OFF))->findex);
  687. return (u8 *)&adapter->fw->data[offs];
  688. }
  689. static __le32
  690. nx_get_fw_size(struct netxen_adapter *adapter)
  691. {
  692. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  693. return cpu_to_le32((nx_get_data_desc(adapter,
  694. NX_UNI_DIR_SECT_FW,
  695. NX_UNI_FIRMWARE_IDX_OFF))->size);
  696. else
  697. return cpu_to_le32(
  698. *(u32 *)&adapter->fw->data[NX_FW_SIZE_OFFSET]);
  699. }
  700. static __le32
  701. nx_get_fw_version(struct netxen_adapter *adapter)
  702. {
  703. struct uni_data_desc *fw_data_desc;
  704. const struct firmware *fw = adapter->fw;
  705. __le32 major, minor, sub;
  706. const u8 *ver_str;
  707. int i, ret = 0;
  708. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
  709. fw_data_desc = nx_get_data_desc(adapter,
  710. NX_UNI_DIR_SECT_FW, NX_UNI_FIRMWARE_IDX_OFF);
  711. ver_str = fw->data + cpu_to_le32(fw_data_desc->findex) +
  712. cpu_to_le32(fw_data_desc->size) - 17;
  713. for (i = 0; i < 12; i++) {
  714. if (!strncmp(&ver_str[i], "REV=", 4)) {
  715. ret = sscanf(&ver_str[i+4], "%u.%u.%u ",
  716. &major, &minor, &sub);
  717. break;
  718. }
  719. }
  720. if (ret != 3)
  721. return 0;
  722. return major + (minor << 8) + (sub << 16);
  723. } else
  724. return cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  725. }
  726. static __le32
  727. nx_get_bios_version(struct netxen_adapter *adapter)
  728. {
  729. const struct firmware *fw = adapter->fw;
  730. __le32 bios_ver, prd_off = adapter->file_prd_off;
  731. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
  732. bios_ver = cpu_to_le32(*((u32 *) (&fw->data[prd_off])
  733. + NX_UNI_BIOS_VERSION_OFF));
  734. return (bios_ver << 16) + ((bios_ver >> 8) & 0xff00) +
  735. (bios_ver >> 24);
  736. } else
  737. return cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
  738. }
  739. int
  740. netxen_need_fw_reset(struct netxen_adapter *adapter)
  741. {
  742. u32 count, old_count;
  743. u32 val, version, major, minor, build;
  744. int i, timeout;
  745. u8 fw_type;
  746. /* NX2031 firmware doesn't support heartbit */
  747. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  748. return 1;
  749. if (adapter->need_fw_reset)
  750. return 1;
  751. /* last attempt had failed */
  752. if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
  753. return 1;
  754. old_count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  755. for (i = 0; i < 10; i++) {
  756. timeout = msleep_interruptible(200);
  757. if (timeout) {
  758. NXWR32(adapter, CRB_CMDPEG_STATE,
  759. PHAN_INITIALIZE_FAILED);
  760. return -EINTR;
  761. }
  762. count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  763. if (count != old_count)
  764. break;
  765. }
  766. /* firmware is dead */
  767. if (count == old_count)
  768. return 1;
  769. /* check if we have got newer or different file firmware */
  770. if (adapter->fw) {
  771. val = nx_get_fw_version(adapter);
  772. version = NETXEN_DECODE_VERSION(val);
  773. major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
  774. minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
  775. build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
  776. if (version > NETXEN_VERSION_CODE(major, minor, build))
  777. return 1;
  778. if (version == NETXEN_VERSION_CODE(major, minor, build) &&
  779. adapter->fw_type != NX_UNIFIED_ROMIMAGE) {
  780. val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
  781. fw_type = (val & 0x4) ?
  782. NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
  783. if (adapter->fw_type != fw_type)
  784. return 1;
  785. }
  786. }
  787. return 0;
  788. }
  789. #define NETXEN_MIN_P3_FW_SUPP NETXEN_VERSION_CODE(4, 0, 505)
  790. int
  791. netxen_check_flash_fw_compatibility(struct netxen_adapter *adapter)
  792. {
  793. u32 flash_fw_ver, min_fw_ver;
  794. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  795. return 0;
  796. if (netxen_rom_fast_read(adapter,
  797. NX_FW_VERSION_OFFSET, (int *)&flash_fw_ver)) {
  798. dev_err(&adapter->pdev->dev, "Unable to read flash fw"
  799. "version\n");
  800. return -EIO;
  801. }
  802. flash_fw_ver = NETXEN_DECODE_VERSION(flash_fw_ver);
  803. min_fw_ver = NETXEN_MIN_P3_FW_SUPP;
  804. if (flash_fw_ver >= min_fw_ver)
  805. return 0;
  806. dev_info(&adapter->pdev->dev, "Flash fw[%d.%d.%d] is < min fw supported"
  807. "[4.0.505]. Please update firmware on flash\n",
  808. _major(flash_fw_ver), _minor(flash_fw_ver),
  809. _build(flash_fw_ver));
  810. return -EINVAL;
  811. }
  812. static char *fw_name[] = {
  813. NX_P2_MN_ROMIMAGE_NAME,
  814. NX_P3_CT_ROMIMAGE_NAME,
  815. NX_P3_MN_ROMIMAGE_NAME,
  816. NX_UNIFIED_ROMIMAGE_NAME,
  817. NX_FLASH_ROMIMAGE_NAME,
  818. };
  819. int
  820. netxen_load_firmware(struct netxen_adapter *adapter)
  821. {
  822. u64 *ptr64;
  823. u32 i, flashaddr, size;
  824. const struct firmware *fw = adapter->fw;
  825. struct pci_dev *pdev = adapter->pdev;
  826. dev_info(&pdev->dev, "loading firmware from %s\n",
  827. fw_name[adapter->fw_type]);
  828. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  829. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
  830. if (fw) {
  831. __le64 data;
  832. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  833. ptr64 = (u64 *)nx_get_bootld_offs(adapter);
  834. flashaddr = NETXEN_BOOTLD_START;
  835. for (i = 0; i < size; i++) {
  836. data = cpu_to_le64(ptr64[i]);
  837. if (adapter->pci_mem_write(adapter, flashaddr, data))
  838. return -EIO;
  839. flashaddr += 8;
  840. }
  841. size = (__force u32)nx_get_fw_size(adapter) / 8;
  842. ptr64 = (u64 *)nx_get_fw_offs(adapter);
  843. flashaddr = NETXEN_IMAGE_START;
  844. for (i = 0; i < size; i++) {
  845. data = cpu_to_le64(ptr64[i]);
  846. if (adapter->pci_mem_write(adapter,
  847. flashaddr, data))
  848. return -EIO;
  849. flashaddr += 8;
  850. }
  851. size = (__force u32)nx_get_fw_size(adapter) % 8;
  852. if (size) {
  853. data = cpu_to_le64(ptr64[i]);
  854. if (adapter->pci_mem_write(adapter,
  855. flashaddr, data))
  856. return -EIO;
  857. }
  858. } else {
  859. u64 data;
  860. u32 hi, lo;
  861. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  862. flashaddr = NETXEN_BOOTLD_START;
  863. for (i = 0; i < size; i++) {
  864. if (netxen_rom_fast_read(adapter,
  865. flashaddr, (int *)&lo) != 0)
  866. return -EIO;
  867. if (netxen_rom_fast_read(adapter,
  868. flashaddr + 4, (int *)&hi) != 0)
  869. return -EIO;
  870. /* hi, lo are already in host endian byteorder */
  871. data = (((u64)hi << 32) | lo);
  872. if (adapter->pci_mem_write(adapter,
  873. flashaddr, data))
  874. return -EIO;
  875. flashaddr += 8;
  876. }
  877. }
  878. msleep(1);
  879. if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) {
  880. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x18, 0x1020);
  881. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001e);
  882. } else if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  883. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
  884. else {
  885. NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
  886. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
  887. }
  888. return 0;
  889. }
  890. static int
  891. netxen_validate_firmware(struct netxen_adapter *adapter)
  892. {
  893. __le32 val;
  894. __le32 flash_fw_ver;
  895. u32 file_fw_ver, min_ver, bios;
  896. struct pci_dev *pdev = adapter->pdev;
  897. const struct firmware *fw = adapter->fw;
  898. u8 fw_type = adapter->fw_type;
  899. u32 crbinit_fix_fw;
  900. if (fw_type == NX_UNIFIED_ROMIMAGE) {
  901. if (netxen_nic_validate_unified_romimage(adapter))
  902. return -EINVAL;
  903. } else {
  904. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
  905. if ((__force u32)val != NETXEN_BDINFO_MAGIC)
  906. return -EINVAL;
  907. if (fw->size < NX_FW_MIN_SIZE)
  908. return -EINVAL;
  909. }
  910. val = nx_get_fw_version(adapter);
  911. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  912. min_ver = NETXEN_MIN_P3_FW_SUPP;
  913. else
  914. min_ver = NETXEN_VERSION_CODE(3, 4, 216);
  915. file_fw_ver = NETXEN_DECODE_VERSION(val);
  916. if ((_major(file_fw_ver) > _NETXEN_NIC_LINUX_MAJOR) ||
  917. (file_fw_ver < min_ver)) {
  918. dev_err(&pdev->dev,
  919. "%s: firmware version %d.%d.%d unsupported\n",
  920. fw_name[fw_type], _major(file_fw_ver), _minor(file_fw_ver),
  921. _build(file_fw_ver));
  922. return -EINVAL;
  923. }
  924. val = nx_get_bios_version(adapter);
  925. netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
  926. if ((__force u32)val != bios) {
  927. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  928. fw_name[fw_type]);
  929. return -EINVAL;
  930. }
  931. if (netxen_rom_fast_read(adapter,
  932. NX_FW_VERSION_OFFSET, (int *)&flash_fw_ver)) {
  933. dev_err(&pdev->dev, "Unable to read flash fw version\n");
  934. return -EIO;
  935. }
  936. flash_fw_ver = NETXEN_DECODE_VERSION(flash_fw_ver);
  937. /* New fw from file is not allowed, if fw on flash is < 4.0.554 */
  938. crbinit_fix_fw = NETXEN_VERSION_CODE(4, 0, 554);
  939. if (file_fw_ver >= crbinit_fix_fw && flash_fw_ver < crbinit_fix_fw &&
  940. NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  941. dev_err(&pdev->dev, "Incompatibility detected between driver "
  942. "and firmware version on flash. This configuration "
  943. "is not recommended. Please update the firmware on "
  944. "flash immediately\n");
  945. return -EINVAL;
  946. }
  947. /* check if flashed firmware is newer only for no-mn and P2 case*/
  948. if (!netxen_p3_has_mn(adapter) ||
  949. NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  950. if (flash_fw_ver > file_fw_ver) {
  951. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  952. fw_name[fw_type]);
  953. return -EINVAL;
  954. }
  955. }
  956. NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
  957. return 0;
  958. }
  959. static void
  960. nx_get_next_fwtype(struct netxen_adapter *adapter)
  961. {
  962. u8 fw_type;
  963. switch (adapter->fw_type) {
  964. case NX_UNKNOWN_ROMIMAGE:
  965. fw_type = NX_UNIFIED_ROMIMAGE;
  966. break;
  967. case NX_UNIFIED_ROMIMAGE:
  968. if (NX_IS_REVISION_P3P(adapter->ahw.revision_id))
  969. fw_type = NX_FLASH_ROMIMAGE;
  970. else if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  971. fw_type = NX_P2_MN_ROMIMAGE;
  972. else if (netxen_p3_has_mn(adapter))
  973. fw_type = NX_P3_MN_ROMIMAGE;
  974. else
  975. fw_type = NX_P3_CT_ROMIMAGE;
  976. break;
  977. case NX_P3_MN_ROMIMAGE:
  978. fw_type = NX_P3_CT_ROMIMAGE;
  979. break;
  980. case NX_P2_MN_ROMIMAGE:
  981. case NX_P3_CT_ROMIMAGE:
  982. default:
  983. fw_type = NX_FLASH_ROMIMAGE;
  984. break;
  985. }
  986. adapter->fw_type = fw_type;
  987. }
  988. static int
  989. netxen_p3_has_mn(struct netxen_adapter *adapter)
  990. {
  991. u32 capability, flashed_ver;
  992. capability = 0;
  993. /* NX2031 always had MN */
  994. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  995. return 1;
  996. netxen_rom_fast_read(adapter,
  997. NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
  998. flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
  999. if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
  1000. capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
  1001. if (capability & NX_PEG_TUNE_MN_PRESENT)
  1002. return 1;
  1003. }
  1004. return 0;
  1005. }
  1006. void netxen_request_firmware(struct netxen_adapter *adapter)
  1007. {
  1008. struct pci_dev *pdev = adapter->pdev;
  1009. int rc = 0;
  1010. adapter->fw_type = NX_UNKNOWN_ROMIMAGE;
  1011. next:
  1012. nx_get_next_fwtype(adapter);
  1013. if (adapter->fw_type == NX_FLASH_ROMIMAGE) {
  1014. adapter->fw = NULL;
  1015. } else {
  1016. rc = request_firmware(&adapter->fw,
  1017. fw_name[adapter->fw_type], &pdev->dev);
  1018. if (rc != 0)
  1019. goto next;
  1020. rc = netxen_validate_firmware(adapter);
  1021. if (rc != 0) {
  1022. release_firmware(adapter->fw);
  1023. msleep(1);
  1024. goto next;
  1025. }
  1026. }
  1027. }
  1028. void
  1029. netxen_release_firmware(struct netxen_adapter *adapter)
  1030. {
  1031. release_firmware(adapter->fw);
  1032. adapter->fw = NULL;
  1033. }
  1034. int netxen_init_dummy_dma(struct netxen_adapter *adapter)
  1035. {
  1036. u64 addr;
  1037. u32 hi, lo;
  1038. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1039. return 0;
  1040. adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
  1041. NETXEN_HOST_DUMMY_DMA_SIZE,
  1042. &adapter->dummy_dma.phys_addr);
  1043. if (adapter->dummy_dma.addr == NULL) {
  1044. dev_err(&adapter->pdev->dev,
  1045. "ERROR: Could not allocate dummy DMA memory\n");
  1046. return -ENOMEM;
  1047. }
  1048. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  1049. hi = (addr >> 32) & 0xffffffff;
  1050. lo = addr & 0xffffffff;
  1051. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  1052. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  1053. return 0;
  1054. }
  1055. /*
  1056. * NetXen DMA watchdog control:
  1057. *
  1058. * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
  1059. * Bit 1 : disable_request => 1 req disable dma watchdog
  1060. * Bit 2 : enable_request => 1 req enable dma watchdog
  1061. * Bit 3-31 : unused
  1062. */
  1063. void netxen_free_dummy_dma(struct netxen_adapter *adapter)
  1064. {
  1065. int i = 100;
  1066. u32 ctrl;
  1067. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1068. return;
  1069. if (!adapter->dummy_dma.addr)
  1070. return;
  1071. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  1072. if ((ctrl & 0x1) != 0) {
  1073. NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
  1074. while ((ctrl & 0x1) != 0) {
  1075. msleep(50);
  1076. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  1077. if (--i == 0)
  1078. break;
  1079. }
  1080. }
  1081. if (i) {
  1082. pci_free_consistent(adapter->pdev,
  1083. NETXEN_HOST_DUMMY_DMA_SIZE,
  1084. adapter->dummy_dma.addr,
  1085. adapter->dummy_dma.phys_addr);
  1086. adapter->dummy_dma.addr = NULL;
  1087. } else
  1088. dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
  1089. }
  1090. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  1091. {
  1092. u32 val = 0;
  1093. int retries = 60;
  1094. if (pegtune_val)
  1095. return 0;
  1096. do {
  1097. val = NXRD32(adapter, CRB_CMDPEG_STATE);
  1098. switch (val) {
  1099. case PHAN_INITIALIZE_COMPLETE:
  1100. case PHAN_INITIALIZE_ACK:
  1101. return 0;
  1102. case PHAN_INITIALIZE_FAILED:
  1103. goto out_err;
  1104. default:
  1105. break;
  1106. }
  1107. msleep(500);
  1108. } while (--retries);
  1109. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
  1110. out_err:
  1111. dev_warn(&adapter->pdev->dev, "firmware init failed\n");
  1112. return -EIO;
  1113. }
  1114. static int
  1115. netxen_receive_peg_ready(struct netxen_adapter *adapter)
  1116. {
  1117. u32 val = 0;
  1118. int retries = 2000;
  1119. do {
  1120. val = NXRD32(adapter, CRB_RCVPEG_STATE);
  1121. if (val == PHAN_PEG_RCV_INITIALIZED)
  1122. return 0;
  1123. msleep(10);
  1124. } while (--retries);
  1125. if (!retries) {
  1126. printk(KERN_ERR "Receive Peg initialization not "
  1127. "complete, state: 0x%x.\n", val);
  1128. return -EIO;
  1129. }
  1130. return 0;
  1131. }
  1132. int netxen_init_firmware(struct netxen_adapter *adapter)
  1133. {
  1134. int err;
  1135. err = netxen_receive_peg_ready(adapter);
  1136. if (err)
  1137. return err;
  1138. NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  1139. NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  1140. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  1141. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1142. NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  1143. return err;
  1144. }
  1145. static void
  1146. netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
  1147. {
  1148. u32 cable_OUI;
  1149. u16 cable_len;
  1150. u16 link_speed;
  1151. u8 link_status, module, duplex, autoneg;
  1152. struct net_device *netdev = adapter->netdev;
  1153. adapter->has_link_events = 1;
  1154. cable_OUI = msg->body[1] & 0xffffffff;
  1155. cable_len = (msg->body[1] >> 32) & 0xffff;
  1156. link_speed = (msg->body[1] >> 48) & 0xffff;
  1157. link_status = msg->body[2] & 0xff;
  1158. duplex = (msg->body[2] >> 16) & 0xff;
  1159. autoneg = (msg->body[2] >> 24) & 0xff;
  1160. module = (msg->body[2] >> 8) & 0xff;
  1161. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
  1162. printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
  1163. netdev->name, cable_OUI, cable_len);
  1164. } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
  1165. printk(KERN_INFO "%s: unsupported cable length %d\n",
  1166. netdev->name, cable_len);
  1167. }
  1168. /* update link parameters */
  1169. if (duplex == LINKEVENT_FULL_DUPLEX)
  1170. adapter->link_duplex = DUPLEX_FULL;
  1171. else
  1172. adapter->link_duplex = DUPLEX_HALF;
  1173. adapter->module_type = module;
  1174. adapter->link_autoneg = autoneg;
  1175. adapter->link_speed = link_speed;
  1176. netxen_advert_link_change(adapter, link_status);
  1177. }
  1178. static void
  1179. netxen_handle_fw_message(int desc_cnt, int index,
  1180. struct nx_host_sds_ring *sds_ring)
  1181. {
  1182. nx_fw_msg_t msg;
  1183. struct status_desc *desc;
  1184. int i = 0, opcode;
  1185. while (desc_cnt > 0 && i < 8) {
  1186. desc = &sds_ring->desc_head[index];
  1187. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  1188. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  1189. index = get_next_index(index, sds_ring->num_desc);
  1190. desc_cnt--;
  1191. }
  1192. opcode = netxen_get_nic_msg_opcode(msg.body[0]);
  1193. switch (opcode) {
  1194. case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  1195. netxen_handle_linkevent(sds_ring->adapter, &msg);
  1196. break;
  1197. default:
  1198. break;
  1199. }
  1200. }
  1201. static int
  1202. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  1203. struct nx_host_rds_ring *rds_ring,
  1204. struct netxen_rx_buffer *buffer)
  1205. {
  1206. struct sk_buff *skb;
  1207. dma_addr_t dma;
  1208. struct pci_dev *pdev = adapter->pdev;
  1209. buffer->skb = netdev_alloc_skb(adapter->netdev, rds_ring->skb_size);
  1210. if (!buffer->skb)
  1211. return 1;
  1212. skb = buffer->skb;
  1213. if (!adapter->ahw.cut_through)
  1214. skb_reserve(skb, 2);
  1215. dma = pci_map_single(pdev, skb->data,
  1216. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  1217. if (pci_dma_mapping_error(pdev, dma)) {
  1218. dev_kfree_skb_any(skb);
  1219. buffer->skb = NULL;
  1220. return 1;
  1221. }
  1222. buffer->skb = skb;
  1223. buffer->dma = dma;
  1224. buffer->state = NETXEN_BUFFER_BUSY;
  1225. return 0;
  1226. }
  1227. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  1228. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  1229. {
  1230. struct netxen_rx_buffer *buffer;
  1231. struct sk_buff *skb;
  1232. buffer = &rds_ring->rx_buf_arr[index];
  1233. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  1234. PCI_DMA_FROMDEVICE);
  1235. skb = buffer->skb;
  1236. if (!skb)
  1237. goto no_skb;
  1238. if (likely((adapter->netdev->features & NETIF_F_RXCSUM)
  1239. && cksum == STATUS_CKSUM_OK)) {
  1240. adapter->stats.csummed++;
  1241. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1242. } else
  1243. skb->ip_summed = CHECKSUM_NONE;
  1244. buffer->skb = NULL;
  1245. no_skb:
  1246. buffer->state = NETXEN_BUFFER_FREE;
  1247. return skb;
  1248. }
  1249. static struct netxen_rx_buffer *
  1250. netxen_process_rcv(struct netxen_adapter *adapter,
  1251. struct nx_host_sds_ring *sds_ring,
  1252. int ring, u64 sts_data0)
  1253. {
  1254. struct net_device *netdev = adapter->netdev;
  1255. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1256. struct netxen_rx_buffer *buffer;
  1257. struct sk_buff *skb;
  1258. struct nx_host_rds_ring *rds_ring;
  1259. int index, length, cksum, pkt_offset;
  1260. if (unlikely(ring >= adapter->max_rds_rings))
  1261. return NULL;
  1262. rds_ring = &recv_ctx->rds_rings[ring];
  1263. index = netxen_get_sts_refhandle(sts_data0);
  1264. if (unlikely(index >= rds_ring->num_desc))
  1265. return NULL;
  1266. buffer = &rds_ring->rx_buf_arr[index];
  1267. length = netxen_get_sts_totallength(sts_data0);
  1268. cksum = netxen_get_sts_status(sts_data0);
  1269. pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
  1270. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  1271. if (!skb)
  1272. return buffer;
  1273. if (length > rds_ring->skb_size)
  1274. skb_put(skb, rds_ring->skb_size);
  1275. else
  1276. skb_put(skb, length);
  1277. if (pkt_offset)
  1278. skb_pull(skb, pkt_offset);
  1279. skb->protocol = eth_type_trans(skb, netdev);
  1280. napi_gro_receive(&sds_ring->napi, skb);
  1281. adapter->stats.rx_pkts++;
  1282. adapter->stats.rxbytes += length;
  1283. return buffer;
  1284. }
  1285. #define TCP_HDR_SIZE 20
  1286. #define TCP_TS_OPTION_SIZE 12
  1287. #define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
  1288. static struct netxen_rx_buffer *
  1289. netxen_process_lro(struct netxen_adapter *adapter,
  1290. struct nx_host_sds_ring *sds_ring,
  1291. int ring, u64 sts_data0, u64 sts_data1)
  1292. {
  1293. struct net_device *netdev = adapter->netdev;
  1294. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1295. struct netxen_rx_buffer *buffer;
  1296. struct sk_buff *skb;
  1297. struct nx_host_rds_ring *rds_ring;
  1298. struct iphdr *iph;
  1299. struct tcphdr *th;
  1300. bool push, timestamp;
  1301. int l2_hdr_offset, l4_hdr_offset;
  1302. int index;
  1303. u16 lro_length, length, data_offset;
  1304. u32 seq_number;
  1305. u8 vhdr_len = 0;
  1306. if (unlikely(ring >= adapter->max_rds_rings))
  1307. return NULL;
  1308. rds_ring = &recv_ctx->rds_rings[ring];
  1309. index = netxen_get_lro_sts_refhandle(sts_data0);
  1310. if (unlikely(index >= rds_ring->num_desc))
  1311. return NULL;
  1312. buffer = &rds_ring->rx_buf_arr[index];
  1313. timestamp = netxen_get_lro_sts_timestamp(sts_data0);
  1314. lro_length = netxen_get_lro_sts_length(sts_data0);
  1315. l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
  1316. l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
  1317. push = netxen_get_lro_sts_push_flag(sts_data0);
  1318. seq_number = netxen_get_lro_sts_seq_number(sts_data1);
  1319. skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
  1320. if (!skb)
  1321. return buffer;
  1322. if (timestamp)
  1323. data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
  1324. else
  1325. data_offset = l4_hdr_offset + TCP_HDR_SIZE;
  1326. skb_put(skb, lro_length + data_offset);
  1327. skb_pull(skb, l2_hdr_offset);
  1328. skb->protocol = eth_type_trans(skb, netdev);
  1329. if (skb->protocol == htons(ETH_P_8021Q))
  1330. vhdr_len = VLAN_HLEN;
  1331. iph = (struct iphdr *)(skb->data + vhdr_len);
  1332. th = (struct tcphdr *)((skb->data + vhdr_len) + (iph->ihl << 2));
  1333. length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
  1334. csum_replace2(&iph->check, iph->tot_len, htons(length));
  1335. iph->tot_len = htons(length);
  1336. th->psh = push;
  1337. th->seq = htonl(seq_number);
  1338. length = skb->len;
  1339. if (adapter->flags & NETXEN_FW_MSS_CAP)
  1340. skb_shinfo(skb)->gso_size = netxen_get_lro_sts_mss(sts_data1);
  1341. netif_receive_skb(skb);
  1342. adapter->stats.lro_pkts++;
  1343. adapter->stats.rxbytes += length;
  1344. return buffer;
  1345. }
  1346. #define netxen_merge_rx_buffers(list, head) \
  1347. do { list_splice_tail_init(list, head); } while (0);
  1348. int
  1349. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  1350. {
  1351. struct netxen_adapter *adapter = sds_ring->adapter;
  1352. struct list_head *cur;
  1353. struct status_desc *desc;
  1354. struct netxen_rx_buffer *rxbuf;
  1355. u32 consumer = sds_ring->consumer;
  1356. int count = 0;
  1357. u64 sts_data0, sts_data1;
  1358. int opcode, ring = 0, desc_cnt;
  1359. while (count < max) {
  1360. desc = &sds_ring->desc_head[consumer];
  1361. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1362. if (!(sts_data0 & STATUS_OWNER_HOST))
  1363. break;
  1364. desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
  1365. opcode = netxen_get_sts_opcode(sts_data0);
  1366. switch (opcode) {
  1367. case NETXEN_NIC_RXPKT_DESC:
  1368. case NETXEN_OLD_RXPKT_DESC:
  1369. case NETXEN_NIC_SYN_OFFLOAD:
  1370. ring = netxen_get_sts_type(sts_data0);
  1371. rxbuf = netxen_process_rcv(adapter, sds_ring,
  1372. ring, sts_data0);
  1373. break;
  1374. case NETXEN_NIC_LRO_DESC:
  1375. ring = netxen_get_lro_sts_type(sts_data0);
  1376. sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
  1377. rxbuf = netxen_process_lro(adapter, sds_ring,
  1378. ring, sts_data0, sts_data1);
  1379. break;
  1380. case NETXEN_NIC_RESPONSE_DESC:
  1381. netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
  1382. default:
  1383. goto skip;
  1384. }
  1385. WARN_ON(desc_cnt > 1);
  1386. if (rxbuf)
  1387. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1388. skip:
  1389. for (; desc_cnt > 0; desc_cnt--) {
  1390. desc = &sds_ring->desc_head[consumer];
  1391. desc->status_desc_data[0] =
  1392. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1393. consumer = get_next_index(consumer, sds_ring->num_desc);
  1394. }
  1395. count++;
  1396. }
  1397. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1398. struct nx_host_rds_ring *rds_ring =
  1399. &adapter->recv_ctx.rds_rings[ring];
  1400. if (!list_empty(&sds_ring->free_list[ring])) {
  1401. list_for_each(cur, &sds_ring->free_list[ring]) {
  1402. rxbuf = list_entry(cur,
  1403. struct netxen_rx_buffer, list);
  1404. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1405. }
  1406. spin_lock(&rds_ring->lock);
  1407. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  1408. &rds_ring->free_list);
  1409. spin_unlock(&rds_ring->lock);
  1410. }
  1411. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  1412. }
  1413. if (count) {
  1414. sds_ring->consumer = consumer;
  1415. NXWRIO(adapter, sds_ring->crb_sts_consumer, consumer);
  1416. }
  1417. return count;
  1418. }
  1419. /* Process Command status ring */
  1420. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1421. {
  1422. u32 sw_consumer, hw_consumer;
  1423. int count = 0, i;
  1424. struct netxen_cmd_buffer *buffer;
  1425. struct pci_dev *pdev = adapter->pdev;
  1426. struct net_device *netdev = adapter->netdev;
  1427. struct netxen_skb_frag *frag;
  1428. int done = 0;
  1429. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  1430. if (!spin_trylock_bh(&adapter->tx_clean_lock))
  1431. return 1;
  1432. sw_consumer = tx_ring->sw_consumer;
  1433. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1434. while (sw_consumer != hw_consumer) {
  1435. buffer = &tx_ring->cmd_buf_arr[sw_consumer];
  1436. if (buffer->skb) {
  1437. frag = &buffer->frag_array[0];
  1438. pci_unmap_single(pdev, frag->dma, frag->length,
  1439. PCI_DMA_TODEVICE);
  1440. frag->dma = 0ULL;
  1441. for (i = 1; i < buffer->frag_count; i++) {
  1442. frag++; /* Get the next frag */
  1443. pci_unmap_page(pdev, frag->dma, frag->length,
  1444. PCI_DMA_TODEVICE);
  1445. frag->dma = 0ULL;
  1446. }
  1447. adapter->stats.xmitfinished++;
  1448. dev_kfree_skb_any(buffer->skb);
  1449. buffer->skb = NULL;
  1450. }
  1451. sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
  1452. if (++count >= MAX_STATUS_HANDLE)
  1453. break;
  1454. }
  1455. tx_ring->sw_consumer = sw_consumer;
  1456. if (count && netif_running(netdev)) {
  1457. smp_mb();
  1458. if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev))
  1459. if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH)
  1460. netif_wake_queue(netdev);
  1461. adapter->tx_timeo_cnt = 0;
  1462. }
  1463. /*
  1464. * If everything is freed up to consumer then check if the ring is full
  1465. * If the ring is full then check if more needs to be freed and
  1466. * schedule the call back again.
  1467. *
  1468. * This happens when there are 2 CPUs. One could be freeing and the
  1469. * other filling it. If the ring is full when we get out of here and
  1470. * the card has already interrupted the host then the host can miss the
  1471. * interrupt.
  1472. *
  1473. * There is still a possible race condition and the host could miss an
  1474. * interrupt. The card has to take care of this.
  1475. */
  1476. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1477. done = (sw_consumer == hw_consumer);
  1478. spin_unlock_bh(&adapter->tx_clean_lock);
  1479. return done;
  1480. }
  1481. void
  1482. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  1483. struct nx_host_rds_ring *rds_ring)
  1484. {
  1485. struct rcv_desc *pdesc;
  1486. struct netxen_rx_buffer *buffer;
  1487. int producer, count = 0;
  1488. netxen_ctx_msg msg = 0;
  1489. struct list_head *head;
  1490. producer = rds_ring->producer;
  1491. head = &rds_ring->free_list;
  1492. while (!list_empty(head)) {
  1493. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1494. if (!buffer->skb) {
  1495. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1496. break;
  1497. }
  1498. count++;
  1499. list_del(&buffer->list);
  1500. /* make a rcv descriptor */
  1501. pdesc = &rds_ring->desc_head[producer];
  1502. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1503. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1504. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1505. producer = get_next_index(producer, rds_ring->num_desc);
  1506. }
  1507. if (count) {
  1508. rds_ring->producer = producer;
  1509. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1510. (producer-1) & (rds_ring->num_desc-1));
  1511. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  1512. /*
  1513. * Write a doorbell msg to tell phanmon of change in
  1514. * receive ring producer
  1515. * Only for firmware version < 4.0.0
  1516. */
  1517. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1518. netxen_set_msg_privid(msg);
  1519. netxen_set_msg_count(msg,
  1520. ((producer - 1) &
  1521. (rds_ring->num_desc - 1)));
  1522. netxen_set_msg_ctxid(msg, adapter->portnum);
  1523. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1524. NXWRIO(adapter, DB_NORMALIZE(adapter,
  1525. NETXEN_RCV_PRODUCER_OFFSET), msg);
  1526. }
  1527. }
  1528. }
  1529. static void
  1530. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1531. struct nx_host_rds_ring *rds_ring)
  1532. {
  1533. struct rcv_desc *pdesc;
  1534. struct netxen_rx_buffer *buffer;
  1535. int producer, count = 0;
  1536. struct list_head *head;
  1537. if (!spin_trylock(&rds_ring->lock))
  1538. return;
  1539. producer = rds_ring->producer;
  1540. head = &rds_ring->free_list;
  1541. while (!list_empty(head)) {
  1542. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1543. if (!buffer->skb) {
  1544. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1545. break;
  1546. }
  1547. count++;
  1548. list_del(&buffer->list);
  1549. /* make a rcv descriptor */
  1550. pdesc = &rds_ring->desc_head[producer];
  1551. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1552. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1553. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1554. producer = get_next_index(producer, rds_ring->num_desc);
  1555. }
  1556. if (count) {
  1557. rds_ring->producer = producer;
  1558. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1559. (producer - 1) & (rds_ring->num_desc - 1));
  1560. }
  1561. spin_unlock(&rds_ring->lock);
  1562. }
  1563. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1564. {
  1565. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1566. }