qed_main.c 28 KB

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  1. /* QLogic qed NIC Driver
  2. * Copyright (c) 2015 QLogic Corporation
  3. *
  4. * This software is available under the terms of the GNU General Public License
  5. * (GPL) Version 2, available from the file COPYING in the main directory of
  6. * this source tree.
  7. */
  8. #include <linux/stddef.h>
  9. #include <linux/pci.h>
  10. #include <linux/kernel.h>
  11. #include <linux/slab.h>
  12. #include <linux/version.h>
  13. #include <linux/delay.h>
  14. #include <asm/byteorder.h>
  15. #include <linux/dma-mapping.h>
  16. #include <linux/string.h>
  17. #include <linux/module.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/workqueue.h>
  20. #include <linux/ethtool.h>
  21. #include <linux/etherdevice.h>
  22. #include <linux/vmalloc.h>
  23. #include <linux/qed/qed_if.h>
  24. #include <linux/crash_dump.h>
  25. #include "qed.h"
  26. #include "qed_sp.h"
  27. #include "qed_dev_api.h"
  28. #include "qed_mcp.h"
  29. #include "qed_hw.h"
  30. static const char version[] =
  31. "QLogic QL4xxx 40G/100G Ethernet Driver qed " DRV_MODULE_VERSION "\n";
  32. MODULE_DESCRIPTION("QLogic 25G/40G/50G/100G Core Module");
  33. MODULE_LICENSE("GPL");
  34. MODULE_VERSION(DRV_MODULE_VERSION);
  35. #define FW_FILE_VERSION \
  36. __stringify(FW_MAJOR_VERSION) "." \
  37. __stringify(FW_MINOR_VERSION) "." \
  38. __stringify(FW_REVISION_VERSION) "." \
  39. __stringify(FW_ENGINEERING_VERSION)
  40. #define QED_FW_FILE_NAME \
  41. "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin"
  42. static int __init qed_init(void)
  43. {
  44. pr_notice("qed_init called\n");
  45. pr_info("%s", version);
  46. return 0;
  47. }
  48. static void __exit qed_cleanup(void)
  49. {
  50. pr_notice("qed_cleanup called\n");
  51. }
  52. module_init(qed_init);
  53. module_exit(qed_cleanup);
  54. /* Check if the DMA controller on the machine can properly handle the DMA
  55. * addressing required by the device.
  56. */
  57. static int qed_set_coherency_mask(struct qed_dev *cdev)
  58. {
  59. struct device *dev = &cdev->pdev->dev;
  60. if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
  61. if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
  62. DP_NOTICE(cdev,
  63. "Can't request 64-bit consistent allocations\n");
  64. return -EIO;
  65. }
  66. } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
  67. DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n");
  68. return -EIO;
  69. }
  70. return 0;
  71. }
  72. static void qed_free_pci(struct qed_dev *cdev)
  73. {
  74. struct pci_dev *pdev = cdev->pdev;
  75. if (cdev->doorbells)
  76. iounmap(cdev->doorbells);
  77. if (cdev->regview)
  78. iounmap(cdev->regview);
  79. if (atomic_read(&pdev->enable_cnt) == 1)
  80. pci_release_regions(pdev);
  81. pci_disable_device(pdev);
  82. }
  83. /* Performs PCI initializations as well as initializing PCI-related parameters
  84. * in the device structrue. Returns 0 in case of success.
  85. */
  86. static int qed_init_pci(struct qed_dev *cdev,
  87. struct pci_dev *pdev)
  88. {
  89. int rc;
  90. cdev->pdev = pdev;
  91. rc = pci_enable_device(pdev);
  92. if (rc) {
  93. DP_NOTICE(cdev, "Cannot enable PCI device\n");
  94. goto err0;
  95. }
  96. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
  97. DP_NOTICE(cdev, "No memory region found in bar #0\n");
  98. rc = -EIO;
  99. goto err1;
  100. }
  101. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
  102. DP_NOTICE(cdev, "No memory region found in bar #2\n");
  103. rc = -EIO;
  104. goto err1;
  105. }
  106. if (atomic_read(&pdev->enable_cnt) == 1) {
  107. rc = pci_request_regions(pdev, "qed");
  108. if (rc) {
  109. DP_NOTICE(cdev,
  110. "Failed to request PCI memory resources\n");
  111. goto err1;
  112. }
  113. pci_set_master(pdev);
  114. pci_save_state(pdev);
  115. }
  116. if (!pci_is_pcie(pdev)) {
  117. DP_NOTICE(cdev, "The bus is not PCI Express\n");
  118. rc = -EIO;
  119. goto err2;
  120. }
  121. cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
  122. if (cdev->pci_params.pm_cap == 0)
  123. DP_NOTICE(cdev, "Cannot find power management capability\n");
  124. rc = qed_set_coherency_mask(cdev);
  125. if (rc)
  126. goto err2;
  127. cdev->pci_params.mem_start = pci_resource_start(pdev, 0);
  128. cdev->pci_params.mem_end = pci_resource_end(pdev, 0);
  129. cdev->pci_params.irq = pdev->irq;
  130. cdev->regview = pci_ioremap_bar(pdev, 0);
  131. if (!cdev->regview) {
  132. DP_NOTICE(cdev, "Cannot map register space, aborting\n");
  133. rc = -ENOMEM;
  134. goto err2;
  135. }
  136. cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2);
  137. cdev->db_size = pci_resource_len(cdev->pdev, 2);
  138. cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size);
  139. if (!cdev->doorbells) {
  140. DP_NOTICE(cdev, "Cannot map doorbell space\n");
  141. return -ENOMEM;
  142. }
  143. return 0;
  144. err2:
  145. pci_release_regions(pdev);
  146. err1:
  147. pci_disable_device(pdev);
  148. err0:
  149. return rc;
  150. }
  151. int qed_fill_dev_info(struct qed_dev *cdev,
  152. struct qed_dev_info *dev_info)
  153. {
  154. struct qed_ptt *ptt;
  155. memset(dev_info, 0, sizeof(struct qed_dev_info));
  156. dev_info->num_hwfns = cdev->num_hwfns;
  157. dev_info->pci_mem_start = cdev->pci_params.mem_start;
  158. dev_info->pci_mem_end = cdev->pci_params.mem_end;
  159. dev_info->pci_irq = cdev->pci_params.irq;
  160. dev_info->is_mf = IS_MF(&cdev->hwfns[0]);
  161. ether_addr_copy(dev_info->hw_mac, cdev->hwfns[0].hw_info.hw_mac_addr);
  162. dev_info->fw_major = FW_MAJOR_VERSION;
  163. dev_info->fw_minor = FW_MINOR_VERSION;
  164. dev_info->fw_rev = FW_REVISION_VERSION;
  165. dev_info->fw_eng = FW_ENGINEERING_VERSION;
  166. dev_info->mf_mode = cdev->mf_mode;
  167. qed_mcp_get_mfw_ver(cdev, &dev_info->mfw_rev);
  168. ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
  169. if (ptt) {
  170. qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt,
  171. &dev_info->flash_size);
  172. qed_ptt_release(QED_LEADING_HWFN(cdev), ptt);
  173. }
  174. return 0;
  175. }
  176. static void qed_free_cdev(struct qed_dev *cdev)
  177. {
  178. kfree((void *)cdev);
  179. }
  180. static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev)
  181. {
  182. struct qed_dev *cdev;
  183. cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
  184. if (!cdev)
  185. return cdev;
  186. qed_init_struct(cdev);
  187. return cdev;
  188. }
  189. /* Sets the requested power state */
  190. static int qed_set_power_state(struct qed_dev *cdev,
  191. pci_power_t state)
  192. {
  193. if (!cdev)
  194. return -ENODEV;
  195. DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n");
  196. return 0;
  197. }
  198. /* probing */
  199. static struct qed_dev *qed_probe(struct pci_dev *pdev,
  200. enum qed_protocol protocol,
  201. u32 dp_module,
  202. u8 dp_level)
  203. {
  204. struct qed_dev *cdev;
  205. int rc;
  206. cdev = qed_alloc_cdev(pdev);
  207. if (!cdev)
  208. goto err0;
  209. cdev->protocol = protocol;
  210. qed_init_dp(cdev, dp_module, dp_level);
  211. rc = qed_init_pci(cdev, pdev);
  212. if (rc) {
  213. DP_ERR(cdev, "init pci failed\n");
  214. goto err1;
  215. }
  216. DP_INFO(cdev, "PCI init completed successfully\n");
  217. rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT);
  218. if (rc) {
  219. DP_ERR(cdev, "hw prepare failed\n");
  220. goto err2;
  221. }
  222. DP_INFO(cdev, "qed_probe completed successffuly\n");
  223. return cdev;
  224. err2:
  225. qed_free_pci(cdev);
  226. err1:
  227. qed_free_cdev(cdev);
  228. err0:
  229. return NULL;
  230. }
  231. static void qed_remove(struct qed_dev *cdev)
  232. {
  233. if (!cdev)
  234. return;
  235. qed_hw_remove(cdev);
  236. qed_free_pci(cdev);
  237. qed_set_power_state(cdev, PCI_D3hot);
  238. qed_free_cdev(cdev);
  239. }
  240. static void qed_disable_msix(struct qed_dev *cdev)
  241. {
  242. if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
  243. pci_disable_msix(cdev->pdev);
  244. kfree(cdev->int_params.msix_table);
  245. } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) {
  246. pci_disable_msi(cdev->pdev);
  247. }
  248. memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param));
  249. }
  250. static int qed_enable_msix(struct qed_dev *cdev,
  251. struct qed_int_params *int_params)
  252. {
  253. int i, rc, cnt;
  254. cnt = int_params->in.num_vectors;
  255. for (i = 0; i < cnt; i++)
  256. int_params->msix_table[i].entry = i;
  257. rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table,
  258. int_params->in.min_msix_cnt, cnt);
  259. if (rc < cnt && rc >= int_params->in.min_msix_cnt &&
  260. (rc % cdev->num_hwfns)) {
  261. pci_disable_msix(cdev->pdev);
  262. /* If fastpath is initialized, we need at least one interrupt
  263. * per hwfn [and the slow path interrupts]. New requested number
  264. * should be a multiple of the number of hwfns.
  265. */
  266. cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns;
  267. DP_NOTICE(cdev,
  268. "Trying to enable MSI-X with less vectors (%d out of %d)\n",
  269. cnt, int_params->in.num_vectors);
  270. rc = pci_enable_msix_exact(cdev->pdev,
  271. int_params->msix_table, cnt);
  272. if (!rc)
  273. rc = cnt;
  274. }
  275. if (rc > 0) {
  276. /* MSI-x configuration was achieved */
  277. int_params->out.int_mode = QED_INT_MODE_MSIX;
  278. int_params->out.num_vectors = rc;
  279. rc = 0;
  280. } else {
  281. DP_NOTICE(cdev,
  282. "Failed to enable MSI-X [Requested %d vectors][rc %d]\n",
  283. cnt, rc);
  284. }
  285. return rc;
  286. }
  287. /* This function outputs the int mode and the number of enabled msix vector */
  288. static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode)
  289. {
  290. struct qed_int_params *int_params = &cdev->int_params;
  291. struct msix_entry *tbl;
  292. int rc = 0, cnt;
  293. switch (int_params->in.int_mode) {
  294. case QED_INT_MODE_MSIX:
  295. /* Allocate MSIX table */
  296. cnt = int_params->in.num_vectors;
  297. int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL);
  298. if (!int_params->msix_table) {
  299. rc = -ENOMEM;
  300. goto out;
  301. }
  302. /* Enable MSIX */
  303. rc = qed_enable_msix(cdev, int_params);
  304. if (!rc)
  305. goto out;
  306. DP_NOTICE(cdev, "Failed to enable MSI-X\n");
  307. kfree(int_params->msix_table);
  308. if (force_mode)
  309. goto out;
  310. /* Fallthrough */
  311. case QED_INT_MODE_MSI:
  312. rc = pci_enable_msi(cdev->pdev);
  313. if (!rc) {
  314. int_params->out.int_mode = QED_INT_MODE_MSI;
  315. goto out;
  316. }
  317. DP_NOTICE(cdev, "Failed to enable MSI\n");
  318. if (force_mode)
  319. goto out;
  320. /* Fallthrough */
  321. case QED_INT_MODE_INTA:
  322. int_params->out.int_mode = QED_INT_MODE_INTA;
  323. rc = 0;
  324. goto out;
  325. default:
  326. DP_NOTICE(cdev, "Unknown int_mode value %d\n",
  327. int_params->in.int_mode);
  328. rc = -EINVAL;
  329. }
  330. out:
  331. cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE;
  332. return rc;
  333. }
  334. static void qed_simd_handler_config(struct qed_dev *cdev, void *token,
  335. int index, void(*handler)(void *))
  336. {
  337. struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
  338. int relative_idx = index / cdev->num_hwfns;
  339. hwfn->simd_proto_handler[relative_idx].func = handler;
  340. hwfn->simd_proto_handler[relative_idx].token = token;
  341. }
  342. static void qed_simd_handler_clean(struct qed_dev *cdev, int index)
  343. {
  344. struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
  345. int relative_idx = index / cdev->num_hwfns;
  346. memset(&hwfn->simd_proto_handler[relative_idx], 0,
  347. sizeof(struct qed_simd_fp_handler));
  348. }
  349. static irqreturn_t qed_msix_sp_int(int irq, void *tasklet)
  350. {
  351. tasklet_schedule((struct tasklet_struct *)tasklet);
  352. return IRQ_HANDLED;
  353. }
  354. static irqreturn_t qed_single_int(int irq, void *dev_instance)
  355. {
  356. struct qed_dev *cdev = (struct qed_dev *)dev_instance;
  357. struct qed_hwfn *hwfn;
  358. irqreturn_t rc = IRQ_NONE;
  359. u64 status;
  360. int i, j;
  361. for (i = 0; i < cdev->num_hwfns; i++) {
  362. status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]);
  363. if (!status)
  364. continue;
  365. hwfn = &cdev->hwfns[i];
  366. /* Slowpath interrupt */
  367. if (unlikely(status & 0x1)) {
  368. tasklet_schedule(hwfn->sp_dpc);
  369. status &= ~0x1;
  370. rc = IRQ_HANDLED;
  371. }
  372. /* Fastpath interrupts */
  373. for (j = 0; j < 64; j++) {
  374. if ((0x2ULL << j) & status) {
  375. struct qed_simd_fp_handler *p_handler =
  376. &hwfn->simd_proto_handler[j];
  377. if (p_handler->func)
  378. p_handler->func(p_handler->token);
  379. else
  380. DP_NOTICE(hwfn,
  381. "Not calling fastpath handler as it is NULL [handler #%d, status 0x%llx]\n",
  382. j, status);
  383. status &= ~(0x2ULL << j);
  384. rc = IRQ_HANDLED;
  385. }
  386. }
  387. if (unlikely(status))
  388. DP_VERBOSE(hwfn, NETIF_MSG_INTR,
  389. "got an unknown interrupt status 0x%llx\n",
  390. status);
  391. }
  392. return rc;
  393. }
  394. int qed_slowpath_irq_req(struct qed_hwfn *hwfn)
  395. {
  396. struct qed_dev *cdev = hwfn->cdev;
  397. int rc = 0;
  398. u8 id;
  399. if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
  400. id = hwfn->my_id;
  401. snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x",
  402. id, cdev->pdev->bus->number,
  403. PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id);
  404. rc = request_irq(cdev->int_params.msix_table[id].vector,
  405. qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc);
  406. if (!rc)
  407. DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP),
  408. "Requested slowpath MSI-X\n");
  409. } else {
  410. unsigned long flags = 0;
  411. snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x",
  412. cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn),
  413. PCI_FUNC(cdev->pdev->devfn));
  414. if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA)
  415. flags |= IRQF_SHARED;
  416. rc = request_irq(cdev->pdev->irq, qed_single_int,
  417. flags, cdev->name, cdev);
  418. }
  419. return rc;
  420. }
  421. static void qed_slowpath_irq_free(struct qed_dev *cdev)
  422. {
  423. int i;
  424. if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
  425. for_each_hwfn(cdev, i) {
  426. if (!cdev->hwfns[i].b_int_requested)
  427. break;
  428. synchronize_irq(cdev->int_params.msix_table[i].vector);
  429. free_irq(cdev->int_params.msix_table[i].vector,
  430. cdev->hwfns[i].sp_dpc);
  431. }
  432. } else {
  433. if (QED_LEADING_HWFN(cdev)->b_int_requested)
  434. free_irq(cdev->pdev->irq, cdev);
  435. }
  436. qed_int_disable_post_isr_release(cdev);
  437. }
  438. static int qed_nic_stop(struct qed_dev *cdev)
  439. {
  440. int i, rc;
  441. rc = qed_hw_stop(cdev);
  442. for (i = 0; i < cdev->num_hwfns; i++) {
  443. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  444. if (p_hwfn->b_sp_dpc_enabled) {
  445. tasklet_disable(p_hwfn->sp_dpc);
  446. p_hwfn->b_sp_dpc_enabled = false;
  447. DP_VERBOSE(cdev, NETIF_MSG_IFDOWN,
  448. "Disabled sp taskelt [hwfn %d] at %p\n",
  449. i, p_hwfn->sp_dpc);
  450. }
  451. }
  452. return rc;
  453. }
  454. static int qed_nic_reset(struct qed_dev *cdev)
  455. {
  456. int rc;
  457. rc = qed_hw_reset(cdev);
  458. if (rc)
  459. return rc;
  460. qed_resc_free(cdev);
  461. return 0;
  462. }
  463. static int qed_nic_setup(struct qed_dev *cdev)
  464. {
  465. int rc;
  466. rc = qed_resc_alloc(cdev);
  467. if (rc)
  468. return rc;
  469. DP_INFO(cdev, "Allocated qed resources\n");
  470. qed_resc_setup(cdev);
  471. return rc;
  472. }
  473. static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt)
  474. {
  475. int limit = 0;
  476. /* Mark the fastpath as free/used */
  477. cdev->int_params.fp_initialized = cnt ? true : false;
  478. if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX)
  479. limit = cdev->num_hwfns * 63;
  480. else if (cdev->int_params.fp_msix_cnt)
  481. limit = cdev->int_params.fp_msix_cnt;
  482. if (!limit)
  483. return -ENOMEM;
  484. return min_t(int, cnt, limit);
  485. }
  486. static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info)
  487. {
  488. memset(info, 0, sizeof(struct qed_int_info));
  489. if (!cdev->int_params.fp_initialized) {
  490. DP_INFO(cdev,
  491. "Protocol driver requested interrupt information, but its support is not yet configured\n");
  492. return -EINVAL;
  493. }
  494. /* Need to expose only MSI-X information; Single IRQ is handled solely
  495. * by qed.
  496. */
  497. if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
  498. int msix_base = cdev->int_params.fp_msix_base;
  499. info->msix_cnt = cdev->int_params.fp_msix_cnt;
  500. info->msix = &cdev->int_params.msix_table[msix_base];
  501. }
  502. return 0;
  503. }
  504. static int qed_slowpath_setup_int(struct qed_dev *cdev,
  505. enum qed_int_mode int_mode)
  506. {
  507. int rc, i;
  508. u8 num_vectors = 0;
  509. memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
  510. cdev->int_params.in.int_mode = int_mode;
  511. for_each_hwfn(cdev, i)
  512. num_vectors += qed_int_get_num_sbs(&cdev->hwfns[i], NULL) + 1;
  513. cdev->int_params.in.num_vectors = num_vectors;
  514. /* We want a minimum of one slowpath and one fastpath vector per hwfn */
  515. cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2;
  516. if (is_kdump_kernel()) {
  517. DP_INFO(cdev,
  518. "Kdump kernel: Limit the max number of requested MSI-X vectors to %hd\n",
  519. cdev->int_params.in.min_msix_cnt);
  520. cdev->int_params.in.num_vectors =
  521. cdev->int_params.in.min_msix_cnt;
  522. }
  523. rc = qed_set_int_mode(cdev, false);
  524. if (rc) {
  525. DP_ERR(cdev, "qed_slowpath_setup_int ERR\n");
  526. return rc;
  527. }
  528. cdev->int_params.fp_msix_base = cdev->num_hwfns;
  529. cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors -
  530. cdev->num_hwfns;
  531. return 0;
  532. }
  533. u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len,
  534. u8 *input_buf, u32 max_size, u8 *unzip_buf)
  535. {
  536. int rc;
  537. p_hwfn->stream->next_in = input_buf;
  538. p_hwfn->stream->avail_in = input_len;
  539. p_hwfn->stream->next_out = unzip_buf;
  540. p_hwfn->stream->avail_out = max_size;
  541. rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS);
  542. if (rc != Z_OK) {
  543. DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n",
  544. rc);
  545. return 0;
  546. }
  547. rc = zlib_inflate(p_hwfn->stream, Z_FINISH);
  548. zlib_inflateEnd(p_hwfn->stream);
  549. if (rc != Z_OK && rc != Z_STREAM_END) {
  550. DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n",
  551. p_hwfn->stream->msg, rc);
  552. return 0;
  553. }
  554. return p_hwfn->stream->total_out / 4;
  555. }
  556. static int qed_alloc_stream_mem(struct qed_dev *cdev)
  557. {
  558. int i;
  559. void *workspace;
  560. for_each_hwfn(cdev, i) {
  561. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  562. p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL);
  563. if (!p_hwfn->stream)
  564. return -ENOMEM;
  565. workspace = vzalloc(zlib_inflate_workspacesize());
  566. if (!workspace)
  567. return -ENOMEM;
  568. p_hwfn->stream->workspace = workspace;
  569. }
  570. return 0;
  571. }
  572. static void qed_free_stream_mem(struct qed_dev *cdev)
  573. {
  574. int i;
  575. for_each_hwfn(cdev, i) {
  576. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  577. if (!p_hwfn->stream)
  578. return;
  579. vfree(p_hwfn->stream->workspace);
  580. kfree(p_hwfn->stream);
  581. }
  582. }
  583. static void qed_update_pf_params(struct qed_dev *cdev,
  584. struct qed_pf_params *params)
  585. {
  586. int i;
  587. for (i = 0; i < cdev->num_hwfns; i++) {
  588. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  589. p_hwfn->pf_params = *params;
  590. }
  591. }
  592. static int qed_slowpath_start(struct qed_dev *cdev,
  593. struct qed_slowpath_params *params)
  594. {
  595. struct qed_mcp_drv_version drv_version;
  596. const u8 *data = NULL;
  597. struct qed_hwfn *hwfn;
  598. int rc;
  599. rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME,
  600. &cdev->pdev->dev);
  601. if (rc) {
  602. DP_NOTICE(cdev,
  603. "Failed to find fw file - /lib/firmware/%s\n",
  604. QED_FW_FILE_NAME);
  605. goto err;
  606. }
  607. rc = qed_nic_setup(cdev);
  608. if (rc)
  609. goto err;
  610. rc = qed_slowpath_setup_int(cdev, params->int_mode);
  611. if (rc)
  612. goto err1;
  613. /* Allocate stream for unzipping */
  614. rc = qed_alloc_stream_mem(cdev);
  615. if (rc) {
  616. DP_NOTICE(cdev, "Failed to allocate stream memory\n");
  617. goto err2;
  618. }
  619. /* Start the slowpath */
  620. data = cdev->firmware->data;
  621. rc = qed_hw_init(cdev, true, cdev->int_params.out.int_mode,
  622. true, data);
  623. if (rc)
  624. goto err3;
  625. DP_INFO(cdev,
  626. "HW initialization and function start completed successfully\n");
  627. hwfn = QED_LEADING_HWFN(cdev);
  628. drv_version.version = (params->drv_major << 24) |
  629. (params->drv_minor << 16) |
  630. (params->drv_rev << 8) |
  631. (params->drv_eng);
  632. strlcpy(drv_version.name, params->name,
  633. MCP_DRV_VER_STR_SIZE - 4);
  634. rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt,
  635. &drv_version);
  636. if (rc) {
  637. DP_NOTICE(cdev, "Failed sending drv version command\n");
  638. return rc;
  639. }
  640. return 0;
  641. err3:
  642. qed_free_stream_mem(cdev);
  643. qed_slowpath_irq_free(cdev);
  644. err2:
  645. qed_disable_msix(cdev);
  646. err1:
  647. qed_resc_free(cdev);
  648. err:
  649. release_firmware(cdev->firmware);
  650. return rc;
  651. }
  652. static int qed_slowpath_stop(struct qed_dev *cdev)
  653. {
  654. if (!cdev)
  655. return -ENODEV;
  656. qed_free_stream_mem(cdev);
  657. qed_nic_stop(cdev);
  658. qed_slowpath_irq_free(cdev);
  659. qed_disable_msix(cdev);
  660. qed_nic_reset(cdev);
  661. release_firmware(cdev->firmware);
  662. return 0;
  663. }
  664. static void qed_set_id(struct qed_dev *cdev, char name[NAME_SIZE],
  665. char ver_str[VER_SIZE])
  666. {
  667. int i;
  668. memcpy(cdev->name, name, NAME_SIZE);
  669. for_each_hwfn(cdev, i)
  670. snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i);
  671. memcpy(cdev->ver_str, ver_str, VER_SIZE);
  672. cdev->drv_type = DRV_ID_DRV_TYPE_LINUX;
  673. }
  674. static u32 qed_sb_init(struct qed_dev *cdev,
  675. struct qed_sb_info *sb_info,
  676. void *sb_virt_addr,
  677. dma_addr_t sb_phy_addr, u16 sb_id,
  678. enum qed_sb_type type)
  679. {
  680. struct qed_hwfn *p_hwfn;
  681. int hwfn_index;
  682. u16 rel_sb_id;
  683. u8 n_hwfns;
  684. u32 rc;
  685. /* RoCE uses single engine and CMT uses two engines. When using both
  686. * we force only a single engine. Storage uses only engine 0 too.
  687. */
  688. if (type == QED_SB_TYPE_L2_QUEUE)
  689. n_hwfns = cdev->num_hwfns;
  690. else
  691. n_hwfns = 1;
  692. hwfn_index = sb_id % n_hwfns;
  693. p_hwfn = &cdev->hwfns[hwfn_index];
  694. rel_sb_id = sb_id / n_hwfns;
  695. DP_VERBOSE(cdev, NETIF_MSG_INTR,
  696. "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
  697. hwfn_index, rel_sb_id, sb_id);
  698. rc = qed_int_sb_init(p_hwfn, p_hwfn->p_main_ptt, sb_info,
  699. sb_virt_addr, sb_phy_addr, rel_sb_id);
  700. return rc;
  701. }
  702. static u32 qed_sb_release(struct qed_dev *cdev,
  703. struct qed_sb_info *sb_info,
  704. u16 sb_id)
  705. {
  706. struct qed_hwfn *p_hwfn;
  707. int hwfn_index;
  708. u16 rel_sb_id;
  709. u32 rc;
  710. hwfn_index = sb_id % cdev->num_hwfns;
  711. p_hwfn = &cdev->hwfns[hwfn_index];
  712. rel_sb_id = sb_id / cdev->num_hwfns;
  713. DP_VERBOSE(cdev, NETIF_MSG_INTR,
  714. "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
  715. hwfn_index, rel_sb_id, sb_id);
  716. rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id);
  717. return rc;
  718. }
  719. static int qed_set_link(struct qed_dev *cdev,
  720. struct qed_link_params *params)
  721. {
  722. struct qed_hwfn *hwfn;
  723. struct qed_mcp_link_params *link_params;
  724. struct qed_ptt *ptt;
  725. int rc;
  726. if (!cdev)
  727. return -ENODEV;
  728. /* The link should be set only once per PF */
  729. hwfn = &cdev->hwfns[0];
  730. ptt = qed_ptt_acquire(hwfn);
  731. if (!ptt)
  732. return -EBUSY;
  733. link_params = qed_mcp_get_link_params(hwfn);
  734. if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG)
  735. link_params->speed.autoneg = params->autoneg;
  736. if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) {
  737. link_params->speed.advertised_speeds = 0;
  738. if ((params->adv_speeds & SUPPORTED_1000baseT_Half) ||
  739. (params->adv_speeds & SUPPORTED_1000baseT_Full))
  740. link_params->speed.advertised_speeds |=
  741. NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
  742. if (params->adv_speeds & SUPPORTED_10000baseKR_Full)
  743. link_params->speed.advertised_speeds |=
  744. NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
  745. if (params->adv_speeds & SUPPORTED_40000baseLR4_Full)
  746. link_params->speed.advertised_speeds |=
  747. NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G;
  748. if (params->adv_speeds & 0)
  749. link_params->speed.advertised_speeds |=
  750. NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G;
  751. if (params->adv_speeds & 0)
  752. link_params->speed.advertised_speeds |=
  753. NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G;
  754. }
  755. if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED)
  756. link_params->speed.forced_speed = params->forced_speed;
  757. rc = qed_mcp_set_link(hwfn, ptt, params->link_up);
  758. qed_ptt_release(hwfn, ptt);
  759. return rc;
  760. }
  761. static int qed_get_port_type(u32 media_type)
  762. {
  763. int port_type;
  764. switch (media_type) {
  765. case MEDIA_SFPP_10G_FIBER:
  766. case MEDIA_SFP_1G_FIBER:
  767. case MEDIA_XFP_FIBER:
  768. case MEDIA_KR:
  769. port_type = PORT_FIBRE;
  770. break;
  771. case MEDIA_DA_TWINAX:
  772. port_type = PORT_DA;
  773. break;
  774. case MEDIA_BASE_T:
  775. port_type = PORT_TP;
  776. break;
  777. case MEDIA_NOT_PRESENT:
  778. port_type = PORT_NONE;
  779. break;
  780. case MEDIA_UNSPECIFIED:
  781. default:
  782. port_type = PORT_OTHER;
  783. break;
  784. }
  785. return port_type;
  786. }
  787. static void qed_fill_link(struct qed_hwfn *hwfn,
  788. struct qed_link_output *if_link)
  789. {
  790. struct qed_mcp_link_params params;
  791. struct qed_mcp_link_state link;
  792. struct qed_mcp_link_capabilities link_caps;
  793. u32 media_type;
  794. memset(if_link, 0, sizeof(*if_link));
  795. /* Prepare source inputs */
  796. memcpy(&params, qed_mcp_get_link_params(hwfn), sizeof(params));
  797. memcpy(&link, qed_mcp_get_link_state(hwfn), sizeof(link));
  798. memcpy(&link_caps, qed_mcp_get_link_capabilities(hwfn),
  799. sizeof(link_caps));
  800. /* Set the link parameters to pass to protocol driver */
  801. if (link.link_up)
  802. if_link->link_up = true;
  803. /* TODO - at the moment assume supported and advertised speed equal */
  804. if_link->supported_caps = SUPPORTED_FIBRE;
  805. if (params.speed.autoneg)
  806. if_link->supported_caps |= SUPPORTED_Autoneg;
  807. if (params.pause.autoneg ||
  808. (params.pause.forced_rx && params.pause.forced_tx))
  809. if_link->supported_caps |= SUPPORTED_Asym_Pause;
  810. if (params.pause.autoneg || params.pause.forced_rx ||
  811. params.pause.forced_tx)
  812. if_link->supported_caps |= SUPPORTED_Pause;
  813. if_link->advertised_caps = if_link->supported_caps;
  814. if (params.speed.advertised_speeds &
  815. NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
  816. if_link->advertised_caps |= SUPPORTED_1000baseT_Half |
  817. SUPPORTED_1000baseT_Full;
  818. if (params.speed.advertised_speeds &
  819. NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
  820. if_link->advertised_caps |= SUPPORTED_10000baseKR_Full;
  821. if (params.speed.advertised_speeds &
  822. NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
  823. if_link->advertised_caps |= SUPPORTED_40000baseLR4_Full;
  824. if (params.speed.advertised_speeds &
  825. NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
  826. if_link->advertised_caps |= 0;
  827. if (params.speed.advertised_speeds &
  828. NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G)
  829. if_link->advertised_caps |= 0;
  830. if (link_caps.speed_capabilities &
  831. NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
  832. if_link->supported_caps |= SUPPORTED_1000baseT_Half |
  833. SUPPORTED_1000baseT_Full;
  834. if (link_caps.speed_capabilities &
  835. NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
  836. if_link->supported_caps |= SUPPORTED_10000baseKR_Full;
  837. if (link_caps.speed_capabilities &
  838. NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
  839. if_link->supported_caps |= SUPPORTED_40000baseLR4_Full;
  840. if (link_caps.speed_capabilities &
  841. NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
  842. if_link->supported_caps |= 0;
  843. if (link_caps.speed_capabilities &
  844. NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G)
  845. if_link->supported_caps |= 0;
  846. if (link.link_up)
  847. if_link->speed = link.speed;
  848. /* TODO - fill duplex properly */
  849. if_link->duplex = DUPLEX_FULL;
  850. qed_mcp_get_media_type(hwfn->cdev, &media_type);
  851. if_link->port = qed_get_port_type(media_type);
  852. if_link->autoneg = params.speed.autoneg;
  853. if (params.pause.autoneg)
  854. if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
  855. if (params.pause.forced_rx)
  856. if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE;
  857. if (params.pause.forced_tx)
  858. if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE;
  859. /* Link partner capabilities */
  860. if (link.partner_adv_speed &
  861. QED_LINK_PARTNER_SPEED_1G_HD)
  862. if_link->lp_caps |= SUPPORTED_1000baseT_Half;
  863. if (link.partner_adv_speed &
  864. QED_LINK_PARTNER_SPEED_1G_FD)
  865. if_link->lp_caps |= SUPPORTED_1000baseT_Full;
  866. if (link.partner_adv_speed &
  867. QED_LINK_PARTNER_SPEED_10G)
  868. if_link->lp_caps |= SUPPORTED_10000baseKR_Full;
  869. if (link.partner_adv_speed &
  870. QED_LINK_PARTNER_SPEED_40G)
  871. if_link->lp_caps |= SUPPORTED_40000baseLR4_Full;
  872. if (link.partner_adv_speed &
  873. QED_LINK_PARTNER_SPEED_50G)
  874. if_link->lp_caps |= 0;
  875. if (link.partner_adv_speed &
  876. QED_LINK_PARTNER_SPEED_100G)
  877. if_link->lp_caps |= 0;
  878. if (link.an_complete)
  879. if_link->lp_caps |= SUPPORTED_Autoneg;
  880. if (link.partner_adv_pause)
  881. if_link->lp_caps |= SUPPORTED_Pause;
  882. if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE ||
  883. link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE)
  884. if_link->lp_caps |= SUPPORTED_Asym_Pause;
  885. }
  886. static void qed_get_current_link(struct qed_dev *cdev,
  887. struct qed_link_output *if_link)
  888. {
  889. qed_fill_link(&cdev->hwfns[0], if_link);
  890. }
  891. void qed_link_update(struct qed_hwfn *hwfn)
  892. {
  893. void *cookie = hwfn->cdev->ops_cookie;
  894. struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common;
  895. struct qed_link_output if_link;
  896. qed_fill_link(hwfn, &if_link);
  897. if (IS_LEAD_HWFN(hwfn) && cookie)
  898. op->link_update(cookie, &if_link);
  899. }
  900. static int qed_drain(struct qed_dev *cdev)
  901. {
  902. struct qed_hwfn *hwfn;
  903. struct qed_ptt *ptt;
  904. int i, rc;
  905. for_each_hwfn(cdev, i) {
  906. hwfn = &cdev->hwfns[i];
  907. ptt = qed_ptt_acquire(hwfn);
  908. if (!ptt) {
  909. DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n");
  910. return -EBUSY;
  911. }
  912. rc = qed_mcp_drain(hwfn, ptt);
  913. qed_ptt_release(hwfn, ptt);
  914. if (rc)
  915. return rc;
  916. }
  917. return 0;
  918. }
  919. const struct qed_common_ops qed_common_ops_pass = {
  920. .probe = &qed_probe,
  921. .remove = &qed_remove,
  922. .set_power_state = &qed_set_power_state,
  923. .set_id = &qed_set_id,
  924. .update_pf_params = &qed_update_pf_params,
  925. .slowpath_start = &qed_slowpath_start,
  926. .slowpath_stop = &qed_slowpath_stop,
  927. .set_fp_int = &qed_set_int_fp,
  928. .get_fp_int = &qed_get_int_fp,
  929. .sb_init = &qed_sb_init,
  930. .sb_release = &qed_sb_release,
  931. .simd_handler_config = &qed_simd_handler_config,
  932. .simd_handler_clean = &qed_simd_handler_clean,
  933. .set_link = &qed_set_link,
  934. .get_link = &qed_get_current_link,
  935. .drain = &qed_drain,
  936. .update_msglvl = &qed_init_dp,
  937. .chain_alloc = &qed_chain_alloc,
  938. .chain_free = &qed_chain_free,
  939. };
  940. u32 qed_get_protocol_version(enum qed_protocol protocol)
  941. {
  942. switch (protocol) {
  943. case QED_PROTOCOL_ETH:
  944. return QED_ETH_INTERFACE_VERSION;
  945. default:
  946. return 0;
  947. }
  948. }
  949. EXPORT_SYMBOL(qed_get_protocol_version);