ether3.h 4.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176
  1. /*
  2. * linux/drivers/acorn/net/ether3.h
  3. *
  4. * Copyright (C) 1995-2000 Russell King
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * network driver for Acorn/ANT Ether3 cards
  11. */
  12. #ifndef _LINUX_ether3_H
  13. #define _LINUX_ether3_H
  14. /* use 0 for production, 1 for verification, >2 for debug. debug flags: */
  15. #define DEBUG_TX 2
  16. #define DEBUG_RX 4
  17. #define DEBUG_INT 8
  18. #define DEBUG_IC 16
  19. #ifndef NET_DEBUG
  20. #define NET_DEBUG 0
  21. #endif
  22. #define priv(dev) ((struct dev_priv *)netdev_priv(dev))
  23. /* Command register definitions & bits */
  24. #define REG_COMMAND (priv(dev)->seeq + 0x0000)
  25. #define CMD_ENINTDMA 0x0001
  26. #define CMD_ENINTRX 0x0002
  27. #define CMD_ENINTTX 0x0004
  28. #define CMD_ENINTBUFWIN 0x0008
  29. #define CMD_ACKINTDMA 0x0010
  30. #define CMD_ACKINTRX 0x0020
  31. #define CMD_ACKINTTX 0x0040
  32. #define CMD_ACKINTBUFWIN 0x0080
  33. #define CMD_DMAON 0x0100
  34. #define CMD_RXON 0x0200
  35. #define CMD_TXON 0x0400
  36. #define CMD_DMAOFF 0x0800
  37. #define CMD_RXOFF 0x1000
  38. #define CMD_TXOFF 0x2000
  39. #define CMD_FIFOREAD 0x4000
  40. #define CMD_FIFOWRITE 0x8000
  41. /* status register */
  42. #define REG_STATUS (priv(dev)->seeq + 0x0000)
  43. #define STAT_ENINTSTAT 0x0001
  44. #define STAT_ENINTRX 0x0002
  45. #define STAT_ENINTTX 0x0004
  46. #define STAT_ENINTBUFWIN 0x0008
  47. #define STAT_INTDMA 0x0010
  48. #define STAT_INTRX 0x0020
  49. #define STAT_INTTX 0x0040
  50. #define STAT_INTBUFWIN 0x0080
  51. #define STAT_DMAON 0x0100
  52. #define STAT_RXON 0x0200
  53. #define STAT_TXON 0x0400
  54. #define STAT_FIFOFULL 0x2000
  55. #define STAT_FIFOEMPTY 0x4000
  56. #define STAT_FIFODIR 0x8000
  57. /* configuration register 1 */
  58. #define REG_CONFIG1 (priv(dev)->seeq + 0x0040)
  59. #define CFG1_BUFSELSTAT0 0x0000
  60. #define CFG1_BUFSELSTAT1 0x0001
  61. #define CFG1_BUFSELSTAT2 0x0002
  62. #define CFG1_BUFSELSTAT3 0x0003
  63. #define CFG1_BUFSELSTAT4 0x0004
  64. #define CFG1_BUFSELSTAT5 0x0005
  65. #define CFG1_ADDRPROM 0x0006
  66. #define CFG1_TRANSEND 0x0007
  67. #define CFG1_LOCBUFMEM 0x0008
  68. #define CFG1_INTVECTOR 0x0009
  69. #define CFG1_RECVSPECONLY 0x0000
  70. #define CFG1_RECVSPECBROAD 0x4000
  71. #define CFG1_RECVSPECBRMULTI 0x8000
  72. #define CFG1_RECVPROMISC 0xC000
  73. /* The following aren't in 8004 */
  74. #define CFG1_DMABURSTCONT 0x0000
  75. #define CFG1_DMABURST800NS 0x0010
  76. #define CFG1_DMABURST1600NS 0x0020
  77. #define CFG1_DMABURST3200NS 0x0030
  78. #define CFG1_DMABURST1 0x0000
  79. #define CFG1_DMABURST4 0x0040
  80. #define CFG1_DMABURST8 0x0080
  81. #define CFG1_DMABURST16 0x00C0
  82. #define CFG1_RECVCOMPSTAT0 0x0100
  83. #define CFG1_RECVCOMPSTAT1 0x0200
  84. #define CFG1_RECVCOMPSTAT2 0x0400
  85. #define CFG1_RECVCOMPSTAT3 0x0800
  86. #define CFG1_RECVCOMPSTAT4 0x1000
  87. #define CFG1_RECVCOMPSTAT5 0x2000
  88. /* configuration register 2 */
  89. #define REG_CONFIG2 (priv(dev)->seeq + 0x0080)
  90. #define CFG2_BYTESWAP 0x0001
  91. #define CFG2_ERRENCRC 0x0008
  92. #define CFG2_ERRENDRIBBLE 0x0010
  93. #define CFG2_ERRSHORTFRAME 0x0020
  94. #define CFG2_SLOTSELECT 0x0040
  95. #define CFG2_PREAMSELECT 0x0080
  96. #define CFG2_ADDRLENGTH 0x0100
  97. #define CFG2_RECVCRC 0x0200
  98. #define CFG2_XMITNOCRC 0x0400
  99. #define CFG2_LOOPBACK 0x0800
  100. #define CFG2_CTRLO 0x1000
  101. #define CFG2_RESET 0x8000
  102. #define REG_RECVEND (priv(dev)->seeq + 0x00c0)
  103. #define REG_BUFWIN (priv(dev)->seeq + 0x0100)
  104. #define REG_RECVPTR (priv(dev)->seeq + 0x0140)
  105. #define REG_TRANSMITPTR (priv(dev)->seeq + 0x0180)
  106. #define REG_DMAADDR (priv(dev)->seeq + 0x01c0)
  107. /*
  108. * Cards transmit/receive headers
  109. */
  110. #define TX_NEXT (0xffff)
  111. #define TXHDR_ENBABBLEINT (1 << 16)
  112. #define TXHDR_ENCOLLISIONINT (1 << 17)
  113. #define TXHDR_EN16COLLISION (1 << 18)
  114. #define TXHDR_ENSUCCESS (1 << 19)
  115. #define TXHDR_DATAFOLLOWS (1 << 21)
  116. #define TXHDR_CHAINCONTINUE (1 << 22)
  117. #define TXHDR_TRANSMIT (1 << 23)
  118. #define TXSTAT_BABBLED (1 << 24)
  119. #define TXSTAT_COLLISION (1 << 25)
  120. #define TXSTAT_16COLLISIONS (1 << 26)
  121. #define TXSTAT_DONE (1 << 31)
  122. #define RX_NEXT (0xffff)
  123. #define RXHDR_CHAINCONTINUE (1 << 6)
  124. #define RXHDR_RECEIVE (1 << 7)
  125. #define RXSTAT_OVERSIZE (1 << 8)
  126. #define RXSTAT_CRCERROR (1 << 9)
  127. #define RXSTAT_DRIBBLEERROR (1 << 10)
  128. #define RXSTAT_SHORTPACKET (1 << 11)
  129. #define RXSTAT_DONE (1 << 15)
  130. #define TX_START 0x0000
  131. #define TX_END 0x6000
  132. #define RX_START 0x6000
  133. #define RX_LEN 0xA000
  134. #define RX_END 0x10000
  135. /* must be a power of 2 and greater than MAX_TX_BUFFERED */
  136. #define MAX_TXED 16
  137. #define MAX_TX_BUFFERED 10
  138. struct dev_priv {
  139. void __iomem *base;
  140. void __iomem *seeq;
  141. struct {
  142. unsigned int command;
  143. unsigned int config1;
  144. unsigned int config2;
  145. } regs;
  146. unsigned char tx_head; /* buffer nr to insert next packet */
  147. unsigned char tx_tail; /* buffer nr of transmitting packet */
  148. unsigned int rx_head; /* address to fetch next packet from */
  149. struct timer_list timer;
  150. int broken; /* 0 = ok, 1 = something went wrong */
  151. };
  152. struct ether3_data {
  153. const char name[8];
  154. unsigned long base_offset;
  155. };
  156. #endif