dwmac100_core.c 6.1 KB

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  1. /*******************************************************************************
  2. This is the driver for the MAC 10/100 on-chip Ethernet controller
  3. currently tested on all the ST boards based on STb7109 and stx7200 SoCs.
  4. DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
  5. this code.
  6. This only implements the mac core functions for this chip.
  7. Copyright (C) 2007-2009 STMicroelectronics Ltd
  8. This program is free software; you can redistribute it and/or modify it
  9. under the terms and conditions of the GNU General Public License,
  10. version 2, as published by the Free Software Foundation.
  11. This program is distributed in the hope it will be useful, but WITHOUT
  12. ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. more details.
  15. You should have received a copy of the GNU General Public License along with
  16. this program; if not, write to the Free Software Foundation, Inc.,
  17. 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18. The full GNU General Public License is included in this distribution in
  19. the file called "COPYING".
  20. Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  21. *******************************************************************************/
  22. #include <linux/crc32.h>
  23. #include <asm/io.h>
  24. #include "dwmac100.h"
  25. static void dwmac100_core_init(struct mac_device_info *hw, int mtu)
  26. {
  27. void __iomem *ioaddr = hw->pcsr;
  28. u32 value = readl(ioaddr + MAC_CONTROL);
  29. writel((value | MAC_CORE_INIT), ioaddr + MAC_CONTROL);
  30. #ifdef STMMAC_VLAN_TAG_USED
  31. writel(ETH_P_8021Q, ioaddr + MAC_VLAN1);
  32. #endif
  33. }
  34. static void dwmac100_dump_mac_regs(struct mac_device_info *hw)
  35. {
  36. void __iomem *ioaddr = hw->pcsr;
  37. pr_info("\t----------------------------------------------\n"
  38. "\t DWMAC 100 CSR (base addr = 0x%p)\n"
  39. "\t----------------------------------------------\n", ioaddr);
  40. pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL,
  41. readl(ioaddr + MAC_CONTROL));
  42. pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH,
  43. readl(ioaddr + MAC_ADDR_HIGH));
  44. pr_info("\taddr LO (offset 0x%x): 0x%08x\n", MAC_ADDR_LOW,
  45. readl(ioaddr + MAC_ADDR_LOW));
  46. pr_info("\tmulticast hash HI (offset 0x%x): 0x%08x\n",
  47. MAC_HASH_HIGH, readl(ioaddr + MAC_HASH_HIGH));
  48. pr_info("\tmulticast hash LO (offset 0x%x): 0x%08x\n",
  49. MAC_HASH_LOW, readl(ioaddr + MAC_HASH_LOW));
  50. pr_info("\tflow control (offset 0x%x): 0x%08x\n",
  51. MAC_FLOW_CTRL, readl(ioaddr + MAC_FLOW_CTRL));
  52. pr_info("\tVLAN1 tag (offset 0x%x): 0x%08x\n", MAC_VLAN1,
  53. readl(ioaddr + MAC_VLAN1));
  54. pr_info("\tVLAN2 tag (offset 0x%x): 0x%08x\n", MAC_VLAN2,
  55. readl(ioaddr + MAC_VLAN2));
  56. }
  57. static int dwmac100_rx_ipc_enable(struct mac_device_info *hw)
  58. {
  59. return 0;
  60. }
  61. static int dwmac100_irq_status(struct mac_device_info *hw,
  62. struct stmmac_extra_stats *x)
  63. {
  64. return 0;
  65. }
  66. static void dwmac100_set_umac_addr(struct mac_device_info *hw,
  67. unsigned char *addr,
  68. unsigned int reg_n)
  69. {
  70. void __iomem *ioaddr = hw->pcsr;
  71. stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
  72. }
  73. static void dwmac100_get_umac_addr(struct mac_device_info *hw,
  74. unsigned char *addr,
  75. unsigned int reg_n)
  76. {
  77. void __iomem *ioaddr = hw->pcsr;
  78. stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
  79. }
  80. static void dwmac100_set_filter(struct mac_device_info *hw,
  81. struct net_device *dev)
  82. {
  83. void __iomem *ioaddr = (void __iomem *)dev->base_addr;
  84. u32 value = readl(ioaddr + MAC_CONTROL);
  85. if (dev->flags & IFF_PROMISC) {
  86. value |= MAC_CONTROL_PR;
  87. value &= ~(MAC_CONTROL_PM | MAC_CONTROL_IF | MAC_CONTROL_HO |
  88. MAC_CONTROL_HP);
  89. } else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
  90. || (dev->flags & IFF_ALLMULTI)) {
  91. value |= MAC_CONTROL_PM;
  92. value &= ~(MAC_CONTROL_PR | MAC_CONTROL_IF | MAC_CONTROL_HO);
  93. writel(0xffffffff, ioaddr + MAC_HASH_HIGH);
  94. writel(0xffffffff, ioaddr + MAC_HASH_LOW);
  95. } else if (netdev_mc_empty(dev)) { /* no multicast */
  96. value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | MAC_CONTROL_IF |
  97. MAC_CONTROL_HO | MAC_CONTROL_HP);
  98. } else {
  99. u32 mc_filter[2];
  100. struct netdev_hw_addr *ha;
  101. /* Perfect filter mode for physical address and Hash
  102. * filter for multicast
  103. */
  104. value |= MAC_CONTROL_HP;
  105. value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR |
  106. MAC_CONTROL_IF | MAC_CONTROL_HO);
  107. memset(mc_filter, 0, sizeof(mc_filter));
  108. netdev_for_each_mc_addr(ha, dev) {
  109. /* The upper 6 bits of the calculated CRC are used to
  110. * index the contens of the hash table
  111. */
  112. int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
  113. /* The most significant bit determines the register to
  114. * use (H/L) while the other 5 bits determine the bit
  115. * within the register.
  116. */
  117. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  118. }
  119. writel(mc_filter[0], ioaddr + MAC_HASH_LOW);
  120. writel(mc_filter[1], ioaddr + MAC_HASH_HIGH);
  121. }
  122. writel(value, ioaddr + MAC_CONTROL);
  123. }
  124. static void dwmac100_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
  125. unsigned int fc, unsigned int pause_time)
  126. {
  127. void __iomem *ioaddr = hw->pcsr;
  128. unsigned int flow = MAC_FLOW_CTRL_ENABLE;
  129. if (duplex)
  130. flow |= (pause_time << MAC_FLOW_CTRL_PT_SHIFT);
  131. writel(flow, ioaddr + MAC_FLOW_CTRL);
  132. }
  133. /* No PMT module supported on ST boards with this Eth chip. */
  134. static void dwmac100_pmt(struct mac_device_info *hw, unsigned long mode)
  135. {
  136. return;
  137. }
  138. static const struct stmmac_ops dwmac100_ops = {
  139. .core_init = dwmac100_core_init,
  140. .rx_ipc = dwmac100_rx_ipc_enable,
  141. .dump_regs = dwmac100_dump_mac_regs,
  142. .host_irq_status = dwmac100_irq_status,
  143. .set_filter = dwmac100_set_filter,
  144. .flow_ctrl = dwmac100_flow_ctrl,
  145. .pmt = dwmac100_pmt,
  146. .set_umac_addr = dwmac100_set_umac_addr,
  147. .get_umac_addr = dwmac100_get_umac_addr,
  148. };
  149. struct mac_device_info *dwmac100_setup(void __iomem *ioaddr)
  150. {
  151. struct mac_device_info *mac;
  152. mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
  153. if (!mac)
  154. return NULL;
  155. pr_info("\tDWMAC100\n");
  156. mac->pcsr = ioaddr;
  157. mac->mac = &dwmac100_ops;
  158. mac->dma = &dwmac100_dma_ops;
  159. mac->link.port = MAC_CONTROL_PS;
  160. mac->link.duplex = MAC_CONTROL_F;
  161. mac->link.speed = 0;
  162. mac->mii.addr = MAC_MII_ADDR;
  163. mac->mii.data = MAC_MII_DATA;
  164. mac->synopsys_uid = 0;
  165. return mac;
  166. }