enh_desc.c 11 KB

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  1. /*******************************************************************************
  2. This contains the functions to handle the enhanced descriptors.
  3. Copyright (C) 2007-2009 STMicroelectronics Ltd
  4. This program is free software; you can redistribute it and/or modify it
  5. under the terms and conditions of the GNU General Public License,
  6. version 2, as published by the Free Software Foundation.
  7. This program is distributed in the hope it will be useful, but WITHOUT
  8. ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  9. FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  10. more details.
  11. You should have received a copy of the GNU General Public License along with
  12. this program; if not, write to the Free Software Foundation, Inc.,
  13. 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  14. The full GNU General Public License is included in this distribution in
  15. the file called "COPYING".
  16. Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  17. *******************************************************************************/
  18. #include <linux/stmmac.h>
  19. #include "common.h"
  20. #include "descs_com.h"
  21. static int enh_desc_get_tx_status(void *data, struct stmmac_extra_stats *x,
  22. struct dma_desc *p, void __iomem *ioaddr)
  23. {
  24. int ret = 0;
  25. struct net_device_stats *stats = (struct net_device_stats *)data;
  26. if (unlikely(p->des01.etx.error_summary)) {
  27. if (unlikely(p->des01.etx.jabber_timeout))
  28. x->tx_jabber++;
  29. if (unlikely(p->des01.etx.frame_flushed)) {
  30. x->tx_frame_flushed++;
  31. dwmac_dma_flush_tx_fifo(ioaddr);
  32. }
  33. if (unlikely(p->des01.etx.loss_carrier)) {
  34. x->tx_losscarrier++;
  35. stats->tx_carrier_errors++;
  36. }
  37. if (unlikely(p->des01.etx.no_carrier)) {
  38. x->tx_carrier++;
  39. stats->tx_carrier_errors++;
  40. }
  41. if (unlikely(p->des01.etx.late_collision))
  42. stats->collisions += p->des01.etx.collision_count;
  43. if (unlikely(p->des01.etx.excessive_collisions))
  44. stats->collisions += p->des01.etx.collision_count;
  45. if (unlikely(p->des01.etx.excessive_deferral))
  46. x->tx_deferred++;
  47. if (unlikely(p->des01.etx.underflow_error)) {
  48. dwmac_dma_flush_tx_fifo(ioaddr);
  49. x->tx_underflow++;
  50. }
  51. if (unlikely(p->des01.etx.ip_header_error))
  52. x->tx_ip_header_error++;
  53. if (unlikely(p->des01.etx.payload_error)) {
  54. x->tx_payload_error++;
  55. dwmac_dma_flush_tx_fifo(ioaddr);
  56. }
  57. ret = -1;
  58. }
  59. if (unlikely(p->des01.etx.deferred))
  60. x->tx_deferred++;
  61. #ifdef STMMAC_VLAN_TAG_USED
  62. if (p->des01.etx.vlan_frame)
  63. x->tx_vlan++;
  64. #endif
  65. return ret;
  66. }
  67. static int enh_desc_get_tx_len(struct dma_desc *p)
  68. {
  69. return p->des01.etx.buffer1_size;
  70. }
  71. static int enh_desc_coe_rdes0(int ipc_err, int type, int payload_err)
  72. {
  73. int ret = good_frame;
  74. u32 status = (type << 2 | ipc_err << 1 | payload_err) & 0x7;
  75. /* bits 5 7 0 | Frame status
  76. * ----------------------------------------------------------
  77. * 0 0 0 | IEEE 802.3 Type frame (length < 1536 octects)
  78. * 1 0 0 | IPv4/6 No CSUM errorS.
  79. * 1 0 1 | IPv4/6 CSUM PAYLOAD error
  80. * 1 1 0 | IPv4/6 CSUM IP HR error
  81. * 1 1 1 | IPv4/6 IP PAYLOAD AND HEADER errorS
  82. * 0 0 1 | IPv4/6 unsupported IP PAYLOAD
  83. * 0 1 1 | COE bypassed.. no IPv4/6 frame
  84. * 0 1 0 | Reserved.
  85. */
  86. if (status == 0x0)
  87. ret = llc_snap;
  88. else if (status == 0x4)
  89. ret = good_frame;
  90. else if (status == 0x5)
  91. ret = csum_none;
  92. else if (status == 0x6)
  93. ret = csum_none;
  94. else if (status == 0x7)
  95. ret = csum_none;
  96. else if (status == 0x1)
  97. ret = discard_frame;
  98. else if (status == 0x3)
  99. ret = discard_frame;
  100. return ret;
  101. }
  102. static void enh_desc_get_ext_status(void *data, struct stmmac_extra_stats *x,
  103. struct dma_extended_desc *p)
  104. {
  105. if (unlikely(p->basic.des01.erx.rx_mac_addr)) {
  106. if (p->des4.erx.ip_hdr_err)
  107. x->ip_hdr_err++;
  108. if (p->des4.erx.ip_payload_err)
  109. x->ip_payload_err++;
  110. if (p->des4.erx.ip_csum_bypassed)
  111. x->ip_csum_bypassed++;
  112. if (p->des4.erx.ipv4_pkt_rcvd)
  113. x->ipv4_pkt_rcvd++;
  114. if (p->des4.erx.ipv6_pkt_rcvd)
  115. x->ipv6_pkt_rcvd++;
  116. if (p->des4.erx.msg_type == RDES_EXT_SYNC)
  117. x->rx_msg_type_sync++;
  118. else if (p->des4.erx.msg_type == RDES_EXT_FOLLOW_UP)
  119. x->rx_msg_type_follow_up++;
  120. else if (p->des4.erx.msg_type == RDES_EXT_DELAY_REQ)
  121. x->rx_msg_type_delay_req++;
  122. else if (p->des4.erx.msg_type == RDES_EXT_DELAY_RESP)
  123. x->rx_msg_type_delay_resp++;
  124. else if (p->des4.erx.msg_type == RDES_EXT_PDELAY_REQ)
  125. x->rx_msg_type_pdelay_req++;
  126. else if (p->des4.erx.msg_type == RDES_EXT_PDELAY_RESP)
  127. x->rx_msg_type_pdelay_resp++;
  128. else if (p->des4.erx.msg_type == RDES_EXT_PDELAY_FOLLOW_UP)
  129. x->rx_msg_type_pdelay_follow_up++;
  130. else
  131. x->rx_msg_type_ext_no_ptp++;
  132. if (p->des4.erx.ptp_frame_type)
  133. x->ptp_frame_type++;
  134. if (p->des4.erx.ptp_ver)
  135. x->ptp_ver++;
  136. if (p->des4.erx.timestamp_dropped)
  137. x->timestamp_dropped++;
  138. if (p->des4.erx.av_pkt_rcvd)
  139. x->av_pkt_rcvd++;
  140. if (p->des4.erx.av_tagged_pkt_rcvd)
  141. x->av_tagged_pkt_rcvd++;
  142. if (p->des4.erx.vlan_tag_priority_val)
  143. x->vlan_tag_priority_val++;
  144. if (p->des4.erx.l3_filter_match)
  145. x->l3_filter_match++;
  146. if (p->des4.erx.l4_filter_match)
  147. x->l4_filter_match++;
  148. if (p->des4.erx.l3_l4_filter_no_match)
  149. x->l3_l4_filter_no_match++;
  150. }
  151. }
  152. static int enh_desc_get_rx_status(void *data, struct stmmac_extra_stats *x,
  153. struct dma_desc *p)
  154. {
  155. int ret = good_frame;
  156. struct net_device_stats *stats = (struct net_device_stats *)data;
  157. if (unlikely(p->des01.erx.error_summary)) {
  158. if (unlikely(p->des01.erx.descriptor_error)) {
  159. x->rx_desc++;
  160. stats->rx_length_errors++;
  161. }
  162. if (unlikely(p->des01.erx.overflow_error))
  163. x->rx_gmac_overflow++;
  164. if (unlikely(p->des01.erx.ipc_csum_error))
  165. pr_err("\tIPC Csum Error/Giant frame\n");
  166. if (unlikely(p->des01.erx.late_collision)) {
  167. stats->collisions++;
  168. }
  169. if (unlikely(p->des01.erx.receive_watchdog))
  170. x->rx_watchdog++;
  171. if (unlikely(p->des01.erx.error_gmii))
  172. x->rx_mii++;
  173. if (unlikely(p->des01.erx.crc_error)) {
  174. x->rx_crc++;
  175. stats->rx_crc_errors++;
  176. }
  177. ret = discard_frame;
  178. }
  179. /* After a payload csum error, the ES bit is set.
  180. * It doesn't match with the information reported into the databook.
  181. * At any rate, we need to understand if the CSUM hw computation is ok
  182. * and report this info to the upper layers. */
  183. ret = enh_desc_coe_rdes0(p->des01.erx.ipc_csum_error,
  184. p->des01.erx.frame_type, p->des01.erx.rx_mac_addr);
  185. if (unlikely(p->des01.erx.dribbling))
  186. x->dribbling_bit++;
  187. if (unlikely(p->des01.erx.sa_filter_fail)) {
  188. x->sa_rx_filter_fail++;
  189. ret = discard_frame;
  190. }
  191. if (unlikely(p->des01.erx.da_filter_fail)) {
  192. x->da_rx_filter_fail++;
  193. ret = discard_frame;
  194. }
  195. if (unlikely(p->des01.erx.length_error)) {
  196. x->rx_length++;
  197. ret = discard_frame;
  198. }
  199. #ifdef STMMAC_VLAN_TAG_USED
  200. if (p->des01.erx.vlan_tag)
  201. x->rx_vlan++;
  202. #endif
  203. return ret;
  204. }
  205. static void enh_desc_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
  206. int mode, int end)
  207. {
  208. p->des01.all_flags = 0;
  209. p->des01.erx.own = 1;
  210. p->des01.erx.buffer1_size = BUF_SIZE_8KiB - 1;
  211. if (mode == STMMAC_CHAIN_MODE)
  212. ehn_desc_rx_set_on_chain(p, end);
  213. else
  214. ehn_desc_rx_set_on_ring(p, end);
  215. if (disable_rx_ic)
  216. p->des01.erx.disable_ic = 1;
  217. }
  218. static void enh_desc_init_tx_desc(struct dma_desc *p, int mode, int end)
  219. {
  220. p->des01.all_flags = 0;
  221. if (mode == STMMAC_CHAIN_MODE)
  222. ehn_desc_tx_set_on_chain(p, end);
  223. else
  224. ehn_desc_tx_set_on_ring(p, end);
  225. }
  226. static int enh_desc_get_tx_owner(struct dma_desc *p)
  227. {
  228. return p->des01.etx.own;
  229. }
  230. static int enh_desc_get_rx_owner(struct dma_desc *p)
  231. {
  232. return p->des01.erx.own;
  233. }
  234. static void enh_desc_set_tx_owner(struct dma_desc *p)
  235. {
  236. p->des01.etx.own = 1;
  237. }
  238. static void enh_desc_set_rx_owner(struct dma_desc *p)
  239. {
  240. p->des01.erx.own = 1;
  241. }
  242. static int enh_desc_get_tx_ls(struct dma_desc *p)
  243. {
  244. return p->des01.etx.last_segment;
  245. }
  246. static void enh_desc_release_tx_desc(struct dma_desc *p, int mode)
  247. {
  248. int ter = p->des01.etx.end_ring;
  249. memset(p, 0, offsetof(struct dma_desc, des2));
  250. if (mode == STMMAC_CHAIN_MODE)
  251. enh_desc_end_tx_desc_on_chain(p, ter);
  252. else
  253. enh_desc_end_tx_desc_on_ring(p, ter);
  254. }
  255. static void enh_desc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
  256. int csum_flag, int mode)
  257. {
  258. p->des01.etx.first_segment = is_fs;
  259. if (mode == STMMAC_CHAIN_MODE)
  260. enh_set_tx_desc_len_on_chain(p, len);
  261. else
  262. enh_set_tx_desc_len_on_ring(p, len);
  263. if (likely(csum_flag))
  264. p->des01.etx.checksum_insertion = cic_full;
  265. }
  266. static void enh_desc_clear_tx_ic(struct dma_desc *p)
  267. {
  268. p->des01.etx.interrupt = 0;
  269. }
  270. static void enh_desc_close_tx_desc(struct dma_desc *p)
  271. {
  272. p->des01.etx.last_segment = 1;
  273. p->des01.etx.interrupt = 1;
  274. }
  275. static int enh_desc_get_rx_frame_len(struct dma_desc *p, int rx_coe_type)
  276. {
  277. /* The type-1 checksum offload engines append the checksum at
  278. * the end of frame and the two bytes of checksum are added in
  279. * the length.
  280. * Adjust for that in the framelen for type-1 checksum offload
  281. * engines. */
  282. if (rx_coe_type == STMMAC_RX_COE_TYPE1)
  283. return p->des01.erx.frame_length - 2;
  284. else
  285. return p->des01.erx.frame_length;
  286. }
  287. static void enh_desc_enable_tx_timestamp(struct dma_desc *p)
  288. {
  289. p->des01.etx.time_stamp_enable = 1;
  290. }
  291. static int enh_desc_get_tx_timestamp_status(struct dma_desc *p)
  292. {
  293. return p->des01.etx.time_stamp_status;
  294. }
  295. static u64 enh_desc_get_timestamp(void *desc, u32 ats)
  296. {
  297. u64 ns;
  298. if (ats) {
  299. struct dma_extended_desc *p = (struct dma_extended_desc *)desc;
  300. ns = p->des6;
  301. /* convert high/sec time stamp value to nanosecond */
  302. ns += p->des7 * 1000000000ULL;
  303. } else {
  304. struct dma_desc *p = (struct dma_desc *)desc;
  305. ns = p->des2;
  306. ns += p->des3 * 1000000000ULL;
  307. }
  308. return ns;
  309. }
  310. static int enh_desc_get_rx_timestamp_status(void *desc, u32 ats)
  311. {
  312. if (ats) {
  313. struct dma_extended_desc *p = (struct dma_extended_desc *)desc;
  314. return p->basic.des01.erx.ipc_csum_error;
  315. } else {
  316. struct dma_desc *p = (struct dma_desc *)desc;
  317. if ((p->des2 == 0xffffffff) && (p->des3 == 0xffffffff))
  318. /* timestamp is corrupted, hence don't store it */
  319. return 0;
  320. else
  321. return 1;
  322. }
  323. }
  324. const struct stmmac_desc_ops enh_desc_ops = {
  325. .tx_status = enh_desc_get_tx_status,
  326. .rx_status = enh_desc_get_rx_status,
  327. .get_tx_len = enh_desc_get_tx_len,
  328. .init_rx_desc = enh_desc_init_rx_desc,
  329. .init_tx_desc = enh_desc_init_tx_desc,
  330. .get_tx_owner = enh_desc_get_tx_owner,
  331. .get_rx_owner = enh_desc_get_rx_owner,
  332. .release_tx_desc = enh_desc_release_tx_desc,
  333. .prepare_tx_desc = enh_desc_prepare_tx_desc,
  334. .clear_tx_ic = enh_desc_clear_tx_ic,
  335. .close_tx_desc = enh_desc_close_tx_desc,
  336. .get_tx_ls = enh_desc_get_tx_ls,
  337. .set_tx_owner = enh_desc_set_tx_owner,
  338. .set_rx_owner = enh_desc_set_rx_owner,
  339. .get_rx_frame_len = enh_desc_get_rx_frame_len,
  340. .rx_extended_status = enh_desc_get_ext_status,
  341. .enable_tx_timestamp = enh_desc_enable_tx_timestamp,
  342. .get_tx_timestamp_status = enh_desc_get_tx_timestamp_status,
  343. .get_timestamp = enh_desc_get_timestamp,
  344. .get_rx_timestamp_status = enh_desc_get_rx_timestamp_status,
  345. };