cpsw-phy-sel.c 5.0 KB

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  1. /* Texas Instruments Ethernet Switch Driver
  2. *
  3. * Copyright (C) 2013 Texas Instruments
  4. *
  5. * Module Author: Mugunthan V N <mugunthanvnm@ti.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * version 2 as published by the Free Software Foundation.
  10. *
  11. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12. * kind, whether express or implied; without even the implied warranty
  13. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <linux/platform_device.h>
  17. #include <linux/init.h>
  18. #include <linux/netdevice.h>
  19. #include <linux/phy.h>
  20. #include <linux/of.h>
  21. #include <linux/of_device.h>
  22. #include "cpsw.h"
  23. /* AM33xx SoC specific definitions for the CONTROL port */
  24. #define AM33XX_GMII_SEL_MODE_MII 0
  25. #define AM33XX_GMII_SEL_MODE_RMII 1
  26. #define AM33XX_GMII_SEL_MODE_RGMII 2
  27. #define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7)
  28. #define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6)
  29. #define GMII_SEL_MODE_MASK 0x3
  30. struct cpsw_phy_sel_priv {
  31. struct device *dev;
  32. u32 __iomem *gmii_sel;
  33. bool rmii_clock_external;
  34. void (*cpsw_phy_sel)(struct cpsw_phy_sel_priv *priv,
  35. phy_interface_t phy_mode, int slave);
  36. };
  37. static void cpsw_gmii_sel_am3352(struct cpsw_phy_sel_priv *priv,
  38. phy_interface_t phy_mode, int slave)
  39. {
  40. u32 reg;
  41. u32 mask;
  42. u32 mode = 0;
  43. reg = readl(priv->gmii_sel);
  44. switch (phy_mode) {
  45. case PHY_INTERFACE_MODE_RMII:
  46. mode = AM33XX_GMII_SEL_MODE_RMII;
  47. break;
  48. case PHY_INTERFACE_MODE_RGMII:
  49. case PHY_INTERFACE_MODE_RGMII_ID:
  50. case PHY_INTERFACE_MODE_RGMII_RXID:
  51. case PHY_INTERFACE_MODE_RGMII_TXID:
  52. mode = AM33XX_GMII_SEL_MODE_RGMII;
  53. break;
  54. case PHY_INTERFACE_MODE_MII:
  55. default:
  56. mode = AM33XX_GMII_SEL_MODE_MII;
  57. break;
  58. };
  59. mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6);
  60. mode <<= slave * 2;
  61. if (priv->rmii_clock_external) {
  62. if (slave == 0)
  63. mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN;
  64. else
  65. mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN;
  66. }
  67. reg &= ~mask;
  68. reg |= mode;
  69. writel(reg, priv->gmii_sel);
  70. }
  71. static void cpsw_gmii_sel_dra7xx(struct cpsw_phy_sel_priv *priv,
  72. phy_interface_t phy_mode, int slave)
  73. {
  74. u32 reg;
  75. u32 mask;
  76. u32 mode = 0;
  77. reg = readl(priv->gmii_sel);
  78. switch (phy_mode) {
  79. case PHY_INTERFACE_MODE_RMII:
  80. mode = AM33XX_GMII_SEL_MODE_RMII;
  81. break;
  82. case PHY_INTERFACE_MODE_RGMII:
  83. case PHY_INTERFACE_MODE_RGMII_ID:
  84. case PHY_INTERFACE_MODE_RGMII_RXID:
  85. case PHY_INTERFACE_MODE_RGMII_TXID:
  86. mode = AM33XX_GMII_SEL_MODE_RGMII;
  87. break;
  88. case PHY_INTERFACE_MODE_MII:
  89. default:
  90. mode = AM33XX_GMII_SEL_MODE_MII;
  91. break;
  92. };
  93. switch (slave) {
  94. case 0:
  95. mask = GMII_SEL_MODE_MASK;
  96. break;
  97. case 1:
  98. mask = GMII_SEL_MODE_MASK << 4;
  99. mode <<= 4;
  100. break;
  101. default:
  102. dev_err(priv->dev, "invalid slave number...\n");
  103. return;
  104. }
  105. if (priv->rmii_clock_external)
  106. dev_err(priv->dev, "RMII External clock is not supported\n");
  107. reg &= ~mask;
  108. reg |= mode;
  109. writel(reg, priv->gmii_sel);
  110. }
  111. static struct platform_driver cpsw_phy_sel_driver;
  112. static int match(struct device *dev, void *data)
  113. {
  114. struct device_node *node = (struct device_node *)data;
  115. return dev->of_node == node &&
  116. dev->driver == &cpsw_phy_sel_driver.driver;
  117. }
  118. void cpsw_phy_sel(struct device *dev, phy_interface_t phy_mode, int slave)
  119. {
  120. struct device_node *node;
  121. struct cpsw_phy_sel_priv *priv;
  122. node = of_get_child_by_name(dev->of_node, "cpsw-phy-sel");
  123. if (!node) {
  124. dev_err(dev, "Phy mode driver DT not found\n");
  125. return;
  126. }
  127. dev = bus_find_device(&platform_bus_type, NULL, node, match);
  128. priv = dev_get_drvdata(dev);
  129. priv->cpsw_phy_sel(priv, phy_mode, slave);
  130. }
  131. EXPORT_SYMBOL_GPL(cpsw_phy_sel);
  132. static const struct of_device_id cpsw_phy_sel_id_table[] = {
  133. {
  134. .compatible = "ti,am3352-cpsw-phy-sel",
  135. .data = &cpsw_gmii_sel_am3352,
  136. },
  137. {
  138. .compatible = "ti,dra7xx-cpsw-phy-sel",
  139. .data = &cpsw_gmii_sel_dra7xx,
  140. },
  141. {
  142. .compatible = "ti,am43xx-cpsw-phy-sel",
  143. .data = &cpsw_gmii_sel_am3352,
  144. },
  145. {}
  146. };
  147. static int cpsw_phy_sel_probe(struct platform_device *pdev)
  148. {
  149. struct resource *res;
  150. const struct of_device_id *of_id;
  151. struct cpsw_phy_sel_priv *priv;
  152. of_id = of_match_node(cpsw_phy_sel_id_table, pdev->dev.of_node);
  153. if (!of_id)
  154. return -EINVAL;
  155. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  156. if (!priv) {
  157. dev_err(&pdev->dev, "unable to alloc memory for cpsw phy sel\n");
  158. return -ENOMEM;
  159. }
  160. priv->dev = &pdev->dev;
  161. priv->cpsw_phy_sel = of_id->data;
  162. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gmii-sel");
  163. priv->gmii_sel = devm_ioremap_resource(&pdev->dev, res);
  164. if (IS_ERR(priv->gmii_sel))
  165. return PTR_ERR(priv->gmii_sel);
  166. if (of_find_property(pdev->dev.of_node, "rmii-clock-ext", NULL))
  167. priv->rmii_clock_external = true;
  168. dev_set_drvdata(&pdev->dev, priv);
  169. return 0;
  170. }
  171. static struct platform_driver cpsw_phy_sel_driver = {
  172. .probe = cpsw_phy_sel_probe,
  173. .driver = {
  174. .name = "cpsw-phy-sel",
  175. .of_match_table = cpsw_phy_sel_id_table,
  176. },
  177. };
  178. builtin_platform_driver(cpsw_phy_sel_driver);