w5300.c 18 KB

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  1. /*
  2. * Ethernet driver for the WIZnet W5300 chip.
  3. *
  4. * Copyright (C) 2008-2009 WIZnet Co.,Ltd.
  5. * Copyright (C) 2011 Taehun Kim <kth3321 <at> gmail.com>
  6. * Copyright (C) 2012 Mike Sinkovsky <msink@permonline.ru>
  7. *
  8. * Licensed under the GPL-2 or later.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/kconfig.h>
  13. #include <linux/netdevice.h>
  14. #include <linux/etherdevice.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/platform_data/wiznet.h>
  17. #include <linux/ethtool.h>
  18. #include <linux/skbuff.h>
  19. #include <linux/types.h>
  20. #include <linux/errno.h>
  21. #include <linux/delay.h>
  22. #include <linux/slab.h>
  23. #include <linux/spinlock.h>
  24. #include <linux/io.h>
  25. #include <linux/ioport.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/irq.h>
  28. #include <linux/gpio.h>
  29. #define DRV_NAME "w5300"
  30. #define DRV_VERSION "2012-04-04"
  31. MODULE_DESCRIPTION("WIZnet W5300 Ethernet driver v"DRV_VERSION);
  32. MODULE_AUTHOR("Mike Sinkovsky <msink@permonline.ru>");
  33. MODULE_ALIAS("platform:"DRV_NAME);
  34. MODULE_LICENSE("GPL");
  35. /*
  36. * Registers
  37. */
  38. #define W5300_MR 0x0000 /* Mode Register */
  39. #define MR_DBW (1 << 15) /* Data bus width */
  40. #define MR_MPF (1 << 14) /* Mac layer pause frame */
  41. #define MR_WDF(n) (((n)&7)<<11) /* Write data fetch time */
  42. #define MR_RDH (1 << 10) /* Read data hold time */
  43. #define MR_FS (1 << 8) /* FIFO swap */
  44. #define MR_RST (1 << 7) /* S/W reset */
  45. #define MR_PB (1 << 4) /* Ping block */
  46. #define MR_DBS (1 << 2) /* Data bus swap */
  47. #define MR_IND (1 << 0) /* Indirect mode */
  48. #define W5300_IR 0x0002 /* Interrupt Register */
  49. #define W5300_IMR 0x0004 /* Interrupt Mask Register */
  50. #define IR_S0 0x0001 /* S0 interrupt */
  51. #define W5300_SHARL 0x0008 /* Source MAC address (0123) */
  52. #define W5300_SHARH 0x000c /* Source MAC address (45) */
  53. #define W5300_TMSRL 0x0020 /* Transmit Memory Size (0123) */
  54. #define W5300_TMSRH 0x0024 /* Transmit Memory Size (4567) */
  55. #define W5300_RMSRL 0x0028 /* Receive Memory Size (0123) */
  56. #define W5300_RMSRH 0x002c /* Receive Memory Size (4567) */
  57. #define W5300_MTYPE 0x0030 /* Memory Type */
  58. #define W5300_IDR 0x00fe /* Chip ID register */
  59. #define IDR_W5300 0x5300 /* =0x5300 for WIZnet W5300 */
  60. #define W5300_S0_MR 0x0200 /* S0 Mode Register */
  61. #define S0_MR_CLOSED 0x0000 /* Close mode */
  62. #define S0_MR_MACRAW 0x0004 /* MAC RAW mode (promiscuous) */
  63. #define S0_MR_MACRAW_MF 0x0044 /* MAC RAW mode (filtered) */
  64. #define W5300_S0_CR 0x0202 /* S0 Command Register */
  65. #define S0_CR_OPEN 0x0001 /* OPEN command */
  66. #define S0_CR_CLOSE 0x0010 /* CLOSE command */
  67. #define S0_CR_SEND 0x0020 /* SEND command */
  68. #define S0_CR_RECV 0x0040 /* RECV command */
  69. #define W5300_S0_IMR 0x0204 /* S0 Interrupt Mask Register */
  70. #define W5300_S0_IR 0x0206 /* S0 Interrupt Register */
  71. #define S0_IR_RECV 0x0004 /* Receive interrupt */
  72. #define S0_IR_SENDOK 0x0010 /* Send OK interrupt */
  73. #define W5300_S0_SSR 0x0208 /* S0 Socket Status Register */
  74. #define W5300_S0_TX_WRSR 0x0220 /* S0 TX Write Size Register */
  75. #define W5300_S0_TX_FSR 0x0224 /* S0 TX Free Size Register */
  76. #define W5300_S0_RX_RSR 0x0228 /* S0 Received data Size */
  77. #define W5300_S0_TX_FIFO 0x022e /* S0 Transmit FIFO */
  78. #define W5300_S0_RX_FIFO 0x0230 /* S0 Receive FIFO */
  79. #define W5300_REGS_LEN 0x0400
  80. /*
  81. * Device driver private data structure
  82. */
  83. struct w5300_priv {
  84. void __iomem *base;
  85. spinlock_t reg_lock;
  86. bool indirect;
  87. u16 (*read) (struct w5300_priv *priv, u16 addr);
  88. void (*write)(struct w5300_priv *priv, u16 addr, u16 data);
  89. int irq;
  90. int link_irq;
  91. int link_gpio;
  92. struct napi_struct napi;
  93. struct net_device *ndev;
  94. bool promisc;
  95. u32 msg_enable;
  96. };
  97. /************************************************************************
  98. *
  99. * Lowlevel I/O functions
  100. *
  101. ***********************************************************************/
  102. /*
  103. * In direct address mode host system can directly access W5300 registers
  104. * after mapping to Memory-Mapped I/O space.
  105. *
  106. * 0x400 bytes are required for memory space.
  107. */
  108. static inline u16 w5300_read_direct(struct w5300_priv *priv, u16 addr)
  109. {
  110. return ioread16(priv->base + (addr << CONFIG_WIZNET_BUS_SHIFT));
  111. }
  112. static inline void w5300_write_direct(struct w5300_priv *priv,
  113. u16 addr, u16 data)
  114. {
  115. iowrite16(data, priv->base + (addr << CONFIG_WIZNET_BUS_SHIFT));
  116. }
  117. /*
  118. * In indirect address mode host system indirectly accesses registers by
  119. * using Indirect Mode Address Register (IDM_AR) and Indirect Mode Data
  120. * Register (IDM_DR), which are directly mapped to Memory-Mapped I/O space.
  121. * Mode Register (MR) is directly accessible.
  122. *
  123. * Only 0x06 bytes are required for memory space.
  124. */
  125. #define W5300_IDM_AR 0x0002 /* Indirect Mode Address */
  126. #define W5300_IDM_DR 0x0004 /* Indirect Mode Data */
  127. static u16 w5300_read_indirect(struct w5300_priv *priv, u16 addr)
  128. {
  129. unsigned long flags;
  130. u16 data;
  131. spin_lock_irqsave(&priv->reg_lock, flags);
  132. w5300_write_direct(priv, W5300_IDM_AR, addr);
  133. mmiowb();
  134. data = w5300_read_direct(priv, W5300_IDM_DR);
  135. spin_unlock_irqrestore(&priv->reg_lock, flags);
  136. return data;
  137. }
  138. static void w5300_write_indirect(struct w5300_priv *priv, u16 addr, u16 data)
  139. {
  140. unsigned long flags;
  141. spin_lock_irqsave(&priv->reg_lock, flags);
  142. w5300_write_direct(priv, W5300_IDM_AR, addr);
  143. mmiowb();
  144. w5300_write_direct(priv, W5300_IDM_DR, data);
  145. mmiowb();
  146. spin_unlock_irqrestore(&priv->reg_lock, flags);
  147. }
  148. #if defined(CONFIG_WIZNET_BUS_DIRECT)
  149. #define w5300_read w5300_read_direct
  150. #define w5300_write w5300_write_direct
  151. #elif defined(CONFIG_WIZNET_BUS_INDIRECT)
  152. #define w5300_read w5300_read_indirect
  153. #define w5300_write w5300_write_indirect
  154. #else /* CONFIG_WIZNET_BUS_ANY */
  155. #define w5300_read priv->read
  156. #define w5300_write priv->write
  157. #endif
  158. static u32 w5300_read32(struct w5300_priv *priv, u16 addr)
  159. {
  160. u32 data;
  161. data = w5300_read(priv, addr) << 16;
  162. data |= w5300_read(priv, addr + 2);
  163. return data;
  164. }
  165. static void w5300_write32(struct w5300_priv *priv, u16 addr, u32 data)
  166. {
  167. w5300_write(priv, addr, data >> 16);
  168. w5300_write(priv, addr + 2, data);
  169. }
  170. static int w5300_command(struct w5300_priv *priv, u16 cmd)
  171. {
  172. unsigned long timeout = jiffies + msecs_to_jiffies(100);
  173. w5300_write(priv, W5300_S0_CR, cmd);
  174. mmiowb();
  175. while (w5300_read(priv, W5300_S0_CR) != 0) {
  176. if (time_after(jiffies, timeout))
  177. return -EIO;
  178. cpu_relax();
  179. }
  180. return 0;
  181. }
  182. static void w5300_read_frame(struct w5300_priv *priv, u8 *buf, int len)
  183. {
  184. u16 fifo;
  185. int i;
  186. for (i = 0; i < len; i += 2) {
  187. fifo = w5300_read(priv, W5300_S0_RX_FIFO);
  188. *buf++ = fifo >> 8;
  189. *buf++ = fifo;
  190. }
  191. fifo = w5300_read(priv, W5300_S0_RX_FIFO);
  192. fifo = w5300_read(priv, W5300_S0_RX_FIFO);
  193. }
  194. static void w5300_write_frame(struct w5300_priv *priv, u8 *buf, int len)
  195. {
  196. u16 fifo;
  197. int i;
  198. for (i = 0; i < len; i += 2) {
  199. fifo = *buf++ << 8;
  200. fifo |= *buf++;
  201. w5300_write(priv, W5300_S0_TX_FIFO, fifo);
  202. }
  203. w5300_write32(priv, W5300_S0_TX_WRSR, len);
  204. }
  205. static void w5300_write_macaddr(struct w5300_priv *priv)
  206. {
  207. struct net_device *ndev = priv->ndev;
  208. w5300_write32(priv, W5300_SHARL,
  209. ndev->dev_addr[0] << 24 |
  210. ndev->dev_addr[1] << 16 |
  211. ndev->dev_addr[2] << 8 |
  212. ndev->dev_addr[3]);
  213. w5300_write(priv, W5300_SHARH,
  214. ndev->dev_addr[4] << 8 |
  215. ndev->dev_addr[5]);
  216. mmiowb();
  217. }
  218. static void w5300_hw_reset(struct w5300_priv *priv)
  219. {
  220. w5300_write_direct(priv, W5300_MR, MR_RST);
  221. mmiowb();
  222. mdelay(5);
  223. w5300_write_direct(priv, W5300_MR, priv->indirect ?
  224. MR_WDF(7) | MR_PB | MR_IND :
  225. MR_WDF(7) | MR_PB);
  226. mmiowb();
  227. w5300_write(priv, W5300_IMR, 0);
  228. w5300_write_macaddr(priv);
  229. /* Configure 128K of internal memory
  230. * as 64K RX fifo and 64K TX fifo
  231. */
  232. w5300_write32(priv, W5300_RMSRL, 64 << 24);
  233. w5300_write32(priv, W5300_RMSRH, 0);
  234. w5300_write32(priv, W5300_TMSRL, 64 << 24);
  235. w5300_write32(priv, W5300_TMSRH, 0);
  236. w5300_write(priv, W5300_MTYPE, 0x00ff);
  237. mmiowb();
  238. }
  239. static void w5300_hw_start(struct w5300_priv *priv)
  240. {
  241. w5300_write(priv, W5300_S0_MR, priv->promisc ?
  242. S0_MR_MACRAW : S0_MR_MACRAW_MF);
  243. mmiowb();
  244. w5300_command(priv, S0_CR_OPEN);
  245. w5300_write(priv, W5300_S0_IMR, S0_IR_RECV | S0_IR_SENDOK);
  246. w5300_write(priv, W5300_IMR, IR_S0);
  247. mmiowb();
  248. }
  249. static void w5300_hw_close(struct w5300_priv *priv)
  250. {
  251. w5300_write(priv, W5300_IMR, 0);
  252. mmiowb();
  253. w5300_command(priv, S0_CR_CLOSE);
  254. }
  255. /***********************************************************************
  256. *
  257. * Device driver functions / callbacks
  258. *
  259. ***********************************************************************/
  260. static void w5300_get_drvinfo(struct net_device *ndev,
  261. struct ethtool_drvinfo *info)
  262. {
  263. strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
  264. strlcpy(info->version, DRV_VERSION, sizeof(info->version));
  265. strlcpy(info->bus_info, dev_name(ndev->dev.parent),
  266. sizeof(info->bus_info));
  267. }
  268. static u32 w5300_get_link(struct net_device *ndev)
  269. {
  270. struct w5300_priv *priv = netdev_priv(ndev);
  271. if (gpio_is_valid(priv->link_gpio))
  272. return !!gpio_get_value(priv->link_gpio);
  273. return 1;
  274. }
  275. static u32 w5300_get_msglevel(struct net_device *ndev)
  276. {
  277. struct w5300_priv *priv = netdev_priv(ndev);
  278. return priv->msg_enable;
  279. }
  280. static void w5300_set_msglevel(struct net_device *ndev, u32 value)
  281. {
  282. struct w5300_priv *priv = netdev_priv(ndev);
  283. priv->msg_enable = value;
  284. }
  285. static int w5300_get_regs_len(struct net_device *ndev)
  286. {
  287. return W5300_REGS_LEN;
  288. }
  289. static void w5300_get_regs(struct net_device *ndev,
  290. struct ethtool_regs *regs, void *_buf)
  291. {
  292. struct w5300_priv *priv = netdev_priv(ndev);
  293. u8 *buf = _buf;
  294. u16 addr;
  295. u16 data;
  296. regs->version = 1;
  297. for (addr = 0; addr < W5300_REGS_LEN; addr += 2) {
  298. switch (addr & 0x23f) {
  299. case W5300_S0_TX_FIFO: /* cannot read TX_FIFO */
  300. case W5300_S0_RX_FIFO: /* cannot read RX_FIFO */
  301. data = 0xffff;
  302. break;
  303. default:
  304. data = w5300_read(priv, addr);
  305. break;
  306. }
  307. *buf++ = data >> 8;
  308. *buf++ = data;
  309. }
  310. }
  311. static void w5300_tx_timeout(struct net_device *ndev)
  312. {
  313. struct w5300_priv *priv = netdev_priv(ndev);
  314. netif_stop_queue(ndev);
  315. w5300_hw_reset(priv);
  316. w5300_hw_start(priv);
  317. ndev->stats.tx_errors++;
  318. ndev->trans_start = jiffies;
  319. netif_wake_queue(ndev);
  320. }
  321. static int w5300_start_tx(struct sk_buff *skb, struct net_device *ndev)
  322. {
  323. struct w5300_priv *priv = netdev_priv(ndev);
  324. netif_stop_queue(ndev);
  325. w5300_write_frame(priv, skb->data, skb->len);
  326. mmiowb();
  327. ndev->stats.tx_packets++;
  328. ndev->stats.tx_bytes += skb->len;
  329. dev_kfree_skb(skb);
  330. netif_dbg(priv, tx_queued, ndev, "tx queued\n");
  331. w5300_command(priv, S0_CR_SEND);
  332. return NETDEV_TX_OK;
  333. }
  334. static int w5300_napi_poll(struct napi_struct *napi, int budget)
  335. {
  336. struct w5300_priv *priv = container_of(napi, struct w5300_priv, napi);
  337. struct net_device *ndev = priv->ndev;
  338. struct sk_buff *skb;
  339. int rx_count;
  340. u16 rx_len;
  341. for (rx_count = 0; rx_count < budget; rx_count++) {
  342. u32 rx_fifo_len = w5300_read32(priv, W5300_S0_RX_RSR);
  343. if (rx_fifo_len == 0)
  344. break;
  345. rx_len = w5300_read(priv, W5300_S0_RX_FIFO);
  346. skb = netdev_alloc_skb_ip_align(ndev, roundup(rx_len, 2));
  347. if (unlikely(!skb)) {
  348. u32 i;
  349. for (i = 0; i < rx_fifo_len; i += 2)
  350. w5300_read(priv, W5300_S0_RX_FIFO);
  351. ndev->stats.rx_dropped++;
  352. return -ENOMEM;
  353. }
  354. skb_put(skb, rx_len);
  355. w5300_read_frame(priv, skb->data, rx_len);
  356. skb->protocol = eth_type_trans(skb, ndev);
  357. netif_receive_skb(skb);
  358. ndev->stats.rx_packets++;
  359. ndev->stats.rx_bytes += rx_len;
  360. }
  361. if (rx_count < budget) {
  362. napi_complete(napi);
  363. w5300_write(priv, W5300_IMR, IR_S0);
  364. mmiowb();
  365. }
  366. return rx_count;
  367. }
  368. static irqreturn_t w5300_interrupt(int irq, void *ndev_instance)
  369. {
  370. struct net_device *ndev = ndev_instance;
  371. struct w5300_priv *priv = netdev_priv(ndev);
  372. int ir = w5300_read(priv, W5300_S0_IR);
  373. if (!ir)
  374. return IRQ_NONE;
  375. w5300_write(priv, W5300_S0_IR, ir);
  376. mmiowb();
  377. if (ir & S0_IR_SENDOK) {
  378. netif_dbg(priv, tx_done, ndev, "tx done\n");
  379. netif_wake_queue(ndev);
  380. }
  381. if (ir & S0_IR_RECV) {
  382. if (napi_schedule_prep(&priv->napi)) {
  383. w5300_write(priv, W5300_IMR, 0);
  384. mmiowb();
  385. __napi_schedule(&priv->napi);
  386. }
  387. }
  388. return IRQ_HANDLED;
  389. }
  390. static irqreturn_t w5300_detect_link(int irq, void *ndev_instance)
  391. {
  392. struct net_device *ndev = ndev_instance;
  393. struct w5300_priv *priv = netdev_priv(ndev);
  394. if (netif_running(ndev)) {
  395. if (gpio_get_value(priv->link_gpio) != 0) {
  396. netif_info(priv, link, ndev, "link is up\n");
  397. netif_carrier_on(ndev);
  398. } else {
  399. netif_info(priv, link, ndev, "link is down\n");
  400. netif_carrier_off(ndev);
  401. }
  402. }
  403. return IRQ_HANDLED;
  404. }
  405. static void w5300_set_rx_mode(struct net_device *ndev)
  406. {
  407. struct w5300_priv *priv = netdev_priv(ndev);
  408. bool set_promisc = (ndev->flags & IFF_PROMISC) != 0;
  409. if (priv->promisc != set_promisc) {
  410. priv->promisc = set_promisc;
  411. w5300_hw_start(priv);
  412. }
  413. }
  414. static int w5300_set_macaddr(struct net_device *ndev, void *addr)
  415. {
  416. struct w5300_priv *priv = netdev_priv(ndev);
  417. struct sockaddr *sock_addr = addr;
  418. if (!is_valid_ether_addr(sock_addr->sa_data))
  419. return -EADDRNOTAVAIL;
  420. memcpy(ndev->dev_addr, sock_addr->sa_data, ETH_ALEN);
  421. w5300_write_macaddr(priv);
  422. return 0;
  423. }
  424. static int w5300_open(struct net_device *ndev)
  425. {
  426. struct w5300_priv *priv = netdev_priv(ndev);
  427. netif_info(priv, ifup, ndev, "enabling\n");
  428. w5300_hw_start(priv);
  429. napi_enable(&priv->napi);
  430. netif_start_queue(ndev);
  431. if (!gpio_is_valid(priv->link_gpio) ||
  432. gpio_get_value(priv->link_gpio) != 0)
  433. netif_carrier_on(ndev);
  434. return 0;
  435. }
  436. static int w5300_stop(struct net_device *ndev)
  437. {
  438. struct w5300_priv *priv = netdev_priv(ndev);
  439. netif_info(priv, ifdown, ndev, "shutting down\n");
  440. w5300_hw_close(priv);
  441. netif_carrier_off(ndev);
  442. netif_stop_queue(ndev);
  443. napi_disable(&priv->napi);
  444. return 0;
  445. }
  446. static const struct ethtool_ops w5300_ethtool_ops = {
  447. .get_drvinfo = w5300_get_drvinfo,
  448. .get_msglevel = w5300_get_msglevel,
  449. .set_msglevel = w5300_set_msglevel,
  450. .get_link = w5300_get_link,
  451. .get_regs_len = w5300_get_regs_len,
  452. .get_regs = w5300_get_regs,
  453. };
  454. static const struct net_device_ops w5300_netdev_ops = {
  455. .ndo_open = w5300_open,
  456. .ndo_stop = w5300_stop,
  457. .ndo_start_xmit = w5300_start_tx,
  458. .ndo_tx_timeout = w5300_tx_timeout,
  459. .ndo_set_rx_mode = w5300_set_rx_mode,
  460. .ndo_set_mac_address = w5300_set_macaddr,
  461. .ndo_validate_addr = eth_validate_addr,
  462. .ndo_change_mtu = eth_change_mtu,
  463. };
  464. static int w5300_hw_probe(struct platform_device *pdev)
  465. {
  466. struct wiznet_platform_data *data = dev_get_platdata(&pdev->dev);
  467. struct net_device *ndev = platform_get_drvdata(pdev);
  468. struct w5300_priv *priv = netdev_priv(ndev);
  469. const char *name = netdev_name(ndev);
  470. struct resource *mem;
  471. int mem_size;
  472. int irq;
  473. int ret;
  474. if (data && is_valid_ether_addr(data->mac_addr)) {
  475. memcpy(ndev->dev_addr, data->mac_addr, ETH_ALEN);
  476. } else {
  477. eth_hw_addr_random(ndev);
  478. }
  479. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  480. priv->base = devm_ioremap_resource(&pdev->dev, mem);
  481. if (IS_ERR(priv->base))
  482. return PTR_ERR(priv->base);
  483. mem_size = resource_size(mem);
  484. spin_lock_init(&priv->reg_lock);
  485. priv->indirect = mem_size < W5300_BUS_DIRECT_SIZE;
  486. if (priv->indirect) {
  487. priv->read = w5300_read_indirect;
  488. priv->write = w5300_write_indirect;
  489. } else {
  490. priv->read = w5300_read_direct;
  491. priv->write = w5300_write_direct;
  492. }
  493. w5300_hw_reset(priv);
  494. if (w5300_read(priv, W5300_IDR) != IDR_W5300)
  495. return -ENODEV;
  496. irq = platform_get_irq(pdev, 0);
  497. if (irq < 0)
  498. return irq;
  499. ret = request_irq(irq, w5300_interrupt,
  500. IRQ_TYPE_LEVEL_LOW, name, ndev);
  501. if (ret < 0)
  502. return ret;
  503. priv->irq = irq;
  504. priv->link_gpio = data ? data->link_gpio : -EINVAL;
  505. if (gpio_is_valid(priv->link_gpio)) {
  506. char *link_name = devm_kzalloc(&pdev->dev, 16, GFP_KERNEL);
  507. if (!link_name)
  508. return -ENOMEM;
  509. snprintf(link_name, 16, "%s-link", name);
  510. priv->link_irq = gpio_to_irq(priv->link_gpio);
  511. if (request_any_context_irq(priv->link_irq, w5300_detect_link,
  512. IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
  513. link_name, priv->ndev) < 0)
  514. priv->link_gpio = -EINVAL;
  515. }
  516. netdev_info(ndev, "at 0x%llx irq %d\n", (u64)mem->start, irq);
  517. return 0;
  518. }
  519. static int w5300_probe(struct platform_device *pdev)
  520. {
  521. struct w5300_priv *priv;
  522. struct net_device *ndev;
  523. int err;
  524. ndev = alloc_etherdev(sizeof(*priv));
  525. if (!ndev)
  526. return -ENOMEM;
  527. SET_NETDEV_DEV(ndev, &pdev->dev);
  528. platform_set_drvdata(pdev, ndev);
  529. priv = netdev_priv(ndev);
  530. priv->ndev = ndev;
  531. ndev->netdev_ops = &w5300_netdev_ops;
  532. ndev->ethtool_ops = &w5300_ethtool_ops;
  533. ndev->watchdog_timeo = HZ;
  534. netif_napi_add(ndev, &priv->napi, w5300_napi_poll, 16);
  535. /* This chip doesn't support VLAN packets with normal MTU,
  536. * so disable VLAN for this device.
  537. */
  538. ndev->features |= NETIF_F_VLAN_CHALLENGED;
  539. err = register_netdev(ndev);
  540. if (err < 0)
  541. goto err_register;
  542. err = w5300_hw_probe(pdev);
  543. if (err < 0)
  544. goto err_hw_probe;
  545. return 0;
  546. err_hw_probe:
  547. unregister_netdev(ndev);
  548. err_register:
  549. free_netdev(ndev);
  550. return err;
  551. }
  552. static int w5300_remove(struct platform_device *pdev)
  553. {
  554. struct net_device *ndev = platform_get_drvdata(pdev);
  555. struct w5300_priv *priv = netdev_priv(ndev);
  556. w5300_hw_reset(priv);
  557. free_irq(priv->irq, ndev);
  558. if (gpio_is_valid(priv->link_gpio))
  559. free_irq(priv->link_irq, ndev);
  560. unregister_netdev(ndev);
  561. free_netdev(ndev);
  562. return 0;
  563. }
  564. #ifdef CONFIG_PM_SLEEP
  565. static int w5300_suspend(struct device *dev)
  566. {
  567. struct platform_device *pdev = to_platform_device(dev);
  568. struct net_device *ndev = platform_get_drvdata(pdev);
  569. struct w5300_priv *priv = netdev_priv(ndev);
  570. if (netif_running(ndev)) {
  571. netif_carrier_off(ndev);
  572. netif_device_detach(ndev);
  573. w5300_hw_close(priv);
  574. }
  575. return 0;
  576. }
  577. static int w5300_resume(struct device *dev)
  578. {
  579. struct platform_device *pdev = to_platform_device(dev);
  580. struct net_device *ndev = platform_get_drvdata(pdev);
  581. struct w5300_priv *priv = netdev_priv(ndev);
  582. if (!netif_running(ndev)) {
  583. w5300_hw_reset(priv);
  584. w5300_hw_start(priv);
  585. netif_device_attach(ndev);
  586. if (!gpio_is_valid(priv->link_gpio) ||
  587. gpio_get_value(priv->link_gpio) != 0)
  588. netif_carrier_on(ndev);
  589. }
  590. return 0;
  591. }
  592. #endif /* CONFIG_PM_SLEEP */
  593. static SIMPLE_DEV_PM_OPS(w5300_pm_ops, w5300_suspend, w5300_resume);
  594. static struct platform_driver w5300_driver = {
  595. .driver = {
  596. .name = DRV_NAME,
  597. .pm = &w5300_pm_ops,
  598. },
  599. .probe = w5300_probe,
  600. .remove = w5300_remove,
  601. };
  602. module_platform_driver(w5300_driver);