xilinx_axienet.h 21 KB

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  1. /*
  2. * Definitions for Xilinx Axi Ethernet device driver.
  3. *
  4. * Copyright (c) 2009 Secret Lab Technologies, Ltd.
  5. * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
  6. */
  7. #ifndef XILINX_AXIENET_H
  8. #define XILINX_AXIENET_H
  9. #include <linux/netdevice.h>
  10. #include <linux/spinlock.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/if_vlan.h>
  13. /* Packet size info */
  14. #define XAE_HDR_SIZE 14 /* Size of Ethernet header */
  15. #define XAE_TRL_SIZE 4 /* Size of Ethernet trailer (FCS) */
  16. #define XAE_MTU 1500 /* Max MTU of an Ethernet frame */
  17. #define XAE_JUMBO_MTU 9000 /* Max MTU of a jumbo Eth. frame */
  18. #define XAE_MAX_FRAME_SIZE (XAE_MTU + XAE_HDR_SIZE + XAE_TRL_SIZE)
  19. #define XAE_MAX_VLAN_FRAME_SIZE (XAE_MTU + VLAN_ETH_HLEN + XAE_TRL_SIZE)
  20. #define XAE_MAX_JUMBO_FRAME_SIZE (XAE_JUMBO_MTU + XAE_HDR_SIZE + XAE_TRL_SIZE)
  21. /* Configuration options */
  22. /* Accept all incoming packets. Default: disabled (cleared) */
  23. #define XAE_OPTION_PROMISC (1 << 0)
  24. /* Jumbo frame support for Tx & Rx. Default: disabled (cleared) */
  25. #define XAE_OPTION_JUMBO (1 << 1)
  26. /* VLAN Rx & Tx frame support. Default: disabled (cleared) */
  27. #define XAE_OPTION_VLAN (1 << 2)
  28. /* Enable recognition of flow control frames on Rx. Default: enabled (set) */
  29. #define XAE_OPTION_FLOW_CONTROL (1 << 4)
  30. /* Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
  31. * stripped. Default: disabled (set)
  32. */
  33. #define XAE_OPTION_FCS_STRIP (1 << 5)
  34. /* Generate FCS field and add PAD automatically for outgoing frames.
  35. * Default: enabled (set)
  36. */
  37. #define XAE_OPTION_FCS_INSERT (1 << 6)
  38. /* Enable Length/Type error checking for incoming frames. When this option is
  39. * set, the MAC will filter frames that have a mismatched type/length field
  40. * and if XAE_OPTION_REPORT_RXERR is set, the user is notified when these
  41. * types of frames are encountered. When this option is cleared, the MAC will
  42. * allow these types of frames to be received. Default: enabled (set)
  43. */
  44. #define XAE_OPTION_LENTYPE_ERR (1 << 7)
  45. /* Enable the transmitter. Default: enabled (set) */
  46. #define XAE_OPTION_TXEN (1 << 11)
  47. /* Enable the receiver. Default: enabled (set) */
  48. #define XAE_OPTION_RXEN (1 << 12)
  49. /* Default options set when device is initialized or reset */
  50. #define XAE_OPTION_DEFAULTS \
  51. (XAE_OPTION_TXEN | \
  52. XAE_OPTION_FLOW_CONTROL | \
  53. XAE_OPTION_RXEN)
  54. /* Axi DMA Register definitions */
  55. #define XAXIDMA_TX_CR_OFFSET 0x00000000 /* Channel control */
  56. #define XAXIDMA_TX_SR_OFFSET 0x00000004 /* Status */
  57. #define XAXIDMA_TX_CDESC_OFFSET 0x00000008 /* Current descriptor pointer */
  58. #define XAXIDMA_TX_TDESC_OFFSET 0x00000010 /* Tail descriptor pointer */
  59. #define XAXIDMA_RX_CR_OFFSET 0x00000030 /* Channel control */
  60. #define XAXIDMA_RX_SR_OFFSET 0x00000034 /* Status */
  61. #define XAXIDMA_RX_CDESC_OFFSET 0x00000038 /* Current descriptor pointer */
  62. #define XAXIDMA_RX_TDESC_OFFSET 0x00000040 /* Tail descriptor pointer */
  63. #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
  64. #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
  65. #define XAXIDMA_BD_NDESC_OFFSET 0x00 /* Next descriptor pointer */
  66. #define XAXIDMA_BD_BUFA_OFFSET 0x08 /* Buffer address */
  67. #define XAXIDMA_BD_CTRL_LEN_OFFSET 0x18 /* Control/buffer length */
  68. #define XAXIDMA_BD_STS_OFFSET 0x1C /* Status */
  69. #define XAXIDMA_BD_USR0_OFFSET 0x20 /* User IP specific word0 */
  70. #define XAXIDMA_BD_USR1_OFFSET 0x24 /* User IP specific word1 */
  71. #define XAXIDMA_BD_USR2_OFFSET 0x28 /* User IP specific word2 */
  72. #define XAXIDMA_BD_USR3_OFFSET 0x2C /* User IP specific word3 */
  73. #define XAXIDMA_BD_USR4_OFFSET 0x30 /* User IP specific word4 */
  74. #define XAXIDMA_BD_ID_OFFSET 0x34 /* Sw ID */
  75. #define XAXIDMA_BD_HAS_STSCNTRL_OFFSET 0x38 /* Whether has stscntrl strm */
  76. #define XAXIDMA_BD_HAS_DRE_OFFSET 0x3C /* Whether has DRE */
  77. #define XAXIDMA_BD_HAS_DRE_SHIFT 8 /* Whether has DRE shift */
  78. #define XAXIDMA_BD_HAS_DRE_MASK 0xF00 /* Whether has DRE mask */
  79. #define XAXIDMA_BD_WORDLEN_MASK 0xFF /* Whether has DRE mask */
  80. #define XAXIDMA_BD_CTRL_LENGTH_MASK 0x007FFFFF /* Requested len */
  81. #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
  82. #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
  83. #define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */
  84. #define XAXIDMA_DELAY_MASK 0xFF000000 /* Delay timeout counter */
  85. #define XAXIDMA_COALESCE_MASK 0x00FF0000 /* Coalesce counter */
  86. #define XAXIDMA_DELAY_SHIFT 24
  87. #define XAXIDMA_COALESCE_SHIFT 16
  88. #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
  89. #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
  90. #define XAXIDMA_IRQ_ERROR_MASK 0x00004000 /* Error interrupt */
  91. #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
  92. /* Default TX/RX Threshold and waitbound values for SGDMA mode */
  93. #define XAXIDMA_DFT_TX_THRESHOLD 24
  94. #define XAXIDMA_DFT_TX_WAITBOUND 254
  95. #define XAXIDMA_DFT_RX_THRESHOLD 24
  96. #define XAXIDMA_DFT_RX_WAITBOUND 254
  97. #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
  98. #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
  99. #define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */
  100. #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */
  101. #define XAXIDMA_BD_STS_COMPLETE_MASK 0x80000000 /* Completed */
  102. #define XAXIDMA_BD_STS_DEC_ERR_MASK 0x40000000 /* Decode error */
  103. #define XAXIDMA_BD_STS_SLV_ERR_MASK 0x20000000 /* Slave error */
  104. #define XAXIDMA_BD_STS_INT_ERR_MASK 0x10000000 /* Internal err */
  105. #define XAXIDMA_BD_STS_ALL_ERR_MASK 0x70000000 /* All errors */
  106. #define XAXIDMA_BD_STS_RXSOF_MASK 0x08000000 /* First rx pkt */
  107. #define XAXIDMA_BD_STS_RXEOF_MASK 0x04000000 /* Last rx pkt */
  108. #define XAXIDMA_BD_STS_ALL_MASK 0xFC000000 /* All status bits */
  109. #define XAXIDMA_BD_MINIMUM_ALIGNMENT 0x40
  110. /* Axi Ethernet registers definition */
  111. #define XAE_RAF_OFFSET 0x00000000 /* Reset and Address filter */
  112. #define XAE_TPF_OFFSET 0x00000004 /* Tx Pause Frame */
  113. #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
  114. #define XAE_IS_OFFSET 0x0000000C /* Interrupt status */
  115. #define XAE_IP_OFFSET 0x00000010 /* Interrupt pending */
  116. #define XAE_IE_OFFSET 0x00000014 /* Interrupt enable */
  117. #define XAE_TTAG_OFFSET 0x00000018 /* Tx VLAN TAG */
  118. #define XAE_RTAG_OFFSET 0x0000001C /* Rx VLAN TAG */
  119. #define XAE_UAWL_OFFSET 0x00000020 /* Unicast address word lower */
  120. #define XAE_UAWU_OFFSET 0x00000024 /* Unicast address word upper */
  121. #define XAE_TPID0_OFFSET 0x00000028 /* VLAN TPID0 register */
  122. #define XAE_TPID1_OFFSET 0x0000002C /* VLAN TPID1 register */
  123. #define XAE_PPST_OFFSET 0x00000030 /* PCS PMA Soft Temac Status Reg */
  124. #define XAE_RCW0_OFFSET 0x00000400 /* Rx Configuration Word 0 */
  125. #define XAE_RCW1_OFFSET 0x00000404 /* Rx Configuration Word 1 */
  126. #define XAE_TC_OFFSET 0x00000408 /* Tx Configuration */
  127. #define XAE_FCC_OFFSET 0x0000040C /* Flow Control Configuration */
  128. #define XAE_EMMC_OFFSET 0x00000410 /* EMAC mode configuration */
  129. #define XAE_PHYC_OFFSET 0x00000414 /* RGMII/SGMII configuration */
  130. #define XAE_MDIO_MC_OFFSET 0x00000500 /* MII Management Config */
  131. #define XAE_MDIO_MCR_OFFSET 0x00000504 /* MII Management Control */
  132. #define XAE_MDIO_MWD_OFFSET 0x00000508 /* MII Management Write Data */
  133. #define XAE_MDIO_MRD_OFFSET 0x0000050C /* MII Management Read Data */
  134. #define XAE_MDIO_MIS_OFFSET 0x00000600 /* MII Management Interrupt Status */
  135. /* MII Mgmt Interrupt Pending register offset */
  136. #define XAE_MDIO_MIP_OFFSET 0x00000620
  137. /* MII Management Interrupt Enable register offset */
  138. #define XAE_MDIO_MIE_OFFSET 0x00000640
  139. /* MII Management Interrupt Clear register offset. */
  140. #define XAE_MDIO_MIC_OFFSET 0x00000660
  141. #define XAE_UAW0_OFFSET 0x00000700 /* Unicast address word 0 */
  142. #define XAE_UAW1_OFFSET 0x00000704 /* Unicast address word 1 */
  143. #define XAE_FMI_OFFSET 0x00000708 /* Filter Mask Index */
  144. #define XAE_AF0_OFFSET 0x00000710 /* Address Filter 0 */
  145. #define XAE_AF1_OFFSET 0x00000714 /* Address Filter 1 */
  146. #define XAE_TX_VLAN_DATA_OFFSET 0x00004000 /* TX VLAN data table address */
  147. #define XAE_RX_VLAN_DATA_OFFSET 0x00008000 /* RX VLAN data table address */
  148. #define XAE_MCAST_TABLE_OFFSET 0x00020000 /* Multicast table address */
  149. /* Bit Masks for Axi Ethernet RAF register */
  150. /* Reject receive multicast destination address */
  151. #define XAE_RAF_MCSTREJ_MASK 0x00000002
  152. /* Reject receive broadcast destination address */
  153. #define XAE_RAF_BCSTREJ_MASK 0x00000004
  154. #define XAE_RAF_TXVTAGMODE_MASK 0x00000018 /* Tx VLAN TAG mode */
  155. #define XAE_RAF_RXVTAGMODE_MASK 0x00000060 /* Rx VLAN TAG mode */
  156. #define XAE_RAF_TXVSTRPMODE_MASK 0x00000180 /* Tx VLAN STRIP mode */
  157. #define XAE_RAF_RXVSTRPMODE_MASK 0x00000600 /* Rx VLAN STRIP mode */
  158. #define XAE_RAF_NEWFNCENBL_MASK 0x00000800 /* New function mode */
  159. /* Exteneded Multicast Filtering mode */
  160. #define XAE_RAF_EMULTIFLTRENBL_MASK 0x00001000
  161. #define XAE_RAF_STATSRST_MASK 0x00002000 /* Stats. Counter Reset */
  162. #define XAE_RAF_RXBADFRMEN_MASK 0x00004000 /* Recv Bad Frame Enable */
  163. #define XAE_RAF_TXVTAGMODE_SHIFT 3 /* Tx Tag mode shift bits */
  164. #define XAE_RAF_RXVTAGMODE_SHIFT 5 /* Rx Tag mode shift bits */
  165. #define XAE_RAF_TXVSTRPMODE_SHIFT 7 /* Tx strip mode shift bits*/
  166. #define XAE_RAF_RXVSTRPMODE_SHIFT 9 /* Rx Strip mode shift bits*/
  167. /* Bit Masks for Axi Ethernet TPF and IFGP registers */
  168. #define XAE_TPF_TPFV_MASK 0x0000FFFF /* Tx pause frame value */
  169. /* Transmit inter-frame gap adjustment value */
  170. #define XAE_IFGP0_IFGP_MASK 0x0000007F
  171. /* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply
  172. * for all 3 registers.
  173. */
  174. /* Hard register access complete */
  175. #define XAE_INT_HARDACSCMPLT_MASK 0x00000001
  176. /* Auto negotiation complete */
  177. #define XAE_INT_AUTONEG_MASK 0x00000002
  178. #define XAE_INT_RXCMPIT_MASK 0x00000004 /* Rx complete */
  179. #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
  180. #define XAE_INT_RXFIFOOVR_MASK 0x00000010 /* Rx fifo overrun */
  181. #define XAE_INT_TXCMPIT_MASK 0x00000020 /* Tx complete */
  182. #define XAE_INT_RXDCMLOCK_MASK 0x00000040 /* Rx Dcm Lock */
  183. #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
  184. #define XAE_INT_PHYRSTCMPLT_MASK 0x00000100 /* Phy Reset complete */
  185. #define XAE_INT_ALL_MASK 0x0000003F /* All the ints */
  186. /* INT bits that indicate receive errors */
  187. #define XAE_INT_RECV_ERROR_MASK \
  188. (XAE_INT_RXRJECT_MASK | XAE_INT_RXFIFOOVR_MASK)
  189. /* Bit masks for Axi Ethernet VLAN TPID Word 0 register */
  190. #define XAE_TPID_0_MASK 0x0000FFFF /* TPID 0 */
  191. #define XAE_TPID_1_MASK 0xFFFF0000 /* TPID 1 */
  192. /* Bit masks for Axi Ethernet VLAN TPID Word 1 register */
  193. #define XAE_TPID_2_MASK 0x0000FFFF /* TPID 0 */
  194. #define XAE_TPID_3_MASK 0xFFFF0000 /* TPID 1 */
  195. /* Bit masks for Axi Ethernet RCW1 register */
  196. #define XAE_RCW1_RST_MASK 0x80000000 /* Reset */
  197. #define XAE_RCW1_JUM_MASK 0x40000000 /* Jumbo frame enable */
  198. /* In-Band FCS enable (FCS not stripped) */
  199. #define XAE_RCW1_FCS_MASK 0x20000000
  200. #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
  201. #define XAE_RCW1_VLAN_MASK 0x08000000 /* VLAN frame enable */
  202. /* Length/type field valid check disable */
  203. #define XAE_RCW1_LT_DIS_MASK 0x02000000
  204. /* Control frame Length check disable */
  205. #define XAE_RCW1_CL_DIS_MASK 0x01000000
  206. /* Pause frame source address bits [47:32]. Bits [31:0] are
  207. * stored in register RCW0
  208. */
  209. #define XAE_RCW1_PAUSEADDR_MASK 0x0000FFFF
  210. /* Bit masks for Axi Ethernet TC register */
  211. #define XAE_TC_RST_MASK 0x80000000 /* Reset */
  212. #define XAE_TC_JUM_MASK 0x40000000 /* Jumbo frame enable */
  213. /* In-Band FCS enable (FCS not generated) */
  214. #define XAE_TC_FCS_MASK 0x20000000
  215. #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
  216. #define XAE_TC_VLAN_MASK 0x08000000 /* VLAN frame enable */
  217. /* Inter-frame gap adjustment enable */
  218. #define XAE_TC_IFG_MASK 0x02000000
  219. /* Bit masks for Axi Ethernet FCC register */
  220. #define XAE_FCC_FCRX_MASK 0x20000000 /* Rx flow control enable */
  221. #define XAE_FCC_FCTX_MASK 0x40000000 /* Tx flow control enable */
  222. /* Bit masks for Axi Ethernet EMMC register */
  223. #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
  224. #define XAE_EMMC_RGMII_MASK 0x20000000 /* RGMII mode enable */
  225. #define XAE_EMMC_SGMII_MASK 0x10000000 /* SGMII mode enable */
  226. #define XAE_EMMC_GPCS_MASK 0x08000000 /* 1000BaseX mode enable */
  227. #define XAE_EMMC_HOST_MASK 0x04000000 /* Host interface enable */
  228. #define XAE_EMMC_TX16BIT 0x02000000 /* 16 bit Tx client enable */
  229. #define XAE_EMMC_RX16BIT 0x01000000 /* 16 bit Rx client enable */
  230. #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
  231. #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
  232. #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
  233. /* Bit masks for Axi Ethernet PHYC register */
  234. #define XAE_PHYC_SGMIILINKSPEED_MASK 0xC0000000 /* SGMII link speed mask*/
  235. #define XAE_PHYC_RGMIILINKSPEED_MASK 0x0000000C /* RGMII link speed */
  236. #define XAE_PHYC_RGMIIHD_MASK 0x00000002 /* RGMII Half-duplex */
  237. #define XAE_PHYC_RGMIILINK_MASK 0x00000001 /* RGMII link status */
  238. #define XAE_PHYC_RGLINKSPD_10 0x00000000 /* RGMII link 10 Mbit */
  239. #define XAE_PHYC_RGLINKSPD_100 0x00000004 /* RGMII link 100 Mbit */
  240. #define XAE_PHYC_RGLINKSPD_1000 0x00000008 /* RGMII link 1000 Mbit */
  241. #define XAE_PHYC_SGLINKSPD_10 0x00000000 /* SGMII link 10 Mbit */
  242. #define XAE_PHYC_SGLINKSPD_100 0x40000000 /* SGMII link 100 Mbit */
  243. #define XAE_PHYC_SGLINKSPD_1000 0x80000000 /* SGMII link 1000 Mbit */
  244. /* Bit masks for Axi Ethernet MDIO interface MC register */
  245. #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable */
  246. #define XAE_MDIO_MC_CLOCK_DIVIDE_MAX 0x3F /* Maximum MDIO divisor */
  247. /* Bit masks for Axi Ethernet MDIO interface MCR register */
  248. #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
  249. #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
  250. #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
  251. #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
  252. #define XAE_MDIO_MCR_OP_MASK 0x0000C000 /* Operation Code Mask */
  253. #define XAE_MDIO_MCR_OP_SHIFT 13 /* Operation Code Shift */
  254. #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
  255. #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
  256. #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
  257. #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
  258. /* Bit masks for Axi Ethernet MDIO interface MIS, MIP, MIE, MIC registers */
  259. #define XAE_MDIO_INT_MIIM_RDY_MASK 0x00000001 /* MIIM Interrupt */
  260. /* Bit masks for Axi Ethernet UAW1 register */
  261. /* Station address bits [47:32]; Station address
  262. * bits [31:0] are stored in register UAW0
  263. */
  264. #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
  265. /* Bit masks for Axi Ethernet FMI register */
  266. #define XAE_FMI_PM_MASK 0x80000000 /* Promis. mode enable */
  267. #define XAE_FMI_IND_MASK 0x00000003 /* Index Mask */
  268. #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
  269. /* Defines for different options for C_PHY_TYPE parameter in Axi Ethernet IP */
  270. #define XAE_PHY_TYPE_MII 0
  271. #define XAE_PHY_TYPE_GMII 1
  272. #define XAE_PHY_TYPE_RGMII_1_3 2
  273. #define XAE_PHY_TYPE_RGMII_2_0 3
  274. #define XAE_PHY_TYPE_SGMII 4
  275. #define XAE_PHY_TYPE_1000BASE_X 5
  276. /* Total number of entries in the hardware multicast table. */
  277. #define XAE_MULTICAST_CAM_TABLE_NUM 4
  278. /* Axi Ethernet Synthesis features */
  279. #define XAE_FEATURE_PARTIAL_RX_CSUM (1 << 0)
  280. #define XAE_FEATURE_PARTIAL_TX_CSUM (1 << 1)
  281. #define XAE_FEATURE_FULL_RX_CSUM (1 << 2)
  282. #define XAE_FEATURE_FULL_TX_CSUM (1 << 3)
  283. #define XAE_NO_CSUM_OFFLOAD 0
  284. #define XAE_FULL_CSUM_STATUS_MASK 0x00000038
  285. #define XAE_IP_UDP_CSUM_VALIDATED 0x00000003
  286. #define XAE_IP_TCP_CSUM_VALIDATED 0x00000002
  287. #define DELAY_OF_ONE_MILLISEC 1000
  288. /**
  289. * struct axidma_bd - Axi Dma buffer descriptor layout
  290. * @next: MM2S/S2MM Next Descriptor Pointer
  291. * @reserved1: Reserved and not used
  292. * @phys: MM2S/S2MM Buffer Address
  293. * @reserved2: Reserved and not used
  294. * @reserved3: Reserved and not used
  295. * @reserved4: Reserved and not used
  296. * @cntrl: MM2S/S2MM Control value
  297. * @status: MM2S/S2MM Status value
  298. * @app0: MM2S/S2MM User Application Field 0.
  299. * @app1: MM2S/S2MM User Application Field 1.
  300. * @app2: MM2S/S2MM User Application Field 2.
  301. * @app3: MM2S/S2MM User Application Field 3.
  302. * @app4: MM2S/S2MM User Application Field 4.
  303. * @sw_id_offset: MM2S/S2MM Sw ID
  304. * @reserved5: Reserved and not used
  305. * @reserved6: Reserved and not used
  306. */
  307. struct axidma_bd {
  308. u32 next; /* Physical address of next buffer descriptor */
  309. u32 reserved1;
  310. u32 phys;
  311. u32 reserved2;
  312. u32 reserved3;
  313. u32 reserved4;
  314. u32 cntrl;
  315. u32 status;
  316. u32 app0;
  317. u32 app1; /* TX start << 16 | insert */
  318. u32 app2; /* TX csum seed */
  319. u32 app3;
  320. u32 app4;
  321. u32 sw_id_offset;
  322. u32 reserved5;
  323. u32 reserved6;
  324. };
  325. /**
  326. * struct axienet_local - axienet private per device data
  327. * @ndev: Pointer for net_device to which it will be attached.
  328. * @dev: Pointer to device structure
  329. * @phy_dev: Pointer to PHY device structure attached to the axienet_local
  330. * @phy_node: Pointer to device node structure
  331. * @mii_bus: Pointer to MII bus structure
  332. * @mdio_irqs: IRQs table for MDIO bus required in mii_bus structure
  333. * @regs: Base address for the axienet_local device address space
  334. * @dma_regs: Base address for the axidma device address space
  335. * @dma_err_tasklet: Tasklet structure to process Axi DMA errors
  336. * @tx_irq: Axidma TX IRQ number
  337. * @rx_irq: Axidma RX IRQ number
  338. * @phy_type: Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X
  339. * @options: AxiEthernet option word
  340. * @last_link: Phy link state in which the PHY was negotiated earlier
  341. * @features: Stores the extended features supported by the axienet hw
  342. * @tx_bd_v: Virtual address of the TX buffer descriptor ring
  343. * @tx_bd_p: Physical address(start address) of the TX buffer descr. ring
  344. * @rx_bd_v: Virtual address of the RX buffer descriptor ring
  345. * @rx_bd_p: Physical address(start address) of the RX buffer descr. ring
  346. * @tx_bd_ci: Stores the index of the Tx buffer descriptor in the ring being
  347. * accessed currently. Used while alloc. BDs before a TX starts
  348. * @tx_bd_tail: Stores the index of the Tx buffer descriptor in the ring being
  349. * accessed currently. Used while processing BDs after the TX
  350. * completed.
  351. * @rx_bd_ci: Stores the index of the Rx buffer descriptor in the ring being
  352. * accessed currently.
  353. * @max_frm_size: Stores the maximum size of the frame that can be that
  354. * Txed/Rxed in the existing hardware. If jumbo option is
  355. * supported, the maximum frame size would be 9k. Else it is
  356. * 1522 bytes (assuming support for basic VLAN)
  357. * @rxmem: Stores rx memory size for jumbo frame handling.
  358. * @csum_offload_on_tx_path: Stores the checksum selection on TX side.
  359. * @csum_offload_on_rx_path: Stores the checksum selection on RX side.
  360. * @coalesce_count_rx: Store the irq coalesce on RX side.
  361. * @coalesce_count_tx: Store the irq coalesce on TX side.
  362. */
  363. struct axienet_local {
  364. struct net_device *ndev;
  365. struct device *dev;
  366. /* Connection to PHY device */
  367. struct phy_device *phy_dev; /* Pointer to PHY device */
  368. struct device_node *phy_node;
  369. /* MDIO bus data */
  370. struct mii_bus *mii_bus; /* MII bus reference */
  371. int mdio_irqs[PHY_MAX_ADDR]; /* IRQs table for MDIO bus */
  372. /* IO registers, dma functions and IRQs */
  373. void __iomem *regs;
  374. void __iomem *dma_regs;
  375. struct tasklet_struct dma_err_tasklet;
  376. int tx_irq;
  377. int rx_irq;
  378. u32 phy_type;
  379. u32 options; /* Current options word */
  380. u32 last_link;
  381. u32 features;
  382. /* Buffer descriptors */
  383. struct axidma_bd *tx_bd_v;
  384. dma_addr_t tx_bd_p;
  385. struct axidma_bd *rx_bd_v;
  386. dma_addr_t rx_bd_p;
  387. u32 tx_bd_ci;
  388. u32 tx_bd_tail;
  389. u32 rx_bd_ci;
  390. u32 max_frm_size;
  391. u32 rxmem;
  392. int csum_offload_on_tx_path;
  393. int csum_offload_on_rx_path;
  394. u32 coalesce_count_rx;
  395. u32 coalesce_count_tx;
  396. };
  397. /**
  398. * struct axiethernet_option - Used to set axi ethernet hardware options
  399. * @opt: Option to be set.
  400. * @reg: Register offset to be written for setting the option
  401. * @m_or: Mask to be ORed for setting the option in the register
  402. */
  403. struct axienet_option {
  404. u32 opt;
  405. u32 reg;
  406. u32 m_or;
  407. };
  408. /**
  409. * axienet_ior - Memory mapped Axi Ethernet register read
  410. * @lp: Pointer to axienet local structure
  411. * @offset: Address offset from the base address of Axi Ethernet core
  412. *
  413. * Return: The contents of the Axi Ethernet register
  414. *
  415. * This function returns the contents of the corresponding register.
  416. */
  417. static inline u32 axienet_ior(struct axienet_local *lp, off_t offset)
  418. {
  419. return in_be32(lp->regs + offset);
  420. }
  421. /**
  422. * axienet_iow - Memory mapped Axi Ethernet register write
  423. * @lp: Pointer to axienet local structure
  424. * @offset: Address offset from the base address of Axi Ethernet core
  425. * @value: Value to be written into the Axi Ethernet register
  426. *
  427. * This function writes the desired value into the corresponding Axi Ethernet
  428. * register.
  429. */
  430. static inline void axienet_iow(struct axienet_local *lp, off_t offset,
  431. u32 value)
  432. {
  433. out_be32((lp->regs + offset), value);
  434. }
  435. /* Function prototypes visible in xilinx_axienet_mdio.c for other files */
  436. int axienet_mdio_setup(struct axienet_local *lp, struct device_node *np);
  437. int axienet_mdio_wait_until_ready(struct axienet_local *lp);
  438. void axienet_mdio_teardown(struct axienet_local *lp);
  439. #endif /* XILINX_AXI_ENET_H */