davicom.c 5.0 KB

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  1. /*
  2. * drivers/net/phy/davicom.c
  3. *
  4. * Driver for Davicom PHYs
  5. *
  6. * Author: Andy Fleming
  7. *
  8. * Copyright (c) 2004 Freescale Semiconductor, Inc.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the License, or (at your
  13. * option) any later version.
  14. *
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/string.h>
  18. #include <linux/errno.h>
  19. #include <linux/unistd.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/init.h>
  22. #include <linux/delay.h>
  23. #include <linux/netdevice.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/skbuff.h>
  26. #include <linux/spinlock.h>
  27. #include <linux/mm.h>
  28. #include <linux/module.h>
  29. #include <linux/mii.h>
  30. #include <linux/ethtool.h>
  31. #include <linux/phy.h>
  32. #include <asm/io.h>
  33. #include <asm/irq.h>
  34. #include <asm/uaccess.h>
  35. #define MII_DM9161_SCR 0x10
  36. #define MII_DM9161_SCR_INIT 0x0610
  37. #define MII_DM9161_SCR_RMII 0x0100
  38. /* DM9161 Interrupt Register */
  39. #define MII_DM9161_INTR 0x15
  40. #define MII_DM9161_INTR_PEND 0x8000
  41. #define MII_DM9161_INTR_DPLX_MASK 0x0800
  42. #define MII_DM9161_INTR_SPD_MASK 0x0400
  43. #define MII_DM9161_INTR_LINK_MASK 0x0200
  44. #define MII_DM9161_INTR_MASK 0x0100
  45. #define MII_DM9161_INTR_DPLX_CHANGE 0x0010
  46. #define MII_DM9161_INTR_SPD_CHANGE 0x0008
  47. #define MII_DM9161_INTR_LINK_CHANGE 0x0004
  48. #define MII_DM9161_INTR_INIT 0x0000
  49. #define MII_DM9161_INTR_STOP \
  50. (MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \
  51. | MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
  52. /* DM9161 10BT Configuration/Status */
  53. #define MII_DM9161_10BTCSR 0x12
  54. #define MII_DM9161_10BTCSR_INIT 0x7800
  55. MODULE_DESCRIPTION("Davicom PHY driver");
  56. MODULE_AUTHOR("Andy Fleming");
  57. MODULE_LICENSE("GPL");
  58. #define DM9161_DELAY 1
  59. static int dm9161_config_intr(struct phy_device *phydev)
  60. {
  61. int temp;
  62. temp = phy_read(phydev, MII_DM9161_INTR);
  63. if (temp < 0)
  64. return temp;
  65. if (PHY_INTERRUPT_ENABLED == phydev->interrupts)
  66. temp &= ~(MII_DM9161_INTR_STOP);
  67. else
  68. temp |= MII_DM9161_INTR_STOP;
  69. temp = phy_write(phydev, MII_DM9161_INTR, temp);
  70. return temp;
  71. }
  72. static int dm9161_config_aneg(struct phy_device *phydev)
  73. {
  74. int err;
  75. /* Isolate the PHY */
  76. err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE);
  77. if (err < 0)
  78. return err;
  79. /* Configure the new settings */
  80. err = genphy_config_aneg(phydev);
  81. if (err < 0)
  82. return err;
  83. return 0;
  84. }
  85. static int dm9161_config_init(struct phy_device *phydev)
  86. {
  87. int err, temp;
  88. /* Isolate the PHY */
  89. err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE);
  90. if (err < 0)
  91. return err;
  92. switch (phydev->interface) {
  93. case PHY_INTERFACE_MODE_MII:
  94. temp = MII_DM9161_SCR_INIT;
  95. break;
  96. case PHY_INTERFACE_MODE_RMII:
  97. temp = MII_DM9161_SCR_INIT | MII_DM9161_SCR_RMII;
  98. break;
  99. default:
  100. return -EINVAL;
  101. }
  102. /* Do not bypass the scrambler/descrambler */
  103. err = phy_write(phydev, MII_DM9161_SCR, temp);
  104. if (err < 0)
  105. return err;
  106. /* Clear 10BTCSR to default */
  107. err = phy_write(phydev, MII_DM9161_10BTCSR, MII_DM9161_10BTCSR_INIT);
  108. if (err < 0)
  109. return err;
  110. /* Reconnect the PHY, and enable Autonegotiation */
  111. return phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
  112. }
  113. static int dm9161_ack_interrupt(struct phy_device *phydev)
  114. {
  115. int err = phy_read(phydev, MII_DM9161_INTR);
  116. return (err < 0) ? err : 0;
  117. }
  118. static struct phy_driver dm91xx_driver[] = {
  119. {
  120. .phy_id = 0x0181b880,
  121. .name = "Davicom DM9161E",
  122. .phy_id_mask = 0x0ffffff0,
  123. .features = PHY_BASIC_FEATURES,
  124. .flags = PHY_HAS_INTERRUPT,
  125. .config_init = dm9161_config_init,
  126. .config_aneg = dm9161_config_aneg,
  127. .read_status = genphy_read_status,
  128. .ack_interrupt = dm9161_ack_interrupt,
  129. .config_intr = dm9161_config_intr,
  130. .driver = { .owner = THIS_MODULE,},
  131. }, {
  132. .phy_id = 0x0181b8b0,
  133. .name = "Davicom DM9161B/C",
  134. .phy_id_mask = 0x0ffffff0,
  135. .features = PHY_BASIC_FEATURES,
  136. .flags = PHY_HAS_INTERRUPT,
  137. .config_init = dm9161_config_init,
  138. .config_aneg = dm9161_config_aneg,
  139. .read_status = genphy_read_status,
  140. .ack_interrupt = dm9161_ack_interrupt,
  141. .config_intr = dm9161_config_intr,
  142. .driver = { .owner = THIS_MODULE,},
  143. }, {
  144. .phy_id = 0x0181b8a0,
  145. .name = "Davicom DM9161A",
  146. .phy_id_mask = 0x0ffffff0,
  147. .features = PHY_BASIC_FEATURES,
  148. .flags = PHY_HAS_INTERRUPT,
  149. .config_init = dm9161_config_init,
  150. .config_aneg = dm9161_config_aneg,
  151. .read_status = genphy_read_status,
  152. .ack_interrupt = dm9161_ack_interrupt,
  153. .config_intr = dm9161_config_intr,
  154. .driver = { .owner = THIS_MODULE,},
  155. }, {
  156. .phy_id = 0x00181b80,
  157. .name = "Davicom DM9131",
  158. .phy_id_mask = 0x0ffffff0,
  159. .features = PHY_BASIC_FEATURES,
  160. .flags = PHY_HAS_INTERRUPT,
  161. .config_aneg = genphy_config_aneg,
  162. .read_status = genphy_read_status,
  163. .ack_interrupt = dm9161_ack_interrupt,
  164. .config_intr = dm9161_config_intr,
  165. .driver = { .owner = THIS_MODULE,},
  166. } };
  167. module_phy_driver(dm91xx_driver);
  168. static struct mdio_device_id __maybe_unused davicom_tbl[] = {
  169. { 0x0181b880, 0x0ffffff0 },
  170. { 0x0181b8b0, 0x0ffffff0 },
  171. { 0x0181b8a0, 0x0ffffff0 },
  172. { 0x00181b80, 0x0ffffff0 },
  173. { }
  174. };
  175. MODULE_DEVICE_TABLE(mdio, davicom_tbl);