icplus.c 6.2 KB

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  1. /*
  2. * Driver for ICPlus PHYs
  3. *
  4. * Copyright (c) 2007 Freescale Semiconductor, Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. *
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/string.h>
  14. #include <linux/errno.h>
  15. #include <linux/unistd.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/init.h>
  18. #include <linux/delay.h>
  19. #include <linux/netdevice.h>
  20. #include <linux/etherdevice.h>
  21. #include <linux/skbuff.h>
  22. #include <linux/spinlock.h>
  23. #include <linux/mm.h>
  24. #include <linux/module.h>
  25. #include <linux/mii.h>
  26. #include <linux/ethtool.h>
  27. #include <linux/phy.h>
  28. #include <asm/io.h>
  29. #include <asm/irq.h>
  30. #include <asm/uaccess.h>
  31. MODULE_DESCRIPTION("ICPlus IP175C/IP101A/IP101G/IC1001 PHY drivers");
  32. MODULE_AUTHOR("Michael Barkowski");
  33. MODULE_LICENSE("GPL");
  34. /* IP101A/G - IP1001 */
  35. #define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */
  36. #define IP1001_RXPHASE_SEL (1<<0) /* Add delay on RX_CLK */
  37. #define IP1001_TXPHASE_SEL (1<<1) /* Add delay on TX_CLK */
  38. #define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */
  39. #define IP1001_APS_ON 11 /* IP1001 APS Mode bit */
  40. #define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */
  41. #define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */
  42. #define IP101A_G_IRQ_PIN_USED (1<<15) /* INTR pin used */
  43. #define IP101A_G_IRQ_DEFAULT IP101A_G_IRQ_PIN_USED
  44. static int ip175c_config_init(struct phy_device *phydev)
  45. {
  46. int err, i;
  47. static int full_reset_performed;
  48. if (full_reset_performed == 0) {
  49. /* master reset */
  50. err = mdiobus_write(phydev->bus, 30, 0, 0x175c);
  51. if (err < 0)
  52. return err;
  53. /* ensure no bus delays overlap reset period */
  54. err = mdiobus_read(phydev->bus, 30, 0);
  55. /* data sheet specifies reset period is 2 msec */
  56. mdelay(2);
  57. /* enable IP175C mode */
  58. err = mdiobus_write(phydev->bus, 29, 31, 0x175c);
  59. if (err < 0)
  60. return err;
  61. /* Set MII0 speed and duplex (in PHY mode) */
  62. err = mdiobus_write(phydev->bus, 29, 22, 0x420);
  63. if (err < 0)
  64. return err;
  65. /* reset switch ports */
  66. for (i = 0; i < 5; i++) {
  67. err = mdiobus_write(phydev->bus, i,
  68. MII_BMCR, BMCR_RESET);
  69. if (err < 0)
  70. return err;
  71. }
  72. for (i = 0; i < 5; i++)
  73. err = mdiobus_read(phydev->bus, i, MII_BMCR);
  74. mdelay(2);
  75. full_reset_performed = 1;
  76. }
  77. if (phydev->addr != 4) {
  78. phydev->state = PHY_RUNNING;
  79. phydev->speed = SPEED_100;
  80. phydev->duplex = DUPLEX_FULL;
  81. phydev->link = 1;
  82. netif_carrier_on(phydev->attached_dev);
  83. }
  84. return 0;
  85. }
  86. static int ip1xx_reset(struct phy_device *phydev)
  87. {
  88. int bmcr;
  89. /* Software Reset PHY */
  90. bmcr = phy_read(phydev, MII_BMCR);
  91. if (bmcr < 0)
  92. return bmcr;
  93. bmcr |= BMCR_RESET;
  94. bmcr = phy_write(phydev, MII_BMCR, bmcr);
  95. if (bmcr < 0)
  96. return bmcr;
  97. do {
  98. bmcr = phy_read(phydev, MII_BMCR);
  99. if (bmcr < 0)
  100. return bmcr;
  101. } while (bmcr & BMCR_RESET);
  102. return 0;
  103. }
  104. static int ip1001_config_init(struct phy_device *phydev)
  105. {
  106. int c;
  107. c = ip1xx_reset(phydev);
  108. if (c < 0)
  109. return c;
  110. /* Enable Auto Power Saving mode */
  111. c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2);
  112. if (c < 0)
  113. return c;
  114. c |= IP1001_APS_ON;
  115. c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c);
  116. if (c < 0)
  117. return c;
  118. if (phy_interface_is_rgmii(phydev)) {
  119. c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
  120. if (c < 0)
  121. return c;
  122. c &= ~(IP1001_RXPHASE_SEL | IP1001_TXPHASE_SEL);
  123. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
  124. c |= (IP1001_RXPHASE_SEL | IP1001_TXPHASE_SEL);
  125. else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
  126. c |= IP1001_RXPHASE_SEL;
  127. else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
  128. c |= IP1001_TXPHASE_SEL;
  129. c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
  130. if (c < 0)
  131. return c;
  132. }
  133. return 0;
  134. }
  135. static int ip101a_g_config_init(struct phy_device *phydev)
  136. {
  137. int c;
  138. c = ip1xx_reset(phydev);
  139. if (c < 0)
  140. return c;
  141. /* INTR pin used: speed/link/duplex will cause an interrupt */
  142. c = phy_write(phydev, IP101A_G_IRQ_CONF_STATUS, IP101A_G_IRQ_DEFAULT);
  143. if (c < 0)
  144. return c;
  145. /* Enable Auto Power Saving mode */
  146. c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
  147. c |= IP101A_G_APS_ON;
  148. return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
  149. }
  150. static int ip175c_read_status(struct phy_device *phydev)
  151. {
  152. if (phydev->addr == 4) /* WAN port */
  153. genphy_read_status(phydev);
  154. else
  155. /* Don't need to read status for switch ports */
  156. phydev->irq = PHY_IGNORE_INTERRUPT;
  157. return 0;
  158. }
  159. static int ip175c_config_aneg(struct phy_device *phydev)
  160. {
  161. if (phydev->addr == 4) /* WAN port */
  162. genphy_config_aneg(phydev);
  163. return 0;
  164. }
  165. static int ip101a_g_ack_interrupt(struct phy_device *phydev)
  166. {
  167. int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
  168. if (err < 0)
  169. return err;
  170. return 0;
  171. }
  172. static struct phy_driver icplus_driver[] = {
  173. {
  174. .phy_id = 0x02430d80,
  175. .name = "ICPlus IP175C",
  176. .phy_id_mask = 0x0ffffff0,
  177. .features = PHY_BASIC_FEATURES,
  178. .config_init = &ip175c_config_init,
  179. .config_aneg = &ip175c_config_aneg,
  180. .read_status = &ip175c_read_status,
  181. .suspend = genphy_suspend,
  182. .resume = genphy_resume,
  183. .driver = { .owner = THIS_MODULE,},
  184. }, {
  185. .phy_id = 0x02430d90,
  186. .name = "ICPlus IP1001",
  187. .phy_id_mask = 0x0ffffff0,
  188. .features = PHY_GBIT_FEATURES | SUPPORTED_Pause |
  189. SUPPORTED_Asym_Pause,
  190. .config_init = &ip1001_config_init,
  191. .config_aneg = &genphy_config_aneg,
  192. .read_status = &genphy_read_status,
  193. .suspend = genphy_suspend,
  194. .resume = genphy_resume,
  195. .driver = { .owner = THIS_MODULE,},
  196. }, {
  197. .phy_id = 0x02430c54,
  198. .name = "ICPlus IP101A/G",
  199. .phy_id_mask = 0x0ffffff0,
  200. .features = PHY_BASIC_FEATURES | SUPPORTED_Pause |
  201. SUPPORTED_Asym_Pause,
  202. .flags = PHY_HAS_INTERRUPT,
  203. .ack_interrupt = ip101a_g_ack_interrupt,
  204. .config_init = &ip101a_g_config_init,
  205. .config_aneg = &genphy_config_aneg,
  206. .read_status = &genphy_read_status,
  207. .suspend = genphy_suspend,
  208. .resume = genphy_resume,
  209. .driver = { .owner = THIS_MODULE,},
  210. } };
  211. module_phy_driver(icplus_driver);
  212. static struct mdio_device_id __maybe_unused icplus_tbl[] = {
  213. { 0x02430d80, 0x0ffffff0 },
  214. { 0x02430d90, 0x0ffffff0 },
  215. { 0x02430c54, 0x0ffffff0 },
  216. { }
  217. };
  218. MODULE_DEVICE_TABLE(mdio, icplus_tbl);